DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claims because the examined application claim is either anticipated by, or would have been obvious over, the reference claims.
Claims 1 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,141,683. Although the claims at issue are not identical, they are not patentably distinct from each other because the present ‘748 application simply claims a broader scope from the ‘683 patent.
Application ‘748
Patent ‘683
(claim 1) an apparatus comprising:
(claim 1) an accelerator integrated circuit, comprising:
memory circuitry; and
an array of processing elements PEs, a PE comprising multiply-and-accumulate MAC units and register file RF instances; and
processor circuitry coupled with the memory circuitry, the processor circuitry comprising an array of processing elements PEs,
wherein a PE of the array of PEs includes a plurality of multiply-and-accumulate MAC units and a register file RD comprising a plurality of RF instances,
wherein a RF instance is to store an input activation IF and a weight FL, the IF and the FL are to be fed into a MAC unit of the plurality of MAC units, and the PE is to compute an output activation OF based on the IF and the FL.
(claim 3) a number of RF instances of the plurality of RF instances is equal to a number of MAC units of the plurality of MAC units.
a plurality of buffers associated with the array of PEs, different buffers of the plurality of buffers associated with different subsets of PEs in the array of PEs,
a buffer comprising entries,
(claim 4) a plurality of column buffers, wherein each column buffer of the plurality of column buffers is associated with a column of PEs in the PE array, and
wherein a number of the RF instances is equal to a number of the MAC units and is equal to a number of the entries.
each column buffer comprises a number of entries equal to the number of RF instances.
(claim 5) implement a time-space multiplexing scheme to deliver a number of data units over a load path to each PE of the array of PEs,
Wherein the number of data units is equal to the number of entries of each column buffer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8 and 17-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kesiraju (US 2020/0,272,467).
Referring to claims 1 and 17, Kesiraju discloses an apparatus (fig. 1, apparatus), comprising:
an array of processing elements PEs (fig. 3, processing elements 42), a PE (fig. 12, PE 42) comprising multiply-and-accumulate MAC units (fig. 12, ALU circuit 58) and register file RF instances (fig. 12, Z memory 60; para.0043, Z memory 28 register); and
a plurality of buffers (fig. 12, data buffer 40) associated with the array of PEs, different buffers of the plurality of buffers associated with different subsets of PEs in the array of PEs (fig. 11, data buffer 40; para.0043, X memory 24 register, Y memory 26 register), a buffer comprising entries (para.0043, X memory 24 entry, Y memory 26 entry),
wherein a number (fig. 12, one Z memory 60) of the RF instances is equal to a number (fig. 12, one MAC 58) of the MAC units and is equal to a number (fig. 11, one data buffer 40) of the entries.
As to claims 2 and 19, Kesiraju discloses the apparatus of claim 1, wherein the array of PEs comprises a plurality of columns of PEs (fig. 3, columns X1~X7), and a subset of PEs (fig. 4, columns of PEs) in the array of PEs is a column of PEs.
As to claim 3, Kesiraju discloses the apparatus of claim 1, wherein a first RF instance (fig. 5, Z memory 60, PE 42 in PE group 50) of the RF instances is associated with a different read port or a different write port from a second RF instances (fig. 5, Z memory 60, PE 42 in PE group 50) of the RF instances.
As to claim 4, Kesiraju discloses the apparatus of claim 1, comprising a multiplexer (para.0103, multiplexors) to deliver data (para.0103, data) to the PE.
As to claim 5, Kesiraju discloses the apparatus of claim 4, wherein the data comprises data units (para.0103, data subset), and a number of the data units (fig. 5, PE group 50) is equal to the number of the MAC units.
As to claims 8 and 20, Kesiraju discloses the apparatus of claim 1, wherein the PE comprises an adder (fig. 5, adder 64) to accumulate products computed by the MAC units.
As to claim 18, Kesiraju discloses the apparatus of claim 17, wherein the memory is a first chip (fig. 18, external memory), and the array of PEs or the plurality of buffers is in a second chip (fig. 18, IC 202).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kesiraju in view of Kang (US 10,698,657).
As to claim 6, Kesiraju discloses the apparatus of claim 1.
Kang discloses a RF instance (fig. 8, activation queue 110) is to store an input activation (11:36-67, input vector X) and a weight (11:36-67, weight matrix W), the input activation and the weight are to be fed into a MAC unit (fig. 7, ALU) of the MAC units, and the PE is to compute an output activation (fig. 7, output Y; fig. 10) from the input activation and the weight.
Kesiraju and Kang are analogous art because they are from the same field of endeavor in hardware accelerator. Before the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kesiraju and Kang before him or her to modify the processing elements of Kesiraju to include the neural network matrix-vector operations of Kang, thereafter the array of PEs implements neural network operations through the hardware accelerator. The suggestion and/or motivation for doing so would be obtaining the advantage of improved computing efficiency and resource utilization (12:30-51) as suggested by Kang. Therefore, it would have been obvious to combine Kesiraju with Kang to obtain the invention as specified in the instant application claims.
As to claim 7, Kesiraju discloses the apparatus of claim 6,
Kang discloses another MAC unit (fig. 7, ALU) of the MAC units is to receive another input activation (11:36-67, input vector X) and another weight (11:36-67, weight matrix W). (See TSM analysis above)
As to claim 9, Kesiraju discloses the apparatus of claim 1, wherein the MAC units are to operate in parallel (para.0051, parallel).
Kang discloses different ones of the MAC unit are configured to perform computations on weights in different output channels (fig. 7, PE0~PEN, N+1 channels). (See TSM analysis above)
As to claim 10, Kesiraju discloses the apparatus of claim 1.
Kang discloses the MAC units are to perform computations on input activations and weights (fig. 7, activation queue 110, ptrread 120), and a MAC unit is to be activated or deactivated based on sparsity information (2:41-49, sparse matrix) of the input activations or weights. (See TSM analysis above)
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See M.P.E.P 707.05(c).
US 10,698,730 discloses neural network processor with array of processing elements having register files and buffers.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
