DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 07/20/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent # 12112891 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments
Applicant’s arguments, filed 07/20/2026, with respect to the rejection of claims 1-21 have been fully considered and are persuasive. The rejection of claims 1-21 has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al (US 2015/0243438).
Regarding claim 23, Ahn discloses a multilayer capacitor (Figs. 13-14, 1000) comprising: a main body (Figs. 13-14, 1100) containing a set of alternating dielectric layers (Figs. 13-14, 1110 near 1120) and internal electrode layers (Figs. 13-14, 1200/1300 near 1120) the set of alternating dielectric layers and internal electrode layers containing a first internal electrode layer (Figs. 13-14, 1200) and a second internal electrode layer (Figs. 13-14, 1300), each internal electrode layer including a top edge (Figs. 13-14, top of 1200/1300), a bottom edge (Figs. 13-14, bottom of 1200/1300) opposite the top edge, and two side edges (Figs. 13-14, left and right of 1200-1300) extending between the top edge and the bottom edge that define a main body of the internal electrode layer (Figs. 13-14), each internal electrode layer containing at least one lead tab (Figs. 13-14, 1230/1330) extending from the top edge of the main body of the internal electrode layer and at least one lead tab (Figs. 13-14, 1210/1310) extending from the bottom edge of the main body of the internal electrode layer, external terminals (Figs. 13-14, 1410-1480) electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor (Figs. 13-14), wherein the top surface of the capacitor is bounded by four top edges (Fig. 5, four sides on top) and the bottom surface of the capacitor is bounded by four bottom edges (Fig. 5, four sides on bottom), and wherein the external terminals are spaced apart from each of the four top edges on the top surface of the capacitor and each of the four bottom edges on the bottom surface of the capacitor (Fig. 5, electrodes on top and bottom are spaced from sides).
Allowable Subject Matter
Claims 1-8, 10-11, 13-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, the prior art fails to teach or suggest, alone or in combination:
A multilayer capacitor comprising: a main body containing a set of alternating dielectric layers and internal electrode layers, the set of alternating dielectric layers and internal electrode layers containing a first internal electrode layer and a second internal electrode layer, each internal electrode layer including a top edge, a bottom edge opposite the top edge, and a first side edge and a second side edge extending between the top edge and the bottom edge that define a main body of the internal electrode layer, each internal electrode layer containing at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, wherein the at least one lead tab extending from the top edge of the main body of the internal electrode layer is offset from the first side edge of the main body of the internal electrode layer by an offset distance and from the second side edge of the main body by a second distance, wherein the at least one lead tab extending from the bottom edge of the main body of the internal electrode layer is offset from the first side edge of the main body of the internal electrode layer by the offset distance and from the second side edge of the main body by the second distance, wherein the second distance is greater than the offset distance, and wherein each lead tab of each internal electrode layer is offset from both the first side edge and the second side edge; and external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor.
Specifically, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the at least one lead tab extending from the top edge of the main body of the internal electrode layer is offset from the first side edge of the main body of the internal electrode layer by an offset distance and from the second side edge of the main body by a second distance, wherein the at least one lead tab extending from the bottom edge of the main body of the internal electrode layer is offset from the first side edge of the main body of the internal electrode layer by the offset distance and from the second side edge of the main body by the second distance, wherein the second distance is greater than the offset distance” in combination with the other claim limitations.
Regarding independent claim 22, the prior art fails to teach or suggest, alone or in combination:
A component, comprising: a multilayer capacitor comprising: a main body containing a set of alternating dielectric layers and internal electrode layers, the set of alternating dielectric layers and internal electrode layers containing a first internal electrode layer and a second internal electrode layer, each internal electrode layer including a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer, each internal electrode layer containing at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor; a circuit board including the multilayer capacitor positioned on the circuit board; and an integrated circuit package, wherein the capacitor is positioned between the circuit board and the integrated circuit package in a vertical direction such that the circuit board, the capacitor, and the integrated circuit package are present in a stacked arrangement, and wherein the capacitor is directly connected to the circuit board and the integrated circuit package.
Specifically, the prior art fails to teach or make obvious, alone or in combination, the limitation of “the integrated circuit package are present in a stacked arrangement, and wherein the capacitor is directly connected to the circuit board and the integrated circuit package” in combination with the other claim limitations.
Additional Relevant Prior Art:
Ahiko et al (US 6292351) Figs. 1-4.
Randall et al (US 7545623) Figs. 3-6.
Galvagni et al (US 2010/0188799) Fig. 1-14.
Hwang et al (US 2015/0294791) teaches relevant art in Fig. 2A.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL P MCFADDEN/ Primary Examiner, Art Unit 2847
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