DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,500,4481. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent No. 11,500,448 anticipate claims 21-40 of the current application. Specifically, claims 1-20 of U.S. Patent No. 11,500,448 disclose all claimed limitations of claims 21-40 of the current invention and also disclose additional subject matter related to an ambient sensor and modifying frame brightness. Since the subject matter of claims 21-40 of the claimed invention is a subset of the subject matter of claims 1-20 of U.S. Patent No. 11,500,448, claims 21-40 of the current application are anticipated by claims 1-20 of U.S. Patent No. 11,500,448.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,822,4162. Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 13, 16 and 20 of U.S. Patent No. 11,822,416 disclose all limitations of claims 21, 34 and 39 of the claimed invention. Claims 2-12, 15, 18 and 19 of U.S. Patent No. 11,822,416 disclose the subject matter of claims 22-33, 35-38 and 40. It would have been obvious to one of ordinary skill in the art to combine the subject matter of claims 2-12, 15, 18 and 19 of U.S. Patent No. 11,822,416 with claims 13, 16 and 20 of U.S. Patent No. 11,822,416 since the claims are directed to the similar subject matter of frame displaying systems that include display controllers that are operated when processor circuitry is powered down.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,141,016. Although the claims at issue are not identical, they are not patentably distinct from each other. Claim 13 of U.S. Patent No. 12,141,016 disclose all limitations of claims 21, 34 and 39 of the claimed invention. Claims 2-12, 14-16 and 18-19 of U.S. Patent No. 12,141,016 disclose the subject matter of claims 22-33, 35-38 and 40. It would have been obvious to one of ordinary skill in the art to combine the subject matter of claims 2-12, 14-16 and 18-19 of U.S. Patent No. 12,141,016 with claims 13, 16 and 20 of U.S. Patent No. 12,141,016 since the claims are directed to the similar subject matter of frame displaying systems that include display controllers that are operated when processor circuitry is powered down.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 25, 26 and 28-40 are rejected under 35 U.S.C. 103 as being unpatentable over Tripathi, US Patent Application Publication no. 2015/03629803, in view of Vaz Waddington, US Patent Application Publication no. 2015/01873394.
Regarding claims 21, 32-34 and 39, Tripathi discloses a wearable device [smart watches or wearable electronics, paragraph 0004], comprising:
processor circuitry configured to store frames in a memory for display [CPU processors assign work to peripheral components by writing data to memory before powering down, paragraphs 0024, 0035, 0039 and 0067-0069];
display controller circuitry configured to read frames from the memory and process the frames for display on a display device [display controller, paragraphs 0039 and 0067-0069];
interconnect circuitry coupled to the display controller circuitry and the processor circuitry, and memory controller circuitry for the memory [communication fabric 27 in Figure 1 and paragraph 0021];
one or more sensors [timer or sensors, paragraphs 0025, 0026 and 0046];
power management circuitry [PMGR and Always-ON in Figure 1] configured to operate the device in:
a first power state, in which: at least a portion of the processor circuitry is powered down and the processor circuitry is not configured to provide frames to the memory; and the display controller circuitry is configured to: read multiple frames from the memory via the interconnect circuitry; and display the multiple frames on the display device [the display controller reads frame data and displays the frames on a display device when the CPU processors are powered down, paragraphs 0062, 0067-0069 and 0074]; and
a second power state, in which: the display controller is not powered; and in response to a measurement by the one or more sensors, the power management circuitry is configured to transition to the first power state [the display controller is powered down and subsequently awakened in response to timer or sensor outputs to display frame data, paragraphs 0046, 0062, 0070 and 0074].
Tripathi does not disclose that the frames displayed by the display controller are prerendered. Like Tripathi, Vaz Waddington discloses a device that performs display related operations in a plurality of device power modes. Specifically, Vaz Waddington discloses a power conserving display process in which a low-power display processor is used to display prerendered frames while an application processor (which includes full graphics rendering capabilities) is powered down [paragraphs 0015, 0020-0021 and 0036]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the Vaz Waddington teachings to the Tripathi system by including a low-power display processor to cause display of prerendered images while the higher power consuming display controller is powered down in order to reduce system power consumption [Vaz Waddington, paragraph 0015].
Regarding claims 22, 35 and 40, Tripathi further discloses that the display controller circuitry, is configured to, in the first power state, adjust one or more display parameters based on the measurement, wherein the display parameters control display of the multiple prerendered frames [the display controller may display an image that is changed to reflect the current time when the device is in the first power state, paragraph 0074].
Regarding claim 23, Tripathi further discloses that the one or more sensors include an ambient light sensor [photodetector that detects light, paragraph 0026].
Regarding claim 25, Tripathi further discloses that the one or more sensors include an audio input sensor [microphone, paragraph 0026].
Regarding claim 26, Tripathi further discloses that the one or more sensors include at least one sensor of the following sensors: accelerometer, gyroscope magnetometer, altimeter, temperature sensor; and pressure sensor [accelerometer, gyroscope, magnetometer, altimeter, temperature sensor and pressure sensor in paragraph 0026].
Regarding claim 28, Tripathi further discloses that the one or more sensors include a biometric sensor [user interface device, such as a button, a touchscreen or camera, paragraph 0026].
Regarding claims 29 and 36, Tripathi further discloses buffer circuitry configured to store the measurement in the second power state [the always-on component buffers sensor data while the rest of the device is powered down, paragraph 0027].
Regarding claims 30 and 37, Tripathi further discloses that the processor circuitry is configured to store multiple prerendered images representing respective potential dynamic content in the memory; and the display controller circuitry is configured to: in the first power state, select one or more prerendered images based on the measurement; and combine the one or more prerendered images with a prerendered frame to modify the frame [the display controller may display an image that is changed to reflect the current time when the device is in the first power state, paragraph 0074].
Regarding claims 31 and 38, Tripathi further discloses that the display controller circuitry is configured to power down, in the first power state, between display of one or more of the multiple prerendered frames [the display controller is powered down and subsequently awakened in response to timer or sensor outputs to display frame data, paragraphs 0046, 0062, 0070 and 0074].
Claims 24 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Tripathi, US Patent Application Publication no. 2015/0362980 and Vaz Waddington, US Patent Application Publication no. 2015/0187339, in view of Takeda, US Patent Application Publication no. 2015/0054814.
Tripathi further discloses powering up a display controller to display the current time on a display according to a timer [paragraphs 0046, 0062, 0070 and 0074]. Tripathi and Vaz Waddington do not disclose that the display controller also is used to display wireless signal strength and batter level information. Like Tripathi and Vaz Waddington, Takeda discloses a computing device that is operable to display information is a plurality of different power modes. Specifically, Takeda discloses that wireless signal strength and remaining battery level information may be displayed in addition to the current time when the computing device is in a low power consuming mode [paragraphs 0016 and 0017]. Since it was known in the art before the effective filing date of the claimed invention to display wireless signal strength and remaining battery level information in addition to the current time while in a low power mode, it would have been obvious to one of ordinary skill in the art to apply the Tripathi and Vaz Waddington teachings to known computing devices that display wireless signal strength and remaining battery level information while in a low power mode in order to further conserve energy [Tripathi, paragraph 0006].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL B YANCHUS III whose telephone number is (571)272-3678. The examiner can normally be reached Monday-Friday 9am-5pm.
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/PAUL B YANCHUS III/Primary Examiner, Art Unit 2115 September 18, 2026
1 U.S. Patent No. 11,500,448 was cited in the 10/7/24 IDS.
2 U.S. Patent No. 11,822,416 was cited in the 10/7/24 IDS.
3 Tripathi was cited in the 10/7/24 IDS.
4 Vaz Waddington was cited in the 10/7/24 IDS.
Prosecution Insights