Prosecution Insights
Last updated: October 02, 2026
Application No. 18/908,068

A LEVEL SHIFTER CIRCUIT

Final Rejection §112
Filed
Oct 07, 2024
Priority
Jul 16, 2024 — IN 202441054390
Examiner
YEAMAN, JAMES G
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
95 granted / 115 resolved
+14.6% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
14 currently pending
Career history
143
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
66.5%
+26.5% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 115 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1 and 11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 discloses “wherein the first MOS device is configured to generate a first resistance path to bypass a second resistance path generated by the p-type transistor of the left branch of the voltage level shifter block.”. Figure 3 teaches the first MOS device bypassing transistor block 314, not the p-type transistor 310. Applicants disclosure does not support the claimed limitation. Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 discloses “bypassing, by the first resistance path generated by the first MOS device, the second resistance path generated by the p-type transistor of a left branch of the voltage level shifter block to provide a current path for the current mirror block.”. Figure 3 teaches the first MOS device bypassing transistor block 314, not the p-type transistor 310. Applicants disclosure does not support the claimed limitation. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 11 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Claims 1 discloses “A level shifter circuit comprising … a left branch…” A branch is typically defined by a path between two endpoints but it is unclear what that path is based on (e.g., whether the left branch is between 304 and 306 or 310-308-312 as indicated by the dashed lines). If the left branch is from 304 to 306, then "a second resistance path generated by the p-type transistor of the left branch" is not supported by Applicant's disclosure. if the left branch corresponds to 320 of Applicant's Fig 3, then "the current generation block of the left branch" is not supported by applicants disclosure. Claims 11 discloses “A method to shift a level of a voltage in a level shifter circuit, the method comprising … a left branch…” A branch is typically defined by a path between two endpoints but it is unclear what that path is based on (e.g., whether the left branch is between 304 and 306 or 310-308-312 as indicated by the dashed lines). If the left branch is from 304 to 306, then "a second resistance path generated by the p-type transistor of the left branch" is not supported by Applicant's disclosure. if the left branch corresponds to 320 of Applicant's Fig 3, then "the current generation block of the left branch" is not supported by applicants disclosure. Claims 19 discloses “A level shifter circuit comprising … a left branch…” A branch is typically defined by a path between two endpoints but it is unclear what that path is based on (e.g., whether the left branch is between 304 and 306 or 310-308-312 as indicated by the dashed lines). If the left branch is from 304 to 306, then "a second resistance path generated by the p-type transistor of the left branch" is not supported by Applicant's disclosure. if the left branch corresponds to 320 of Applicant's Fig 3, then "the current generation block of the left branch" is not supported by applicants disclosure. Claims 1 and 19 recites the limitation "the current generation block of the left branch" in line 10. There is insufficient antecedent basis for this limitation in the claim. Allowable Subject Matter Claims 1-14 and 16-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES G YEAMAN/Examiner, Art Unit 2836 /TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Show 1 earlier event
Feb 05, 2026
Non-Final Rejection mailed — §112
Apr 07, 2026
Interview Requested
Apr 23, 2026
Applicant Interview (Telephonic)
Apr 23, 2026
Examiner Interview Summary
Jun 12, 2026
Response Filed
Aug 25, 2026
Final Rejection mailed — §112
Sep 13, 2026
Interview Requested
Sep 28, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12726181
CLOCK GENERATION CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS
4y 12m to grant Granted Sep 01, 2026
Patent 12726187
SIGNAL TRANSMISSION DEVICE AND SIGNAL TRANSMISSION SYSTEM
1y 11m to grant Granted Sep 01, 2026
Patent 12712534
LEVEL SHIFTER AND MEMORY DEVICE INCLUDING THE SAME
2y 4m to grant Granted Aug 18, 2026
Patent 12695458
DELAY LOCKED LOOP CIRCUIT
1y 10m to grant Granted Jul 28, 2026
Patent 12695447
FAULT PROTECTION IN SWITCH DRIVER UNITS
1y 11m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
90%
With Interview (+6.9%)
2y 7m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 115 resolved cases by this examiner. Grant probability derived from career allowance rate.

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