Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1a – 1c should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "-- the p-type transistor block --" in – line 16 --. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "-- the p-type transistor block --" in – line 1 --. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "-- the p-type transistor block --" in – line 2 --. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8, 11 – 14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Neugebauer et al. (US 11979154 B1 and Neugebauer hereinafter.) in view of Ko et al. (US 20190173455 A1 and Ko hereinafter.).
Regarding claim 1, Neugebauer discloses a level shifter circuit [fig. 8] comprising: a p-type transistor [60]; a first metal-oxide semiconductor (MOS) device [59] connected to the p-type transistor [as shown]; a voltage level shifter block comprising: a current mirror block [39 and 40], wherein the first MOS device is connected to the current mirror block at a left branch [a node between 59 and 39/40] of the voltage level shifter block, a current generation block [52 and 51], a transistor block [42, 43], and a second MOS device [48] connected to the transistor block [as shown] and to the current generation block [as shown] of the left branch and a source terminal of the first MOS device is connected to a drain terminal of the second MOS device [as shown]; a p-type transistor logic block [44] connected to an N-side final output [node 64] of the voltage level shifter block, wherein the p-type transistor block is configured to receive an input from the left branch [44 accepting input at 47]. Neugebauer does not explicitly disclose a gate terminal of the second MOS device is connected to a final output of the level shifter circuit and an n-type transistor block connected at a right branch of the level shifter circuit, wherein the n-type transistor block is configured to receive an input from the N-side final output of the level shifter circuit.
However, Ko discloses [fig. 4] a gate terminal of the second MOS device [510c] is connected to a final output of the level shifter circuit [Y output] and an n-type transistor block [110c] connected at a right branch of the level shifter circuit, wherein the n-type transistor block is configured to receive an input from the N-side final output of the level shifter circuit [410c providing Y output]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Neugebauer to include a gate terminal of the second MOS device is connected to a final output of the level shifter circuit and an n-type transistor block connected at a right branch of the level shifter circuit, wherein the n-type transistor block is configured to receive an input from the N-side final output of the level shifter circuit as taught by Ko to improve duty ratio and distortion in a circuit.
Regarding claim 2, Neugebauer in view of Ko discloses further the level shifter circuit is a single stage level shifter circuit [as shown]. Neugebauer in view of Ko does not explicitly disclose wherein the level shifter circuit is configured to tolerate a high voltage over a frequency range. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the level shifter circuit is configured to tolerate a high voltage over a frequency range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, Neugebauer in view of Ko discloses further wherein the p-type transistor block is connected to the N-side final output [as shown], and wherein the p-type transistor block is configured to pull up an n-side of the N-side final output to a supply voltage [Neugebauer, transistors 42-44 activated thereby bringing node 64 up towards node 38].
Regarding claim 11, Neugebauer discloses method to shift a level of a voltage in a level shifter circuit [fig. 5], the method comprising: generating a first low resistance path [current through 59], by a first metal oxide semiconductor (MOS) device [59], through the first MOS device from a p-type transistor [transistors within 540c] connected to a current generation block [52 and 51] and to a current mirror block [39 and 40], thereby strengthening the current mirror block [increase in current], wherein a voltage level shifter block comprises the current mirror block [as shown]. Neugebauer does not explicitly disclose generating a second low resistance path via a connection of a final output of the level shifter circuit to a gate terminal of a second MOS device to drive, the current mirror block up to a maximum capacity; receiving a first feedback, provided by the second low resistance path connected to a p-type transistor block, wherein the first feedback is configured to boost an n-type feedback voltage to reach a maximum logic level; receiving a second feedback from an n-type transistor block; and generating the final output at high frequencies and over a range of voltages based on the first feedback and the second feedback.
However, Ko discloses generating a second low resistance path [path through 510c] via a connection of a final output [Y output] of the level shifter circuit to a gate terminal of a second MOS device [510c] to drive, the current mirror block [210c] up to a maximum capacity [510c activated thereby lowering resistance through 510c and increasing current]; receiving a first feedback, provided by the second low resistance path connected to a p-type transistor block [410c output Y effected by 510c], wherein the first feedback is configured to boost an n-type feedback voltage (FBN) to reach a maximum logic level [410 output effecting 510c]; receiving a second feedback [540c accepting Y from 410c] from an n-type transistor block [n type transistor within 410c]; and generating the final output at high frequencies and over a range of voltages based on the first feedback and the second feedback [given]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Neugebauer to include generating a second low resistance path via a connection of a final output of the level shifter circuit to a gate terminal of a second MOS device to drive, the current mirror block up to a maximum capacity; receiving a first feedback, provided by the second low resistance path connected to a p-type transistor block, wherein the first feedback is configured to boost an n-type feedback voltage to reach a maximum logic level; receiving a second feedback from an n-type transistor block; and generating the final output at high frequencies and over a range of voltages based on the first feedback and the second feedback as taught by Ko to improve duty ratio and distortion in a circuit.
Regarding claim 12, Neugebauer in view of Ko discloses further wherein the method comprises generating the final output [Ko, Y output]. Neugebauer in view of Ko does not explicitly disclose wherein the final output comprises a high frequency output. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the level shifter circuit is configured to tolerate a high voltage over a frequency range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 13, Neugebauer in view of Ko discloses further wherein the method comprises shifting of a range of core voltage levels [levels at any node] to a range of I/O voltage levels [differing input and output voltages].
Regarding claim 14, Neugebauer in view of Ko discloses further wherein the method comprises operating the level shifter circuit as a single stage level shifter circuit [as shown].
Regarding claim 16, Neugebauer in view of Ko discloses further wherein the method comprises reducing, by the second MOS device [Ko, 510c], a resistance created by a transistor block [Ko, 510c increasing current through 110c] at a left branch of the voltage level shifter block.
Regarding claim 17, Neugebauer in view of Ko discloses further wherein the method comprises pulling up, by the p-type transistor block, an n-side of an N-side final output to a supply voltage [Neugebauer, transistors 42-44 activated thereby bringing node 64 up towards node 38].
Regarding claim 17, Neugebauer in view of Ko discloses further wherein the method comprises pulling up a final output block of the voltage level shifter block, by the n-type transistor block at a right branch by receiving an input from an N-side final output of the level shifter circuit [Ko, 410c causing Y output to be either high or low bases on an input signal].
Allowable Subject Matter
Claims 3, 9-10 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842