DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
As noted in the prosecution of the parent application, the claimed buffering module (and its buffer) is placed in parallel to the battery. Its “input” and “output” are the same node. The claim language giving the nodes different names, descriptions of what they are coupled to, and descriptions of what the energy they are “to receive” or “to provide”, does not overcome this interpretation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 10-11, 13-14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain (US 2011/0260676).
With respect to claim 1, Jain discloses a system (fig 2; par 3-4, 13, 21-32) comprising:
an intermittent power source (260) to output electrical energy at a first rate that exceeds a threshold charging rate of a battery storage system;
the battery storage system (270); and
a buffering module (205 as a whole, or just 252; par 13, 23, 25, 30) directly coupled to the intermittent power source, the buffering module comprising:
an input (positive terminal on the left side of 205; near where the label “panel output 262” is written) to receive the electrical energy from the intermittent power source,
a buffer (252) electrically coupled to the input, the buffer to temporarily store the electrical energy received from the intermittent power source, and
an output (positive terminal on the right side of 205) electrically coupled to the buffer, the output to provide electrical energy to the battery storage system at a second rate that is at or below the threshold charging rate of the battery storage system.
Jain discloses “control system 205 performs a ‘maximum current tracking’ for operating a solar panel system 200 [] to increase the current level of the panel output 262 until either the current level reaches a maximum charge current of the battery or the current level reaches a maximum of the power output…” (par 30, emphasis added). Jain uses a buffering module (205) with a buffer (252) to absorb the excess power that is denied to the battery (par 26). The maximum charge current is a “rate”, as Jain explains in paragraph 3.
With respect to claim 2, Jain discloses the threshold charging rate of the battery storage system is a maximum charging rate of the battery storage system (par 3-4). Claim 2 appears to simply change “threshold” to “maximum”. As a threshold is a critical value/limit – it would be understood to already indicate a maximum.
With respect to claim 3, Jain discloses the threshold charging rate of the battery storage system is an optimized charging rate of the battery storage system (par 4). Further, Jain’s system operates to its satisfaction. Thus, it is “optimized”.
With respect to claims 5 and 10-11, Jain discloses the system, as discussed above in the art rejection of claims 1-3, respectively, and further discloses a voltage limiting element (240) coupled to the intermittent power source, the voltage limiting element to output electrical energy at a second rate that is equal to or less than the first rate, the second rate exceeding the threshold charging rate of the battery storage system (par 12, 23-24).
With respect to claims 13 and 17-18, Jain discloses the system, as discussed above in the art rejections of claims 1-3, respectively, and further discloses a current limiting element (240) coupled to the intermittent power source, the current limiting element to output electrical energy at a second rate that is equal to or less than the first rate, the second rate exceeding the threshold charging rate of the battery storage system (par 13, 23, 30).
With respect to claims 14, Jain discloses the current limiting element is adjusted using a maximum power point tracking (MPPT) algorithm (par 13, 20, 31).
With respect to claim 16, Jain discloses the current limiting element is connected in parallel with the buffering module (see fig 2). The path from the buffering module input (at 262) through the buffer (252) in in parallel with the path from the buffering module input through the current limiting element (240) and storage devices (250 and/or 270).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Hopf (US 2018/0351015).
Jain discloses the buffer is a capacitor, but does not expressly disclose a supercapacitor. Hopf discloses a solar power system and the equivalence of using a capacitor or supercapacitor as an energy storage element (par 24).
Jain and Hopf are analogous to the claimed invention because they are from the same field of endeavor, namely solar power systems with energy storage. At the time of the earliest priority date of the application, it would have been obvious to one skilled in the art to replace the Jain capacitor with a supercapacitor, as taught by Hopf. The motivation for doing so would have been to realize the expected benefits of the supercapacitor. Hopf does not disclose any hardships in switching between the different energy storage options.
Claims 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Chang (US 2019/0058351).
As an alternative rejection for claim 5, Jain discloses the system (see art rejection of claim 1), but does not expressly disclose the voltage limiting element. Chang discloses a system (fig 1-2; par ) comprising:
an intermittent power source (22) to output electrical energy at a first rate;
a voltage limiting element (D3 and/or D1) coupled to the intermittent power source, the voltage limiting element to output electrical energy at a second rate that is equal to or less than the first rate (obvious function of the diodes as “voltage limiting” elements); and
a buffering module (C1-C3) coupled to the voltage limiting element, the buffering module comprising:
an input (positive node above Cn) to receive the electrical energy from the voltage limiting element,
a buffer (C1-C3) electrically coupled to the input, the buffer to temporarily store the electrical energy received from the intermittent power source, and
an output (positive node above Cn) electrically coupled to the buffer, the output to provide electrical energy.
Chang discloses combining a solar power generation system with voltage regulation elements (diodes). While Chang does not disclose providing the solar power to a battery, this feature (and the regulation of that power to below the battery’s maximum charging rate) is taught by Jain.
Jain and Chang are analogous to the claimed invention because they are from the same field of endeavor, namely solar power systems. At the time of the earliest priority date of the application, it would have been obvious to one skilled in the art to modify Jain to include a voltage limiting element, as taught by Chang. The motivation for doing so would have been to regulate power flow from the source. The skilled artisan would have understood the benefits of using diodes in a circuit and would have been motivated to add them to Jain, in the locations taught by Chang.
With respect to claim 6, Chang discloses the voltage limiting element is a Zener diode (D1).
With respect to claim 7, Chang discloses the voltage limiting element is a Schottky diode (D3).
With respect to claim 8, Chang discloses the voltage limiting element (D3) is connected in series between the intermittent power source and the buffering module.
With respect to claim 9, Chang discloses the voltage limiting element (D1) is connected in parallel with the buffering module.
With respect to claims 10-11, Jain discloses the recited limitations, as discussed above.
With respect to claim 12, Chang discloses the buffer is a supercapacitor (C1-C3).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Parameswaran (US 2012/0173031).
For the purpose of the art rejection of claim 15, the Jain current limiting element is interpreted as current sensor 220. Jain discloses the current limiting element is in series between the intermittent power source and the buffering module (see fig 2). Jain discloses a current sensor, but does not expressly disclose it includes a series-resistor. Parameswaran discloses that it is known to construct current sensors with an in-series resistor (fig 1, item 112; par 30). The Applicants’ specification discloses that the current limiting element is a resistor (par 70). Thus, the references’ teachings satisfies the limitation in claim 15.
Jain and Parameswaran are analogous to the claimed invention because they are from the same field of endeavor, namely solar power systems with current limiters. At the time of the earliest priority date of the application, it would have been obvious to one skilled in the art to modify the sensor taught by Jain to include a resistor, as taught by Parameswaran. The motivation for doing so would have been to build a sensor with a known and proven design.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADI AMRANY whose telephone number is (571)272-0415. The examiner can normally be reached Monday - Friday, 8am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rex Barnie can be reached at 5712722800 x36. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADI AMRANY/ Primary Examiner, Art Unit 2836