Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20200244252 A1 and Kim hereinafter.).
Regarding claim 1, Kim discloses [fig. 3] a level shifter [10] comprising: a Wilson current mirror circuit [200] configured to output an output voltage of an output node [VSK] based on a first input voltage [VINB] inverting a phase of an input voltage [VIN] and a second input voltage [VIND] inverting the phase of the first input voltage; a leakage current control circuit [MP3] configured to receive the output voltage and control a leakage current generated in the Wilson current mirror circuit using the output voltage [para. 49 regarding floating terminals on MP1 and MP2]; and a latch circuit [310] configured to provide a voltage of a logic high level to the output node when the output voltage is a logic high level [para. 36].
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagarajan et al. (US 11050424 B1 and Nagarajan hereinafter.).
Regarding claim 20, Nagarajan discloses a semiconductor device [fig. 3a] comprising: a receiver that receives an input signal from an outside [col 5 lines 48-57]; and a level shifter [300] configured to receive the input signal, output an output signal at an output node by level-shifting the input signal [shown], and control a leakage current flowing to the output node and a voltage of the output node using the output signal [col 6 lines 52-64].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of De Sandre et al. (US 20060226873 A1 and De Sandre hereinafter.).
Regarding claim 2, Kim discloses all the features regarding claim 1 as indicated above. Kim discloses further comprising: an output inverter circuit [320] configured to receive the output voltage and output a first output voltage [VOUTB] inverting the phase of the output voltage and a second output voltage [VOUT] inverting the phase of the first output voltage, wherein the Wilson current mirror circuit comprises: a first mirror transistor [MN3] electrically connected to a ground voltage and including a gate to which the second input voltage is applied; a second mirror transistor [MN1] electrically connected to the ground voltage and including a gate to which the first input voltage is applied. Kim discloses further a fifth mirror transistor (MP5)[MP2] electrically connected between the output node and the driving voltage source and including a gate connected to the mirror node. Kim does not explicitly disclose a third mirror transistor electrically connected to the first mirror transistor and including a gate to which the output voltage is applied; a fourth mirror transistor electrically connected between the third mirror transistor and a driving voltage source and including a gate connected to the mirror node.
However, De Sandre discloses a third mirror transistor (MP3)[M3] electrically connected to the first mirror transistor [M2] and including a gate to which the output voltage [VOUT] is applied; a fourth mirror transistor (MP4)[M5] electrically connected between the third mirror transistor and a driving voltage source [VDD] and including a gate connected to the mirror node [G5]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kim to include a third mirror transistor electrically connected to the first mirror transistor and including a gate to which the output voltage is applied; a fourth mirror transistor electrically connected between the third mirror transistor and a driving voltage source and including a gate connected to the mirror node as taught by De Sandre to improve a level shifting circuit by allowing a translation with a current conductive path without starting a positive feedback, thus providing the speed up in the transition from one logic level to another, and hence improving the operating efficiency.
Regarding claim 14, Kim discloses [fig. 3] a level shifter [10] comprising: a first transistor [MN1] electrically connected to a ground voltage and including a gate to which a first input voltage [VINB] is applied, wherein the first input voltage is an inverted copy of an input voltage [VIN]; a second transistor [MN3] electrically connected to the ground voltage and including a gate to which a second input voltage [VIND] is applied, wherein the second input voltage is an inverted copy of the first input voltage; a third transistor [MN2] electrically connected to the first transistor and including a gate to which an output voltage [VOUT] is applied; a fifth transistor [MP2] electrically connected between an output node to which the output voltage is applied [through 310 and 320] and the driving voltage source [VDDH] and including a gate connected to a mirror node [DR]. Kim does not explicitly disclose a fourth transistor electrically connected between the third transistor and a driving voltage source and including a gate connected to the mirror node; at least one control transistor disposed between the mirror node and the driving voltage source and including a gate configured to receive the output voltage as a feedback.
However, De Sandre discloses [fig. 5] a fourth transistor [M5] electrically connected between the third transistor [M3] and a driving voltage source [VDD] and including a gate connected to the mirror node [G5]; at least one control transistor [M8] disposed between the mirror node and the driving voltage source and including a gate configured to receive the output voltage as a feedback [Vout through buffer Buf1]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kim to include a fourth transistor electrically connected between the third transistor and a driving voltage source and including a gate connected to the mirror node; at least one control transistor disposed between the mirror node and the driving voltage source and including a gate configured to receive the output voltage as a feedback as taught by De Sandre to improve a level shifting circuit by allowing a translation with a current conductive path without starting a positive feedback, thus providing the speed up in the transition from one logic level to another, and hence improving the operating efficiency.
Allowable Subject Matter
Claims 3, 7, 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2842 /LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842