Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the fourth mirror transistor" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the fifth mirror transistor" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the fourth mirror transistor " in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the fifth mirror transistor " in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200244252 A1 and Kim hereinafter.).
Regarding claim 1, Kim discloses [fig. 3] a level shifter [10] comprising: a current mirror circuit [200] configured to output an output voltage of an output node [VSK] based on a first input voltage [VINB] inverting a phase of an input voltage [VIN] and a second input voltage [VIND] inverting the phase of the first input voltage; a leakage current control circuit [MP3] configured to receive the output voltage and control a leakage current generated in the Wilson current mirror circuit using the output voltage [para. 49 regarding floating terminals on MP1 and MP2]; and a latch circuit [310] configured to provide a voltage of a logic high level to the output node when the output voltage is a logic high level [para. 36], wherein the leakage current control circuit comprises a control transistor [MP3] including a gate configured to receive the output voltage [VSK], the control transistor is electrically connected between a driving voltage source that provides a driving voltage [MP3 driven by VSK] and a mirror node of the Wilson current mirror circuit [DR], and the leakage current control circuit is configured to provide the driving voltage [VDDH] to the mirror node so that a fourth mirror [MP1] transistor and a fifth mirror transistor [MP2] of the Wilson current mirror circuit are turned off when the output voltage is a logic low level [fig. 6 showing MP1 and MP2 off due to MP3 being turned on coupling DR to VDDH].
Kim does not explicitly disclose the current mirror as a Wilson current mirror. However, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the current mirror 210 of Kim by placing a third mirroring transistor between MP1 and MN1 with a gate coupled to VSK, thereby having a Wilson current mirror thereby improving input and output impedance as well as frequency response of the current mirror. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 2, Kim discloses further comprising: an output inverter circuit [fig. 3, inverter 320] configured to receive the output voltage [VOUTB] and output a first output voltage inverting the phase of the output voltage and a second output voltage [VOUT] inverting the phase of the first output voltage, wherein the Wilson current mirror circuit comprises: a first mirror transistor [MN3] electrically connected to a ground voltage and including a gate to which the second input voltage is applied [VIND]; a second mirror transistor [MN1] electrically connected to the ground voltage and including a gate to which the first input voltage is applied [VINB]; a third mirror transistor electrically connected to the first mirror transistor and including a gate to which the output voltage is applied [the third mirroring transistor of the Wilson current mirror between MP1 and MN1 with a gate coupled to VSK]; a fourth mirror transistor [MP3] electrically connected between the third mirror transistor and a driving voltage source [VDDH] and including a gate connected to a mirror node [DR]; and the fifth mirror transistor [MP2] electrically connected between the output node and the driving voltage source and including a gate connected to the mirror node [DR].
Regarding claim 8, Kim discloses all the features of claim 1 as indicated above. Kim discloses further wherein the leakage current control circuit further comprises a control transistor [MP3] including a gate configured to receive the output voltage [gate of MP3 receiving VSK as shown in fig. 3], and the control transistors are coupled in series between the driving voltage source and the mirror node [MP3 coupled in series between VDDH and DR as shown in fig. 3].
Kim does not explicitly disclose the leakage current control circuit further comprises a plurality of control transistors including a gate configured to receive the output voltage, coupled in series between the driving voltage source and the mirror node.
However, it would be obvious to one of ordinary skill in the art before the effective filing date to replace the leakage control transistor MP3 with a plurality of series connected leakage control transistors to prevent damage due to a drain-source voltage exceeding a maximum breakdown voltage, thereby improving power performance in the leakage detection circuit.
Regarding claim 9, Kim discloses further wherein the leakage current control circuit is configured to transmit the driving voltage to the mirror node when the output voltage is at a logic low level [fig. 6 showing MP3 on with solid lines, coupling DR to VDDH thereby turning MP1 and MP2 off, shown with dashed lines, due to VSK being low], causing the fourth mirror transistor and the fifth mirror transistor to be turned off [MP1 and MP2 off], and does not transmit the driving voltage to the mirror node when the output voltage is at a logic high level [fig. 7 showing MP1 and MP2 to be turned on due to MP3 turning off due to VSK transitioning from low to high], causing the fourth mirror transistor and the fifth mirror transistor to be temporarily turned on [MP1 and MP2 to be turned on].
Regarding claim 10, Kim discloses further wherein when a voltage level of the input voltage transitions from a logic high level to a logic low level [fig. 3, VIND is still high due to inverters 101 and 102], the leakage current control circuit is further configured to transmit the driving voltage to the mirror node [fig. 6, MP3 on shown with solid lines, coupling DR to VDDH], and the Wilson current mirror circuit is configured to lower a voltage of the mirror node [fig. 8, after VIND transitions from high to low, MP3 is turned off shown with dashed lines, causing DR to now be low].
Regarding claim 11, Kim discloses further wherein when the voltage of the mirror node is lowered by the Wilson current mirror circuit [fig. 7, MP3 turned off], the fourth mirror transistor and the fifth mirror transistor are further configured to be turned on [fig. 7, MP1 and MP2 turned on], and the output voltage is further configured to transit from a logic low level to a logic high level [fig. 7, VSK transitioning from low to high].
Regarding claim 12, Kim discloses further wherein when a voltage level of the input voltage transitions from a logic low level to a logic high level [fig. 3 and 5, VIN transitioning from low to high means VINB is also transitioning from high to low due to inverter 101], the leakage current control circuit is further configured to increase a voltage of the mirror node [fig. 5 showing MP3 turned on with solid lines, coupling DR to VDDH], and the Wilson current mirror circuit is further configured to lower the output voltage to the logic low level [VSK transitioning from high to low].
Regarding claim 13, Kim discloses further wherein the control transistor receiving the output voltage is further configured to be turned on [fig. 6, MP3 turned on shown with solid lines], and the voltage applied to the mirror node increases [DR coupled to VDDH], causing the fourth mirror transistor and the fifth mirror transistor to be turned off [MP1 and MP2 turned off shown with dashed lines].
Regarding claim 14, Kim discloses [fig. 3] a level shifter [10] comprising: a first transistor [MN1] electrically connected to a ground voltage and including a gate to which a first input voltage [VINB] is applied, wherein the first input voltage is an inverted copy of an input voltage [VIN]; a second transistor [MN3] electrically connected to the ground voltage and including a gate to which a second input voltage [VIND] is applied, wherein the second input voltage is an inverted copy of the first input voltage; a third transistor [MN2] electrically connected to the first transistor and including a gate to which an output voltage [VOUT] is applied; a fourth transistor [MP1] electrically connected between the third transistor and a driving voltage source [VDHH] and including a gate connected to a mirror node [DR];[VSK] and the driving voltage source [as shown in fig. 3] and including a gate connected to a mirror node [DR]; and at least one control transistor [MP3] disposed between the mirror node and the driving voltage source [as shown in fig. 3] and including a gate configured to receive the output voltage as a feedback [as shown in fig. 3], wherein a leakage current control circuit comprises a control transistors [MP3], including the at least one control transistor [MP3], wherein the control transistor is provided for configuring the leakage current control circuit [para. 78 and fig. 4], wherein, when the output voltage is at a logic low level, a voltage applied to the mirror node is raised to a logic high level causing the fourth transistor and the fifth transistor to be turned off [fig. 6 showing MP3 on, coupling DR to VDDH thereby turning MP1 and MP2 off due to VSK being low], and wherein, when the output voltage transitions from the logic low level to a logic high level, the first transistor lowers the voltage applied to the mirror node to a logic low level causing the fourth transistor and the fifth transistor to be temporarily turned on [fig. 7 showing MP1 and MP2 to be turned on due to MP3 turning off due to VSK transitioning from low to high].
Kim does not explicitly disclose the leakage current control circuit comprises a plurality of control transistors, coupled in series, wherein a number of the plurality of control transistors is provided for configuring the leakage current control circuit.
However, it would be obvious to one of ordinary skill in the art before the effective filing date to replace the leakage control transistor MP3 with a plurality of series connected leakage control transistors to prevent damage due to a drain-source voltage exceeding a maximum breakdown voltage, thereby improving power performance in the leakage detection circuit.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nagarajan et al. (US 11050424 B1 and Nagarajan hereinafter.) in view of Kim.
Regarding claim 20, Nagarajan discloses a semiconductor device [fig. 3a] comprising: a receiver that receives an input signal from an outside [col 5 lines 48-57]; and a level shifter [300] configured to receive the input signal, output an output signal at an output node by level-shifting the input signal [shown], and control a leakage current flowing to the output node and a voltage of the output node using the output signal [col 6 lines 52-64] Nagarajan does not explicitly disclose wherein the level shifter includes a Wilson current mirror circuit including a mirror node, and a leakage current control circuit comprising a control transistor including a gate configured to receive the output signal, wherein the control transistor is electrically connected between a driving voltage source that provides a driving voltage and the mirror node, and wherein the leakage current control circuit is configured to provide the driving voltage to the mirror node so that a fourth mirror transistor and a fifth mirror transistor of the Wilson current mirror circuit are turned off when the output signal is a logic low level.
However, Kim discloses [fig. 3] wherein the level shifter [10] includes a current mirror circuit [210] including a mirror node [DR], and a leakage current control circuit [MP3, para. 86] comprising a control transistor [MP3] including a gate configured to receive the output signal [VSK], wherein the control transistor is electrically connected between a driving voltage source that provides a driving voltage [unlabeled high rail providing power] and the mirror node [MP3 coupled between DR and unlabeled high rail providing power], and wherein the leakage current control circuit is configured to provide the driving voltage to the mirror node [MP3 turned ON shorts DR to high rail providing power to current mirror] so that a fourth mirror transistor and a fifth mirror transistor of the Wilson current mirror circuit are turned off when the output signal is a logic low level [para. 68, fig. 5 showing VSK transitioning from high to low causes MP1 and MP2 to be off].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the semiconductor device as described by Nagarajan to include the leakage current control circuit of Kim between the mirror node and VDD0 to improve current leakage in a semiconductor device.
Nagarajan in view of Kim does not explicitly disclose the current mirror as a Wilson current mirror. However, it would be obvious to one of ordinary skill in the art before the effective filing date to modify the current mirror 210 of Kim by placing a third mirroring transistor between MP1, MP2 and MN1 and MN3 thereby having a Wilson current mirror thereby improving input and output impedance as well as frequency response of the current mirror. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Allowable Subject Matter
Claims 3 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot. Regarding claims 1 and 14, a new grounds of rejection is made with respect to Kim as outlined above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Mathur (US 9240787 B2) is cited to teach a level shifting circuit featuring current mirrors and latches.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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