DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Marathe et al (U.S. 2018/0046556), and in view of Gadangi et al (U.S. 6,219,772).
Regarding claim 1:
A storage device comprising:
a memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of sub-blocks, wherein at least two sub-blocks of the plurality of sub-blocks have different sizes; Marathe teaches in Figs. 1-2, a memory device comprises a memory controller 110, memory 134 includes a plurality of superblock (Fig. 2), each of the plurality of superblock hosts memory blocks of a specific size (¶0065), which may vary (¶0069). Marathe also teaches a collection of superblock lists, where each list may include superblocks used to allocate/deallocate blocks of a specific size (¶0073). Thus Marathe teaches the idea of a memory block/superblock comprises one or more smaller units such as pages/sub-blocks having different size according to their respective block/superblock.
However, Marathe does not teach but Gadangi teaches a memory controller configured to manage the plurality of memory blocks and the plurality of sub-blocks, wherein the memory controller is further configured to: based on a predetermined sub-block attribute criteria, select at least one sub-block from the plurality of sub-blocks, add the selected at least one sub-block to at least one sub-block pool, Gadangi teaches in Fig. 2, a plurality of same size pools 230, each of the same size pools comprises a plurality of blocks having a particular size (Fig. 2, same size pool 230 comprises block with size 4kB, 64Kb, 128Kb (3:35-45).
and based on the predetermined sub-block attribute criteria, allocate the selected at least one sub-block in the at least one sub-block pool to a virtual memory block. Gadangi further teaches in Fig. 3A, and corresponding text, an allocation request for a block having a size is received (3:30-45), a same size pool 230 is created (as needed) for each of the possible block size, a free block from the same size pool is committed to satisfy the request (3:46 – 4:15, 4:55- 5:55). It has been interpreted that satisfying a memory block allocation request, is allocate a block/sub-block with a size (attribute criteria) to a virtual memory block.
Marathe teaches the a memory structure with superblock at first level, and a plurality of block with different sizes at second level, as show above. Gadangi teaches the idea of a plurality of blocks with different sizes are organized in block pools with respective size, and allocate the block in response to a request. Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Gadangi into the teaching of Marathe to obtain the claimed limitations above. The motivation for doing so is to utilize known technique to a known device, ready for improvement, to yield predictable results.
Regarding claim 2:
The storage device of claim 1, wherein the plurality of sub-blocks comprise: a first sub-block with a first capacity being the smallest capacity; a second sub-block with a second capacity that is larger than the first capacity of the first sub-block; and a third sub-block with a third capacity that is larger than the second capacity of the second sub-block, Gadangi teaches in Fig. 2, a plurality of same size pools 230, each of the same size pools comprises a plurality of blocks having a particular size (Fig. 2, same size pool 230 comprises block with size 4kB, 64Kb, 128Kb (3:35-45).
wherein the memory controller is further configured to: based on the first capacity, the second capacity, and the third capacity, select one of the first sub-block, the second sub-block and the third sub-block, add the first sub-block to a first sub-block pool, add the second sub-block to a second sub-block pool, and add the third sub-block to a third sub-block pool. Gadangi teaches same size pool is created to each block size (Fig. 2, 3:45-60)
Regarding claim 11:
A method performed by a storage device comprising a plurality of memory blocks, the method comprising: wherein at least two sub-blocks of the plurality of sub-blocks have different sizes. Marathe teaches in Figs. 1-2, a memory device comprises a memory controller 110, memory 134 includes a plurality of superblock (Fig. 2), each of the plurality of superblock hosts memory blocks of a specific size (¶0065), which may vary (¶0069). Marathe also teaches a collection of superblock lists, where each list may include superblocks used to allocate/deallocate blocks of a specific size (¶0073). Thus Marathe teaches the idea of a memory block/superblock comprises one or more smaller units such as pages/sub-blocks having different size according to their respective block/superblock.
However, Marathe does not teach but Gadangi teaches based on a predetermined sub-block attribute criteria, selecting at least one sub-block from a plurality of sub-blocks in the plurality of memory blocks; adding the selected at least one sub-block to a sub-block pool; and based on the predetermined sub-block attribute criteria, allocating the selected at least one sub-block in the sub-block pool to a virtual memory block, wherein at least two sub-blocks of the plurality of sub-blocks have different sizes. Gadangi teaches in Fig. 2, a plurality of same size pools 230, each of the same size pools comprises a plurality of blocks having a particular size (Fig. 2, same size pool 230 comprises block with size 4kB, 64Kb, 128Kb (3:35-45). Gadangi further teaches in Fig. 3A, and corresponding text, an allocation request for a block having a size is received (3:30-45), a same size pool 230 is created (as needed) for each of the possible block size, a free block from the same size pool is committed to satisfy the request (3:46 – 4:15, 4:55- 5:55). It has been interpreted that satisfying a memory block allocation request, is allocate a block/sub-block with a size (attribute criteria) to a virtual memory block.
Marathe teaches the a memory structure with superblock at first level, and a plurality of block with different sizes at second level, as show above. Gadangi teaches the idea of a plurality of blocks with different sizes are organized in block pools with respective size, and allocate the block in response to a request. Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Gadangi into the teaching of Marathe to obtain the claimed limitations above. The motivation for doing so is to utilize known technique to a known device, ready for improvement, to yield predictable results.
Allowable Subject Matter
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of record teaches a storage device comprises a plurality of superblocks, each of the plurality of superblocks comprises one or more sub-block with different size, and allocate one or more sub-block in response to receiving an allocation request from external requester. However, the prior art of record does not teach combining a virtual memory block using at least one sub-block based on the virtual memory block allocation requirement.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 3-10, 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior of record, is not reasonable combinable to teach adding multiple sub-blocks from multiple block pools to a virtual memory block, where the sub-blocks either having same capacities or different capacities, or different erase counts.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Narayanasamy et al (U.S. 20110107052) teaches data blocks can be grouped into a subpage, and subpages, in turn, can be grouped into a page. The subpage and page sizes can be different, and may be varied to optimize the performance of the system.
Chang et al (U.S. 2004/0080985) teaches sorting memory blocks to groups according to their respective erase counts.
S. Teshome and T. -S. Chung teaches a tri-pool dynamic wear leveling technique, where flash memory array is partitioned into three groups, hot pool, cold pool, and neutral pool.
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/KHOA D DOAN/ Primary Examiner, Art Unit 2133