DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation "the CTE of the flip-chip" and “the CTE of the base layer”. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitations "the CTE of the flip-chip" and “the CTE of the base layer” of claim 1 will be interpreted and examined as "a CTE of the flip-chip" and “a CTE of the base layer”.
Regarding claim 11, claim 11 recites the limitation "the CTE of the flip-chip" and “the CTE of the second layer”. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitations "the CTE of the flip-chip" and “the CTE of the second layer” of claim 1 will be interpreted and examined as "a CTE of the flip-chip" and “a CTE of the second layer”.
Regarding claim 16, claim 16 recites the limitation "the CTE of the flip-chip" and “the CTE of the second laminate layer”. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitations "the CTE of the flip-chip" and “the CTE of the second laminate layer” of claim 16 will be interpreted and examined as "a CTE of the flip-chip" and “a CTE of the second laminate layer”.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280)
Regarding claim 1, Kimura discloses in Fig. 4, Fig. 8, paragraph [0033] and [0043] an integrated circuit package comprising:
a plurality of devices [6 and 7] comprising a flip-chip [6] having an active side;
a base layer [1] configured to electrically interconnect the plurality of devices [6 and 7], wherein the active side of the flip-chip [6] is positioned opposite the base layer [1] and is electrically connected to the base layer [1]; and
a thermally conductive layer [13] positioned so that the plurality of devices [6 and 7] are located between the base layer [1] and the thermally conductive layer [13], wherein the flip-chip [6] is thermally connected to the thermally conductive layer [13].
Kimura fails to disclose
wherein a coefficient of thermal expansion (CTE) of the thermally conductive layer is approximately the same as the base layer, and wherein a CTE of the flip-chip is not approximately the same as the CTE of the thermally conductive layer or a CTE of the base layer.
Doany et al. discloses in Fig. 3, paragraph [0024], [0026]-[0028], [0036]-[0037]
wherein a coefficient of thermal expansion (CTE) of the thermally conductive layer is approximately the same as the base layer, and wherein a CTE of the flip-chip is not approximately the same as the CTE of the thermally conductive layer or a CTE of the base layer [“the CTE of the spreader can be matched to the silicon photonics die instead of the CTE of the laser die”; “the laser die 106 can be disposed on the carrier die 108…To mitigate the effects of thermal expansion, the CTE of the spreader 102 and the CTE of the carrier die 108 can be matched.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Doany et al. into the method of Kimura to include wherein a coefficient of thermal expansion (CTE) of the thermally conductive layer is approximately the same as the base layer, and wherein a CTE of the flip-chip is not approximately the same as the CTE of the thermally conductive layer or a CTE of the base layer. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of maintaining device alignment to improve the heat sink assembly performance [Abstract, paragraph [0036] of Doany et al.].
Regarding claim 5, Kimura discloses in Fig. 4, Fig. 8
a plurality of solder balls [9] arranged as a ball grid array, wherein the ball grid array electrically connects the active side of the flip-chip [6] to the base layer [1].
Regarding claim 8, Kimura discloses in Fig. 4, Fig. 8, paragraph [0033]
molding compound [14] surrounding the flip-chip [6].
Claims 2-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280) as applied to claim 1 above and further in view of Desai et al. (US Pub. 20050224955).
Regarding claims 2-3 and 6, Kimura discloses in Fig. 8
wherein the flip-chip [6] is thermally connected to the thermally conductive layer [13];
wherein the thermally conductive layer [13] comprises a heat spreading region;
a second flip-chip [7] having a second active side;
wherein the second active side is positioned opposite the base layer [1] and is electrically connected to the base layer [1], and
wherein the second flip-chip [7] is thermally connected to the thermally conductive layer [13];
wherein: the thermally conductive layer [13] comprises a first heat spreading region and a second heat spreading region.
Kimura fails to disclose
a spacer, wherein the flip-chip is thermally connected to the thermally conductive layer via the spacer, and wherein the spacer is connected to the heat spreading region via a connection layer;
a second spacer, and wherein the second flip-chip is thermally connected to the thermally conductive layer via the second spacer;
a second spacer, the first heat spreading region is attached to the spacer via a first connection layer; and the second heat spreading region is attached to the second spacer via a second connection layer.
Desai et al. discloses in Fig. 2a, Fig. 2b, paragraphs [0001], [0005], [0007]-[0008]
a spacer [203], wherein a flip-chip [102] is thermally connected to the thermally conductive layer [110] via a spacer [203], and wherein a spacer [203] is connected to a heat spreading region via a connection layer [202].
Replacing incorporating thermal conductivity adhesive 18 on the flip-chip 6 and the second flip-chip 7 disclosed in Fig. 8 of Kimura with the multi-layer heat transfer element disclosed by Desai et al. would result to “a spacer, wherein the flip-chip is thermally connected to the thermally conductive layer via the spacer, and wherein the spacer is connected to the heat spreading region via a connection layer; a second spacer, and wherein the second flip-chip is thermally connected to the thermally conductive layer via the second spacer; a second spacer, the first heat spreading region is attached to the spacer via a first connection layer; and the second heat spreading region is attached to the second spacer via a second connection layer.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Desai et al. into the method of Kimura to include a spacer, wherein the flip-chip is thermally connected to the thermally conductive layer via the spacer, and wherein the spacer is connected to the heat spreading region via a connection layer; a second spacer, and wherein the second flip-chip is thermally connected to the thermally conductive layer via the second spacer; a second spacer, the first heat spreading region is attached to the spacer via a first connection layer; and the second heat spreading region is attached to the second spacer via a second connection layer. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of providing improved thermal communication between a die and a heat spreader in a semiconductor integrated circuit package [paragraphs [0001], [0005], [0007]-[0008] of Desai et al.]
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280) as applied to claim 1 above and further in view of Leal et al. (US Pub. 20070284704)
Regarding claim 4, Kimura fails to disclose
wherein the flip-chip is a radio frequency power amplifier.
Leal et al. discloses in Fig. 2, paragraph [0024], [0061]
wherein the flip-chip [208] is a radio frequency power amplifier.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Leal et al. into the method of Kimura to include wherein the flip-chip is a radio frequency power amplifier. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of providing suitable semiconductor die [Abstract, paragraph [0002]-[0003], [0021] of Leal et al.].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280) and Desai et al. (US Pub. 20050224955) as applied to claim 6 above and further in view of Chen et al. (US Pub. 20230260866).
Regarding claim 7, Kimura discloses in Fig. 4, Fig. 8, paragraph [0033]
wherein the thermally conductive layer [13] comprises a metal, and where the first heat spreading region and the second heat spreading region are made of the metal.
Kimura fails to disclose
wherein the thermally conductive layer comprises a dielectric material.
Chen et al. discloses in Fig. 1B, Fig. 4, Fig. 6, paragraph [0028], [0031]-[0032]
wherein the thermally conductive layer [118] comprises a dielectric material [passivation layers].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen et al. into the method of Kimura to include wherein the thermally conductive layer comprises a dielectric material. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of providing suitable alternative configuration of the thermally conductive layer [paragraph [0028], [0031]-[0032] of Chen et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280) and Desai et al. (US Pub. 20050224955) as applied to claim 3 above and further in view of Dou et al. (US Pub. 20230178442) and Yoshimi et al. (US Pub. 20220199557).
Regarding claim 9, Kimura fails to disclose
a top-side active device having a first side and a second side, wherein the base layer further comprises a heat spreading region, wherein the first side is electrically connected to the base layer, and wherein the second side is thermally connected to the heat spreading region.
Dou et al. discloses in Fig. 16, Fig. 17, paragraphs [0015], [0067], [0101]-[0102], [0108], [0114]
a top-side active device [222 left] having a first side [top side] and a second side [bottom side], wherein the base layer [21] further comprises a heat spreading region, wherein the first side [top side] is electrically connected to the base layer [21], and wherein the second side [bottom side] is thermally connected to the heat spreading region.
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For further providing support for a base layer comprises a heat spreading region, Yoshimi et al. is cited.
Yoshimi et al. discloses in Fig. 3, paragraph [0049]
a top-side active device [32] having a first side [top side] and a second side [bottom side], wherein the base layer [312] further comprises a heat spreading region, wherein the first side [top side] is electrically connected to the base layer [312], and wherein the second side [bottom side] is thermally connected to the heat spreading region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Dou et al. and Yoshimi et al. into the method of Kimura to include a top-side active device having a first side and a second side, wherein the base layer further comprises a heat spreading region, wherein the first side is electrically connected to the base layer, and wherein the second side is thermally connected to the heat spreading region. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of providing a package including multiple components to facilitate miniaturization and improvement of function diversity of an electronic apparatus; providing a base layer that functions as heat transfer path to improve heat dissipation efficiency of the top-side active device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US Pub. 20040099944) in view of Doany et al. (US Pub. 20190214280) as applied to claim 1 above and further in view of Lin et al. (US Pub. 20230335507)
Regarding claim 10, Kimura fails to disclose
wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the thermally conductive layer is in a range of about 9 to 16 parts per million per °C.
Lin et al. discloses in claim 2
wherein the CTE value of the flip-chip [is in a range of about 2 to 5 parts per million per °C [2.6-2.8 ppm/°C], and the CTE value of the base layer is in a range of about 9 to 16 parts per million per °C [16ppm/° C].
Doany et al. suggests the CTE value of the base layer is matched with the CTE value of the thermally conductive layer. Thus, the combination of Doany et al. and Lin et al. suggests the CTE value of the thermally conductive layer is 16ppm/°C.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Doany et al. and Lin et al. into the method of Kimura to include wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the thermally conductive layer is in a range of about 9 to 16 parts per million per °C. The ordinary artisan would have been motivated to modify Kimura in the above manner for the purpose of provide suitable CTE values of the flip chip and of the thermally conductive layer.
In addition, Applicant has not provided criticality of the claimed ranges. It would have been obvious to modify Kimura et al. to provide wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the thermally conductive layer is in a range of about 9 to 16 parts per million per °C. The ordinary artisan would have been motivated to modify Kimura et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide suitable CTE values of the flip chip and of the thermally conductive layer to provide a package having desired performance. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 11, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis et al. (US Pub. 20170084554) in view of Doany et al. (US Pub. 20190214280) and Lin et al. (US Pub. 20230335507) and Leal et al. (US Pub. 20070284704)
Regarding claims 11, 14 and 15, Dogiamis et al. discloses in Fig. 3A, 3B, 5B, paragraph [0039] a heterogeneous integrated circuit package for wireless communications, comprising:
a plurality of devices comprising a flip-chip [330/530] having an active side;
a first layer [310/510] configured to electrically interconnect the plurality of devices, wherein the active side of the flip-chip [6] is positioned opposite the first layer [310/510] and is electrically connected to the first layer [310/510][paragraph [0040]-[0041]]; and
a second layer [horizontal portions of 528 and 585 on the flip-chip] positioned so that the plurality of devices are located between the first layer [310/510] and the second layer [horizontal portions of 528 and 585 on the flip-chip], wherein the flip-chip [530] is thermally connected to the second layer [horizontal portions of 528 and 585 on the flip-chip].
Dogiamis et al. discloses the flip-chip [330/530] is a radio frequency integrated circuit (RFIC).
Dogiamis et al. fails to disclose
wherein the flip-chip is a radio frequency power amplifier.
Leal et al. discloses in Fig. 2, paragraph [0024], [0061]
wherein the flip-chip [208] is a radio frequency power amplifier.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Leal et al. into the method of Dogiamis et al. to include wherein the flip-chip is a radio frequency power amplifier. The ordinary artisan would have been motivated to modify Dogiamis et al. in the above manner for the purpose of providing suitable radio frequency die [Abstract, paragraph [0002]-[0003], [0021] of Leal et al.].
Dogiamis et al. fails to disclose
wherein a coefficient of thermal expansion (CTE) of the first layer is a first value that results in a substantially planar thermally conducive layer in all operating conditions, and wherein a CTE of the flip-chip is not approximately the same as either the CTE of the first layer or a CTE of the second layer;
wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the first layer is in a range of about 9 to 16 parts per million per °C;
wherein the first value is approximately the same as the CTE of the second layer.
Lin et al. discloses in paragraph [0003], [0049] and claim 2
wherein a coefficient of thermal expansion (CTE) of the first layer is a first value [16ppm/°C] that results in a substantially planar thermally conducive layer in all operating conditions, wherein a CTE of the flip-chip [2.6-2.8 ppm/° C] is not approximately the same as either the CTE of the first layer or a CTE of the second layer;
wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C [2.6-2.8 ppm/° C], and the CTE value of the first layer is in a range of about 9 to 16 parts per million per °C [16ppm/°C].
Doany et al. discloses in Fig. 3, paragraph [0024], [0026]-[0028], [0036]-[0037]
wherein a coefficient of thermal expansion (CTE) of the first layer is approximately the same as the CTE of the second layer, and wherein a CTE of the flip-chip is not approximately the same as the CTE of the thermally conductive layer or a CTE of the base layer [“the CTE of the spreader can be matched to the silicon photonics die instead of the CTE of the laser die”; “the laser die 106 can be disposed on the carrier die 108…To mitigate the effects of thermal expansion, the CTE of the spreader 102 and the CTE of the carrier die 108 can be matched.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin et al. and Doany et al. into the method of Dogiamis et al. to include wherein a coefficient of thermal expansion (CTE) of the first layer is a first value that results in a substantially planar thermally conducive layer in all operating conditions, and wherein a CTE of the flip-chip is not approximately the same as either the CTE of the first layer or a CTE of the second layer; wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the first layer is in a range of about 9 to 16 parts per million per °C; wherein the first value is approximately the same as the CTE of the second layer. The ordinary artisan would have been motivated to modify Dogiamis et al. in the above manner for the purpose of providing suitable CTE values of the first/second layer and the flip chip and maintaining device alignment to improve the heat sink assembly performance [Abstract, paragraph [0036] of Doany et al., claim 2 of Lin et al.].
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis et al. (US Pub. 20170084554) in view of Doany et al. (US Pub. 20190214280) and Lin et al. (US Pub. 20230335507) and Leal et al. (US Pub. 20070284704) as applied to claim 11 above and further in view of Mori et al. (US Pub. 20060186755)
Regarding claim 12, Dogiamis et al. fails to disclose
wherein the plurality of devices further comprises a filter, and wherein the heterogeneous integrated circuit package is configured to connect to an antenna array.
Mori et al. discloses in Fig. 5, Fig. 6, paragraph [0089]-[0090]
wherein the plurality of devices further comprises a filter [39, 40], and wherein the heterogeneous integrated circuit package is configured to connect to an antenna array [31].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Mori et al. into the method of Dogiamis et al. to include wherein the plurality of devices further comprises a filter, and wherein the heterogeneous integrated circuit package is configured to connect to an antenna array. The ordinary artisan would have been motivated to modify Dogiamis et al. in the above manner for the purpose of providing a high-frequency module of a CDMA dual band system for use in mobile communication apparatuses [paragraph [0087]-[0090] of Mori et al.].
Regarding claim 13, Dogiamis et al. discloses in Fig. 5B
a thermal shunt [vertical portions of 585 and 528] sandwiched between the first layer [510] and the second layer [horizontal portion of 585 and 528], wherein the thermal shunt [vertical portions of 585 and 528] is configured to direct heat from the first layer [510] to the second layer [horizontal portion of 585 and 528].
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dogiamis et al. (US Pub. 20170084554) in view of Doany et al. (US Pub. 20190214280) and Lin et al. (US Pub. 20230335507)
Regarding claims 16 and 18, Dogiamis et al. discloses in Fig. 3A, 3B, 5B, paragraph [0039] a system for wireless communications, comprising:
a plurality of devices comprising a flip-chip [330/530] having a first side [active side] and a second side, the first side [active side] is configured to receive an input signal and transmit an output signal;
a first laminate layer [310/510] configured to electrically interconnect the plurality of devices and transmit the input signal and receive the output signal, wherein the first side is positioned opposite the first laminate layer [310/510][paragraph [0040]-[0041]]; and
a second laminate layer [horizontal portions of 528 and 585 on the flip-chip] positioned so that the plurality of devices are located between the first laminate layer [310/510] and the second laminate layer [horizontal portions of 528 and 585 on the flip-chip], wherein the flip-chip [530] is thermally connected to the second laminate layer [horizontal portions of 528 and 585 on the flip-chip] via the second side.
Dogiamis et al. fails to disclose
wherein a coefficient of thermal expansion (CTE) of the first laminate layer is approximately the same as the second laminate layer, and wherein a CTE of the flip-chip is not the same as the CTE of the first laminate layer or a CTE of the second laminate layer;
wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the first layer is in a range of about 9 to 16 parts per million per °C.
Lin et al. discloses in paragraph [0003], [0049] and claim 2
wherein a CTE of the flip-chip [2.6-2.8 ppm/° C] is not approximately the same as either the CTE of the first lamiate layer or a CTE of the second laminate layer;
wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C [2.6-2.8 ppm/° C], and the CTE value of the first laminate layer is in a range of about 9 to 16 parts per million per °C [16ppm/°C].
Doany et al. discloses in Fig. 3, paragraph [0024], [0026]-[0028], [0036]-[0037]
wherein a coefficient of thermal expansion (CTE) of the first laminate layer [108] is approximately the same as the second laminate layer [102], and wherein a CTE of the flip-chip [106] is not the same as the CTE of the first laminate layer [108] or a CTE of the second laminate layer [102][“the CTE of the spreader can be matched to the silicon photonics die instead of the CTE of the laser die”; “the laser die 106 can be disposed on the carrier die 108…To mitigate the effects of thermal expansion, the CTE of the spreader 102 and the CTE of the carrier die 108 can be matched.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin et al. and Doany et al. into the method of Dogiamis et al. to include wherein a coefficient of thermal expansion (CTE) of the first laminate layer is approximately the same as the second laminate layer, and wherein a CTE of the flip-chip is not the same as the CTE of the first laminate layer or a CTE of the second laminate layer; wherein the CTE value of the flip-chip is in a range of about 2 to 5 parts per million per °C, and the CTE value of the first layer is in a range of about 9 to 16 parts per million per °C. The ordinary artisan would have been motivated to modify Dogiamis et al. in the above manner for the purpose of providing suitable CTE values of the first/second layer and the flip chip and maintaining device alignment to improve the heat sink assembly performance [Abstract, paragraph [0036] of Doany et al., claim 2 of Lin et al.].
Regarding claim 17, Dogiamis et al. discloses in Fig. 5B
a thermal shunt [vertical portions of 585 and 528] sandwiched between the first laminate layer [510] and the second laminate layer [horizontal portions of 585 and 528], wherein the thermal shunt [vertical portions of 585 and 528] is configured to direct heat from the first laminate layer [510] to the second laminate layer [horizontal portions of 585 and 528].
Regarding claims 19-20, Dogiamis et al. discloses in Fig. 5B
wherein the second laminate layer comprises a heat spreader [horizontal portion of 585], and wherein the heat spreader is attached to the flip-chip [530];
wherein: the plurality of devices further comprises a second flip-chip [520];
the second flip-chip [520] comprises a second active side;
the second laminate layer [horizontal portions of 585 and 528] further comprises a second heat spreader [horizontal portion of 528];
the second active side is positioned opposite of, and is electrically connected to, the first laminate layer [510]; and
the second heat spreader [horizontal portion of 528] is attached to the second flip-chip [520].
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
