CTNF 18/908,445 CTNF 91104 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Preliminary Amendment The preliminary amendment received 12/17/2024 has been entered. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-27 of U.S. Patent No. US 12148063 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations in claim 1 is anticipated by claim 1 of the U.S. Patent No. US 12148063 B2 . Application 18908445 Claim 1 U.S. Patent No. US 12148063 B2 Claim 1 A multi-chip module accelerator usable to execute tensor data processing operations, the multi-chip module accelerator comprising: A multi-chip module accelerator usable to execute tensor data processing instructions, the multi-chip module accelerator comprising: a multi-chip module comprising: a multi-chip module comprising: an interconnect to a host processor; a plurality of distinct chips integrated on the multi-chip module; a memory stack including multiple memory dies; and a memory stack including multiple memory dies; and parallel processor circuitry communicatively coupled to the memory stack, the parallel processor circuitry comprising multiprocessor cores to execute matrix multiplication and accumulate operations, a multiprocessor core configured to execute a single instruction to perform matrix multiplication and accumulate operations; parallel processor circuitry communicatively coupled to the memory stack, the parallel processor circuitry comprising a plurality of multiprocessor cores distributed across the plurality of distinct chips, each of the plurality of multiprocessor cores configured to execute a single instruction to perform multiple matrix multiplication and accumulate operations; wherein: wherein: the matrix multiplication and accumulate operations comprise floating-point operations; the matrix multiplication and accumulate operations comprise floating-point operations; the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions and include a plurality of concurrent multiply operations; the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions, the two-dimensional matrix multiply and accumulate operations including a plurality of concurrent multiply operations; the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and the first operation comprises a multiply having at least one 16-bit floating- point input and the second operation comprises an accumulate having a 32-bit floating-point input. the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input. 2. The multi-chip module accelerator of claim 1, wherein the memory stack comprises high bandwidth memory. 2. The multi-chip module accelerator of claim 1, wherein the memory stack comprises high bandwidth memory. 3. The multi-chip module accelerator of claim 1, wherein the memory stack is comprised in a common physical package with the parallel processor circuitry. 3. The multi-chip module accelerator of claim 1, wherein the memory stack is comprised in a same physical package as the parallel processor circuitry. 4. The multi-chip module accelerator of claim 1, wherein the first operation is at a 16-bit precision, and the second operation is at a 32-bit precision. Claim 1 5. The multi-chip module accelerator of claim 1, wherein the first operation involves two or more 16-bit floating-point inputs. 5. The multi-chip module accelerator of claim 1, wherein the first operation involves two or more 16-bit floating-point inputs. 6-20 6-27 Allowable Subject Matter Claims 1-20 would be allowable if overcoming the double patenting rejections above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hai Tao Sun whose telephone number is (571)272-5630. The examiner can normally be reached 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Daniel Hajnik can be reached at 5712727642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAI TAO SUN/Primary Examiner, Art Unit 2616 Application/Control Number: 18/908,445 Page 2 Art Unit: 2616 Application/Control Number: 18/908,445 Page 3 Art Unit: 2616
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