DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 30, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant's amendments to the claims have overcome the objection and the 35 U.S.C. 112(b) rejections previously set forth in the Non-Final Office Action mailed January 2, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bhavsar et al. (US 2021/0271619) and Cheng et al. (US 2024/0330214).
Regarding claim 1, Bhavsar et al. disclose:
An apparatus comprising:
a first memory device (FIG. 1 devices 132, 136; [0011] one or more associated memory devices) coupled to a memory module management control (M3C) bus (FIG. 1 I3C bus 130 (bus 0)) and configured to provide, over the M3C control bus, a first in-band interrupt (IBI) message ([0013] the I3C interface provides for I3C slave devices to issue in-band interrupts (IBI) over the two-wire interface) having a first unique identifier ([0003] a first I3C address) and corresponding to a first category ([0015] the associated functions monitored…a low I3C address is generating a large number of interrupts to report power delivery issues);
a second memory device (FIG. 1 devices 132, 136; [0011] one or more associated memory devices) coupled to the M3C bus (FIG. 1 I3C bus 130 (bus 0)) and configured to provide, over the M3C control bus, a second IBI message ([0013] the I3C interface provides for I3C slave devices to issue in-band interrupts (IBI) over the two-wire interface) having a second unique identifier ([0003] a second I3C address) and corresponding to a second category ([0015] the associated functions monitored; [0016] BMC 110 can infer that the I3C slave interfaces associated with the temperature sensors on the DIMMs are in fact issuing IBIs related to temperature events), wherein the first unique identifier is lower than the second unique identifier ([0003] the second I3C address being higher than the first I3C address);
a memory module control hub (FIG. 1 a baseboard management controller (BMC) 110) configured to receive the first IBI message and the second IBI message (FIG. 2; [0019] BMC records a number of clock cycles utilized in receiving each I3C slave interface's IBIs in block 204), wherein, in response to the second category corresponding to higher priority message than the first category, the memory module control hub is configured to dynamically assign priority bits of the second unique identifier in the second IBI message to change the second unique identifier to be lower than the first unique identifier ([0017] BMC 110 can determine that, for example, a large number of IBIs are being received from the I3C slave interfaces associated with the RCDs of the DIMMs that are related to the occurrence of correctable memory errors on the DIMMs, and are starving the I3C slave interfaces associated with the temperature sensors. In this case, BMC 130 may determine that the occurrence of temperature events are of greater priority than the reporting of correctable memory errors, and can assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs; [0018] BMC 110 operates to reassign I3C addresses…so that when a lower I3C address is needed, an unused I3C address can be assigned to a particular I3C slave interface…BMC 110 can manage the priorities of IBIs by reassigning only a particular I3C slave interface)…the second IBI message…having higher priority over the first IBI message ([0017] assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs).
Bhavsar et al. do not appear to explicitly teach “to send” the second IBI message “to a host over a module control bus.” However, Cheng et al. disclose:
to send the second IBI message to a host over a module control bus (FIG. 1; [0053] interrupt requests 108 from the plurality of source peripheral component requesting client devices 104 for the target device 102 such as a host processer and serially arbitrates among them and selects one of the interrupt requests for processing; [0002])
Bhavsar et al. and Cheng et al. are analogous art because Bhavsar et al. teach overcoming in-band interrupt starvation and Cheng et al. teach message signaled interrupts.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Bhavsar et al. and Cheng et al. before him/her, to modify the teachings of Bhavsar et al. with the Cheng et al. teachings of sending the interrupt message to a host because sending a message to interrupt a host, such as a host processor, would have amounted to little more than combining "familiar elements according to known methods" and would have been obvious because it would have done "no more than yield predictable results." (MPEP 2143 I.A.) Interrupt messaging is a well-known technique used to request interrupt service. Modifying the teachings of Bhavsar et al. with the teachings of Cheng et al. would have yielded the predictable result of notifying the host of an interrupt request.
Regarding claim 2, Bhavsar et al. further disclose:
The apparatus of claim 1, wherein the memory module control hub is configured to determine a priority associated with the first category of the first IBI message and a priority associated with the second category of the second IBI message to determine which has a higher priority ([0017] BMC 110 can determine that, for example, a large number of IBIs are being received from the I3C slave interfaces associated with the RCDs of the DIMMs that are related to the occurrence of correctable memory errors on the DIMMs, and are starving the I3C slave interfaces associated with the temperature sensors. In this case, BMC 130 may determine that the occurrence of temperature events are of greater priority than the reporting of correctable memory errors, and can assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs, or assign the I3C slave interfaces associated with the RCDs higher I3C addresses than the I3C slave interfaces associated with the temperature sensors).
Regarding claim 3, Bhavsar et al. further disclose:
The apparatus of claim 3, wherein the memory module control hub (FIG. 1 a baseboard management controller (BMC) 110) includes an IBI priority circuit (FIG. 1 BMC; it would be obvious to one skilled in the art before the effective filing date of the claimed invention that the BMC, which dynamically assigns priority bits, has a logic circuit for performing the assigning of the priority bits) comprising logic to dynamically assign the priority bits for the second identifier based on the second category ([0017] BMC 130 may determine that the occurrence of temperature events are of greater priority than the reporting of correctable memory errors, and can assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs).
Regarding claim 7, Bhavsar et al. further disclose:
The apparatus of claim 1, wherein the second category includes over-temperature message or an error correction code defect message ([0017] BMC 130 may determine that the occurrence of temperature events are of greater priority…) and the first category includes a different type of message ([0017] … than the reporting of correctable memory errors).
Regarding claim 8, Bhavsar et al. further disclose:
The apparatus of claim 1, wherein the memory module control hub is configured to assign priority bits of the first unique identifier based on the first category ([0018] where the I3C address space is closely assigned, that is, with few unused I3C address between the I3C slave interfaces, when BMC 110 needs to manage the priorities of IBIs, the BMC may need to reassign several I3C addresses to insert a higher priority IBI into the I3C address space).
Regarding claim 15, Bhavsar et al. disclose:
A method comprising:
receiving, at a memory module control hub (FIG. 1 a baseboard management controller (BMC) 110) from a first memory device (FIG. 1 devices 132, 136; [0011] one or more associated memory devices) over a memory module management control (M3C) bus (FIG. 1 I3C bus 130 (bus 0)), a first in-band interrupt (IBI) message ([0013] the I3C interface provides for I3C slave devices to issue in-band interrupts (IBI) over the two-wire interface) corresponding to a first category ([0015] the associated functions monitored…a low I3C address is generating a large number of interrupts to report power delivery issues) and having a first unique identifier ([0003] a first I3C address);
receiving, at the memory module control hub (FIG. 1 a baseboard management controller (BMC) 110) from a second memory device (FIG. 1 devices 132, 136; [0011] one or more associated memory devices) over the M3C bus (FIG. 1 I3C bus 130 (bus 0)), a second IBI message ([0013] the I3C interface provides for I3C slave devices to issue in-band interrupts (IBI) over the two-wire interface) corresponding to a second category ([0015] the associated functions monitored; [0016] BMC 110 can infer that the I3C slave interfaces associated with the temperature sensors on the DIMMs are in fact issuing IBIs related to temperature events) and having a second unique identifier ([0003] a second I3C address);
in response to the second category corresponding to higher priority message than the first category, dynamically assigning priority bits of the second unique identifier in the second IBI message to be lower than priority bits of first unique identifier ([0017] BMC 110 can determine that, for example, a large number of IBIs are being received from the I3C slave interfaces associated with the RCDs of the DIMMs that are related to the occurrence of correctable memory errors on the DIMMs, and are starving the I3C slave interfaces associated with the temperature sensors. In this case, BMC 130 may determine that the occurrence of temperature events are of greater priority than the reporting of correctable memory errors, and can assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs; [0018] BMC 110 operates to reassign I3C addresses…so that when a lower I3C address is needed, an unused I3C address can be assigned to a particular I3C slave interface…BMC 110 can manage the priorities of IBIs by reassigning only a particular I3C slave interface)…the second IBI message…priority over the first IBI message ([0017] assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs).
Bhavsar et al. do not appear to explicitly teach “to give” the second IBI message “to a host over a module control bus.” However, Cheng et al. disclose:
to give the second IBI message to a host over a module control bus (FIG. 1; [0053] interrupt requests 108 from the plurality of source peripheral component requesting client devices 104 for the target device 102 such as a host processer and serially arbitrates among them and selects one of the interrupt requests for processing)
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 16, Bhavsar et al. further disclose:
The method of claim 15, further comprising determining a priority associated with the first category of the first IBI message and a priority associated with the second category of the second IBI message to determine which has a higher priority ([0017] BMC 110 can determine that, for example, a large number of IBIs are being received from the I3C slave interfaces associated with the RCDs of the DIMMs that are related to the occurrence of correctable memory errors on the DIMMs, and are starving the I3C slave interfaces associated with the temperature sensors. In this case, BMC 130 may determine that the occurrence of temperature events are of greater priority than the reporting of correctable memory errors, and can assign the I3C slave interfaces associated with the temperature sensors lower I3C addresses than the I3C slave interfaces associated with the RCDs, or assign the I3C slave interfaces associated with the RCDs higher I3C addresses than the I3C slave interfaces associated with the temperature sensors).
Regarding claim 19, Bhavsar et al. further disclose:
The method of claim 15, wherein the second category includes over-temperature message or an error correction code defect message ([0017] BMC 130 may determine that the occurrence of temperature events are of greater priority…) and the first category includes a different type of message ([0017] … than the reporting of correctable memory errors).
Allowable Subject Matter
Claims 11-14 are allowed.
The reasons for allowing the claims are considered to be clear (see 37 CFR 1.104 (e)) in light of the application’s prosecution. While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Bhavsar et al. and Cheng et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date as discussed in the Non-Final Rejection mailed January 2, 2026.
Claims 4-6, 9-10, 17-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims, 4-6, 10, 17-18, the prior art of Bhavsar et al. and Cheng et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date as discussed in the Non-Final Rejection mailed January 2, 2026.
Regarding claims 9 and 20, Shrivastava et al. (US 2021/0318903) disclose a 32-bit interrupt packet that comprises a one-bit or multi-bit priority field (paragraph [0017]). However, Shrivastava et al. do not appear to disclose that the priority field in the two most significant bits of the packet. Therefore, the prior art of Bhavsar et al., Cheng et al., and Shrivastava et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 9, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The apparatus of claim 1, wherein the priority bits of the second unique identifier comprises two most significant bits of the second unique identifier.”
Regarding claim 20, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The method of claim 15, wherein the priority bits of the second unique identifier comprises two most significant bits of the second unique identifier.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed March, 2026 have been fully considered but they are not persuasive.
Applicant argues that Bhavsar et al. do not disclose the memory module control hub of claim 1. The examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the address for the slave interface of Bhavsar does not include a portion that remains unchanged) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the 35 U.S.C. 103 rejection over Bhavsar et al. and Cheng et al., as discussed above, is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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