Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification
The disclosure is objected to because of the following informalities:
Paragraph [76] of the originally filed Specification has two inconsistent numeral references with the Drawings. “router 440” should read “router 540”, and “global buffer (GLB) 450” should read “global buffer (GLB) 550”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 5, 7, 8, 11, 13, 14, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Alvarez-Icaza Rivera et al. U.S. PGPUB No. 2016/0323137 in view of Gray, U.S. PGPUB No. 2016/0344629 (Gray was cited in the IDS filed 10/7/2024).
Per Claim 1, Alvarez-Icaza Rivera discloses:
a many-core neural network (NN) accelerator (Paragraph 60, Fig. 5; on-board neural network system 115), comprises:
a plurality of routers (Paragraph 73, Fig. 7A-7C; routers 110),
a routing control circuit (Paragraph 52, Fig. 6; chip configuration unit 109),
and a plurality of cores respectively coupled to the plurality of routers to form a Network-on-Chip (NoC) (Paragraphs 73-78, Figures 7A-7C; Cores 10 and routers 110);
wherein: for a given core of the plurality of cores, the routing control circuit of the router coupled to the given core is configured to:
detect defective cores within the NoC (Paragraphs 52 and 80; Fig. 8 numeral 202 [Wingdings font/0xE0] yes);
classify the defective cores as defective-with-bypass (Paragraphs 75, 76, 81, and 82, Figures 7B and 8; If a non-router core unit defect is detected, but the router is not faulty, communications can be passed through the core via the router to other neighboring cores.) or defective-without-bypass (Paragraphs 77, 78, and 83, Figures 7C and 8; If a core has faulty components and the faulty component is a faulty router, numeral 208, then the router of the core can’t be used, i.e. no bypass option.);
and dynamically reconfigure the NoC by adjusting routing paths to exclude the defective cores classified as defective-without-bypass and to keep the defective cores classified as defective-with-bypass as passive conduits for data routing (Paragraphs 75-76, Figure 7B; “To recover from the non-router core unit defect, all computation is programmed around the non-router core unit defect by disabling the hardware core circuit with corresponding physical label (1,0) (e.g., setting/activating the KILLSWITCH bit). The corresponding packet router 110 for the hardware core circuit with corresponding physical label (1,0) maintains its router functionality.”; Paragraphs 81-82, Figure 8; “In process block 209, all computation is programmed around the faulty non-router core unit.”).
Alvarez-Icaza Rivera teaches a routing system for routing data between the core circuits 10 (Paragraph 45), but does not specifically teach that each router comprises a routing control circuit as claimed.
However, Gray, similar to Alvarez-Icaza Rivera, teaches a NoC (150/299) comprising a plurality of routers (Paragraph 53, Fig. 2B; Routers 200-232) coupled to a plurality of cores in a row and column matrix arrangement utilizing unidirectional ring bus structure (Paragraph 53, Fig. 2B; cores 290-292 and additional unnumbered cores). Gray further teaches that each router comprises a routing control circuit configured to manage routing logics for data read from a coupled core and data received from another router (Paragraphs 44, 54, 94, and 269, Figure 3; Routing circuit 350 uses received inputs to control the flow of data between client core 390 as well as to other interconnected routers.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the NoC router, having the local routing control circuit, of Gray within the chips of Alvarez-Icaza Rivera because it provides beneficial routing functionality such as configurable ultra-wide links, routing functions, multicast support, switch-energy reduction, etc. (Gray; Paragraph 45).
Per Claim 2, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein to classify the defective cores, the routing control circuit is configured to: classify a core as defective-with-bypass in response to an internal buffer of the core is inaccessible (Paragraph 47, Fig. 3 discloses that the core array 112 comprises buffers for buffering incoming data path 111 data. Paragraphs 75 and 82 disclose that a core circuit (which includes the buffer(s)) is faulty but the router of the core can be operated with the core in a defective with bypass state.).
Per Claim 4, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein to dynamically reconfigure the NoC, the routing control circuit is configured to adjust physical to logical address mappings (Paragraphs 73-78; Physical label and logical mapping).
Per Claim 5, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein to dynamically reconfigure the NoC, the routing control circuit is configured to disable a port of the router coupled to a core classified as defective-without-bypass (Paragraph 64, 69, 77, and 78).
Per Claim 7, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein to dynamically reconfigure the NoC, the routing control circuit is configured to downgrade the NoC to a smaller configuration with a smaller number of cores and routers (Paragraph 64; Disabling a row/column of the core array 112 due to failed/faulty packet router represents a “downgrade” to the NoC.).
Per Claim 8, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein the plurality of cores are arranged, in a logic view, as a matrix, each row of the matrix comprising a same number of cores (Figure 3), and the router coupled to the given core comprises three ports, including a first port connected the given core to a horizontal ring formed by a row of cores, a second port connected the given core to a vertical ring formed by a column of cores, and a third port connected to an internal buffer of the given core (Figure 3 shows the routers comprising ports for vertical and horizontal connection to neighboring cores. Paragraph 47, Fig. 3 discloses that the core array 112 comprises buffers for buffering incoming data path 111 data.).
Per Claim 11, Alvarez-Icaza Rivera discloses the NN accelerator of claim 1, wherein the routing control circuit of the router is further configured to manage routing logics for data read from an internal buffer of the coupled core and data received from another router (Paragraphs 44, 54, 94, and 269, Figure 3; Routing circuit 350 uses received inputs to control the flow of data between client core 390 as well as to other interconnected routers. Paragraph 47, Fig. 3 discloses that the core array 112 comprises buffers for buffering incoming data path 111 data.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the NoC router, having the local routing control circuit, of Gray within the chips of Alvarez-Icaza Rivera because it provides beneficial routing functionality such as configurable ultra-wide links, routing functions, multicast support, switch-energy reduction, etc. (Gray; Paragraph 45).
Per Claims 13, 14, 17, and 19, please refer to the above rejection of claims 1, 8, 7, and 5, respectively, as the limitations are substantially similar and the mapping of the references to the limitations is equally applicable.
Allowable Subject Matter
Claims 3, 6, 9, 10, 12, 15, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Per claims 3 and 20, no combination of Alvarez-Icaza Rivera, Gray, and the prior art specifically teaches each of the inner, middle, and outer layer NoC’s with respect to the specific components each is claimed to be interconnected with, in combination with the limitations of the independent claim.
Per Claims 6 and 18, no combination of Alvarez-Icaza Rivera, Gray, and the prior art specifically teaches detecting the defective cores in the manner claimed, when considered in combination with the limitations of the independent claim.
Per Claims 9, 10, 15, and 16, no combination of Alvarez-Icaza Rivera, Gray, and the prior art specifically teaches classifying the defective cores in the manner claimed with respect to the three ports of the router, when considered in combination with the limitations of the base claim 8/14 and independent claim 1/13.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Prior Art
Prior art references U.S. Patent No. 12,072,834 and U.S. PGPUB No. 2026/0017226 comprise teachings similar to the claimed invention (See paragraphs 73-78 for teachings of defective with and without bypass.) but the references do not qualify as prior art due to their later effective filing dates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Brian T Misiura/
Primary Examiner, Art Unit 2175