DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the RCE and amendment filed on 9/3/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/3/2026 has been entered.
Claims 1 and 21-22 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti et al. (2011/0173391), Lai et al. (US 2018/0336143), Mehrotra (US 6,226,713), and Lee et al. (US 6,170,040).
With respect to claim 1, Venkumahanti teaches of a system comprising: a cache comprising first sub-cache (fig. 1, item 104; paragraph 16; L1 cache);
a second sub-cache (fig. 1-2, item 108; paragraph 16, 30; where the first portion of L2 is accessed in parallel with L1),
a cache controller (fig. 5; paragraph 43-45; the DSP is analogous to the claimed cache controller), wherein:
the second sub-cache includes a set of lines (paragraph 30; where the L2 memory is composed of cache lines),
each line of the set of lines is configured to operate in a first manner to store data (paragraph 18, 30-31; where a request to access data at a specific address is provided to first portion 108. As a data request typical of cache memories is sent to the first portion 108, it is clear to one of ordinary skill in the art that the first portion stores a set of data).
Venkumahanti fails to explicitly teach of (1) the first sub-cache and the second sub-cache having a same cache level, (2) the second sub-cache includes a set of line type bits; (3) wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines; (4) each line of the set of lines is configured to operate in a first manner to store data associated with a write-miss or a second manner to store data associated with an eviction of a cache entry from the first sub-cache; (5) the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache.
However, Lai teaches of the first sub-cache and the second sub-cache having a same cache level (fig. 1; paragraph 16; where the fast and slow caches are at the same cache level and are queried concurrently).
Venkumahanti and Lai fails to explicitly teach of (1) the second sub-cache includes a set of line type bits; (2) wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines; (3) each line of the set of lines is configured to operate in a first manner to store data associated with a write-miss or a second manner to store data associated with an eviction of a cache entry from the first sub-cache; (4) the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache.
However, Mehrotra teaches of each line of the set of lines is configured to operate in a first manner to store data associated with a write-miss or a second manner to store data associated with an eviction of a cache entry from the first sub-cache (fig. 5; column 12, lines 30-36 and column 12, line 48-column 13, line 15; where the L2 cache contains a miss queue that stores the address of a miss and the returned miss data).
The combination of Venkumahanti, Lai, and Mehrotra fails to explicitly teach of (1) the second sub-cache includes a set of line type bits; (2) wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines; (3) the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache.
However, Lee teaches of the second sub-cache includes a set of lines and a set of line type bits (fig. 3; abstract, column 4, lines 36-41, column 5, lines 1-4, column 6, lines 29-32; where the write buffer contains an x-buffer and a y-buffer (set of lines) and include multiple bit blocks that contain numerous bits including a ‘HIT’ bit for each line (set of line type bits));
wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines (fig. 3; abstract, column 4, lines 36-41, column 5, lines 1-4, column 6, lines 29-32; where each line in the write buffer contains a bit block that contain numerous bits including a ‘HIT’ bit for each line (set of line type bits));
the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache (fig. 3; abstract, column 5, lines 1-4, column 6, lines 29-32; where the ‘HIT’ bit indicates whether the information is written by a cache miss or that of a hit occurrence).
Venkumahanti and Lai are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti and Lai before the time of the effective filing of the claimed invention to incorporate the caches being at the same cache level which are queried in parallel in Venkumahanti as taught in Lai. Their motivation would have been to more efficiently use the cache memory (Lai, paragraph 14).
Venkumahanti, Lai, and Mehrotra are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, and Mehrotra before the time of the effective filing of the claimed invention to incorporate the miss, victim and write queues of Mehrotra into the cache of the combination of Venkumahanti and Lai. Their motivation would have been to more efficiently handle interaction between different cache levels (Mehrotra, column 3, lines 24-61).
Venkumahanti, Lai, Mehrotra, and Lee are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, and Lee before the time of the effective filing of the claimed invention to combine the miss and write queues of the combination of the combination of Venkumahanti, Lai, and Mehrotra into one write queue and incorporate the status ‘HIT’ bit as taught in Lee. Their motivation would have been to reduce the size and cost of the cache and improve the management of the cache memory.
With respect to claim 8, Venkumahanti teaches of wherein the cache controller is configured to: receive a write request; and determine whether the write request corresponds to a miss in the first sub-cache and, in parallel, determine whether the write request corresponds to a miss in the second sub-cache (paragraph 16, 20, 38-41, 48; where as the first portion of the level two memory and the level one memory are addressable in parallel, when the request is received, it is distributed to the level one memory and the sub-portion of level two memory and it is accessed to determine if there is a hit or miss in each portion).
Claim 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti, Lai, Mehrotra, and Lee as applied to claim 1 above, and further in view of Hansson et al. (US 2019/0384718).
With respect to claim 2, the combination of Venkumahanti, Lai, Mehrotra, and Lee fails to explicitly teach of wherein the second sub-cache comprises a tag random access memory (RAM) configured to store a respective memory address for each line of a first subset of the set of lines associated with a write-miss.
However, Hansson teaches of wherein the second sub-cache comprises a tag random access memory (RAM) configured to store a respective memory address for each line of a first subset of the set of lines associated with a write-miss (fig. 5; paragraph 56; where in the event of a write miss, the cache controller allocates the data value and its corresponding tag to a new storage location in the cache).
Venkumahanti, Lai, Mehrotra, Lee, and Hansson are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, Lee and Hansson before the time of the effective filing of the claimed invention to incorporate the cache tag of Hansson in the combination of Venkumahanti, Lai, Mehrotra, and Lee. Their motivation would have been to enable quicker cache lookups.
Claims 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti, Lai, Mehrotra, and Lee as applied to claim 1 above, and further in view of Akenine-Moller et al. (US 2018/0089091).
With respect to claim 3 the combination of Venkumahanti, Lai, Mehrotra, and Lee fails to explicitly teach of wherein the second sub-cache comprises a byte-enable memory configured to store a respective byte-enable mask for each line of the set of lines associated with a write-miss.
However, Akenine-Moller teaches of wherein the second sub-cache comprises a byte-enable memory configured to store a respective byte-enable mask for each line of the set of lines associated with a write-miss (fig. 20; paragraph 178-183; where the cache supports byte masked access and a byte mask corresponds to each data block in the cache).
Venkumahanti, Lai, Mehrotra, Lee, and Akenine-Moller are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, Lee, and Akenine-Moller before the time of the effective filing of the claimed invention to incorporate the evicting of cache lines that contain more dirty blocks before evicting those that contain less dirty blocks using the byte mask taught in Akenine-Moller into the combination of Venkumahanti, Lai, Mehrotra, and Lee. Their motivation would have been to more efficiently use the cache memories.
With respect to claim 4, Akenine-Moller teaches of wherein the byte-enable memory includes memory positions corresponding with each line of the set of lines of the second sub-cache (fig. 20; paragraph 178-183; where each block of the cache line has a dirty bit and byte mask).
The reasons for obviousness is the same as indicated above with respect to claim 3.
Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti, Lai, Mehrotra, and Lee as applied to claim 1 above, and further in view of Cabot (US 2006/0143396).
With respect to claim 5, the combination of Venkumahanti, Lai, Mehrotra, and Lee fails to explicitly teach of wherein the set of line type bits is stored in a memory configured to store modified, exclusive, shared, and invalid (MESI) states of the set of lines in the second sub-cache.
However, Cabot teaches of wherein the set of line type bits is stored in a memory configured to store modified, exclusive, shared, and invalid (MESI) states of the set of lines in the second sub-cache (fig. 8c; paragraph 80; where the cache includes a 2-bit MESI field).
Venkumahanti, Lai, Mehrotra, Lee, and Cabot are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, Lee, and Cabot before the time of the effective filing of the claimed invention to incorporate the MESI protocol taught in Cabot into the combination of Venkumahanti, Lai, Mehrotra, and Lee. Their motivation would have been to maintain coherency in the cache (Cabot, paragraph 80).
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti, Lai, Mehrotra, and Lee as applied to claim 1 above, and further in view of Hum (US 6,078,992).
With respect to claim 6, the combination of Venkumahanti, Lai, Mehrotra, and Lee fails to explicitly teach of wherein the first sub-cache is a n-way set associative cache, and wherein the second sub-cache is a fully associative cache.
However, Hum teaches of wherein the first sub-cache is a n-way set associative cache, and wherein the second sub-cache is a fully associative cache (fig. 2; column 3, lines 55-64; where the L1 cache is either direct mapped or low set associative and the victim cache is fully associative).
Venkumahanti, Lai, Mehrotra, Lee, and Hum are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, Lee, and Hum before the time of the effective filing of the claimed invention to incorporate the associativity of the caches of Hum to the caches of the combination of Venkumahanti, Lai, Mehrotra, and Lee. Their motivation would have been to more efficiently use the cache memory.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkumahanti, Lai, Mehrotra, and Lee as applied to claim 1 above, and further in view of Tran (US 2012/0221793).
With respect to claim 7, Venkumahanti teaches of wherein the first sub-cache is a main cache, and wherein the second sub-cache is a cache in parallel with the main cache (fig. 1-2, item 108; paragraph 16, 30; where the first portion of L2 is accessed in parallel with L1).
The combination of Venkumahanti, Lai, Mehrotra, and Lee fails to explicitly teach of wherein the first sub-cache is a main cache, and wherein the second sub-cache is a victim cache in parallel with the main cache.
However, Tran teaches of wherein the first sub-cache is a main cache, and wherein the second sub-cache is a victim cache (fig. 2; paragraph 21-22; where a second L1 cache is a victim cache).
Venkumahanti, Lai, Mehrotra, Lee, and Tran are analogous art because they are from the same field of endeavor, as they are directed to cache memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Venkumahanti, Lai, Mehrotra, Lee, and Tran before the time of the effective filing of the claimed invention to incorporate the victim cache of Tran into the first portion of the L2 cache of the combination of Venkumahanti, Lai, Mehrotra, and Lee. Their motivation would have been to more efficiently use the cache memory.
Allowable Subject Matter
Claims 9-16 and 18-19 and 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to independent claims 9 and 18, the prior art fails to explicitly teach of, “determining to store a second indication in the first line type bit to indicate that the data stored in the first line is associated with an eviction from the first sub-cache,” in the context of each respective claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kruckemyer et al. (US 7,437,597) discloses multiple caches including a write-back cache that are at the same level and operate in parallel with each other.
Arimilli et al. (US 6,446,165) discloses at least two caches at said same level concurrently implement at least one of different (1) store-through/write-back policies (2) cache line replacement policies (3) coherence protocols or (4) prefetch behaviors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
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