Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/08/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Non-Statutory Type Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patenVpatents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIN25, or PTO/AIN26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.isp
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by the earlier claim. ln re Longi-759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Regarding claim 1, claim 1 of “reference patent US 12147697 B2” as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim 1 are matching in contents (while language is different) to reference claim 1 of reference patent US 12147697 B2. There is no new patentably distinct claim element in the instant claim.
Regarding claim 12, claim 8 of “reference patent US 12147697 B2” as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim 12 are matching in contents (while language is different) to reference claim 12 of reference patent US 12147697 B2. There is no new patentably distinct claim element in the instant claim.
Instant app #18/909,050
reference patent (US 12147697 B2), ref app#17/900,551
Regarding claim 1
Regarding claim 1
A device, comprising:
A device, comprising:
a first circuit configured to:
converter circuitry configured to:
receive an instruction formatted with a protocol; and
convert the instruction from the protocol to a protocol specific to a first memory circuit of a plurality of memory circuits;
logic circuitry configured to couple to the plurality of memory circuits, the logic circuitry configured to:
receive a first result from a first memory circuit;
receive a first result responsive to the instruction from the first memory circuit; and
receive a second result from a second memory circuit; and
combine the first result with a second result from a second memory circuit of the plurality of memory circuits into an output; and
combine the first and second results to generate a combined result; and
a second circuit configured to:
a Built In Self Test (BIST) circuit configured to:
determine a measured signature based on the combined result; and
determine a measured signature based on the output:
determine whether a fault exists in at least one of the first memory circuit or the second memory circuit based on a comparison of the measured signature with an expected signature.
and determine a fault in the plurality of memory circuits based on a comparison between the measured signature and an expected signature.
Regarding claim 12
Regarding claim 8
A method, comprising:
A method, comprising:
receiving a first result from a first memory circuit and a second result from a second memory circuit;
receiving an instruction in a format ;
combining the first and second results to generate a combined result;
and converting the instruction from the format to a first instruction in a first format specific to a first memory circuit of a plurality of memory circuits;
determining a measured signature based on the combined result; and
receiving a first result responsive to the first instruction from the first memory circuit;
determining whether a fault exists in at least one of the first memory circuit or the second memory circuit based on a comparison of the measured signature with an expected signature.
combining the first result with a second result from a second memory circuit of the plurality of memory circuits into an output, determining a measured signature based on the output:
and determining a fault in the plurality of memory circuits based on the measured signature and an expected signature
Regarding claim 2, claim 1 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim are matching in contents (while language is different) to reference claim of reference patent US 12147697 B2. There is no new patentably distinct claim element in the instant claim.
Regarding claim 13, claim 8 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim are matching in contents (while language is different) to reference claim of reference patent US 12147697 B2. There is no new patentably distinct claim element in the instant claim.
Regarding claim 3 and 14, claim 3 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim are matching in contents (while language is different) to reference claim of reference patent US 12147697 B2. converting operations to a third format for third memory circuit and converter circuitry to convert instructions/operations for second memory circuit seems to have similar teaching - converting operations/instructions to be applicable to the memory. There is no new patentably distinct claim element in the instant claim.
Regarding claim 14, this is a method claim corresponding to the device claim 3, and has the same double patenting issue with reference claim 3 as quoted above.
Regarding claim 4, 5 and 6, claim 5 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim are matching in contents (while language is different) to reference claim of reference patent US 12147697 B2. The teaching here in instant and reference claim is to select and produce output results from the memory circuits. There is no new patentably distinct claim element in the instant claim.
Regarding claim 15, 16 and 17, these are method claims corresponding to the device claim 4, 5 and 6 and has the same double patenting issue with reference claim 5 as quoted above.
Regarding claim 7, claim 4, 6 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements of the instant claim are matching in contents (while language is different) to reference claim. Being able to safely generate results in parallel implies it meets the power requirements to execute them in parallel. There is no new patentably distinct claim element in the instant claim.
Regarding claim 18, this is a method claim corresponding to the device claim 7, and has the same double patenting issue with reference claim 4, 6 as quoted above.
Regarding claim 8, claim 3 and 4 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements are matching in contents (while language is different) to reference claim. Instant claim 8 teaches converting operation into first and second format and broadcasting it and reference claim 3 teaches converting instructions/operations to the format executable by the target memory circuit and reference claim 4 teaches generating results in parallel which includes sending/broadcasting the converted operation/instruction to the target memories. There is no new patentably distinct claim element in the instant claim.
Regarding claim 9, 10 and 11, claim 1 of “reference patent US 12147697 B2” contains similar claim elements in the instant application and in the claims of “reference patent US 12147697 B2”. It seems that all the claim elements are matching in contents (while language is different) to reference claim. Instant claim 9 teaches operation is a read operation and obtaining results from memory in reference claim 1 implies it involves read operation. Claim 10 discloses first and second memory circuit of different type. Converting instructions specific to some memory circuit implies memory circuits are of different type. Claim 11 discloses combining the results using XOR gate and combining the results in reference claim 1 includes combining using XOR gate. There is no new patentably distinct claim element in the instant claims.
Regarding claim 19, this is a method claim corresponding to the device claim 9, and has the same double patenting issue with reference claim 1 as quoted above.
Regarding claim 20, this is a method claim corresponding to the device claim 11, and has the same double patenting issue with reference claim 1 as quoted above.
Potential Allowable Subject Matter
Claims 1-20 are currently not rejected in view of prior art on the grounds of 35 U.S.C 103, and could become allowable subject matter if the double patenting rejection is overcome.
The following is an Examiner's statement of reasons for allowance:
Claim 1 states, ‘A device, comprising: a first circuit configured to: receive a first result from a first memory circuit; receive a second result from a second memory circuit; and combine the first and second results to generate a combined result; and a second circuit configured to: determine a measured signature based on the combined result; and determine whether a fault exists in at least one of the first memory circuit or the second memory circuit based on a comparison of the measured signature with an expected signature.’
Prior art Takazawa et al. (US 20030222283 A1) [Takazawa]: [0010]-[0012]: teaches a semiconductor integrated circuit (converter) receiving and converting test data and address information (which are part of a read/write instruction/command) from the common test bus to the inherent access data width of each memory and then supply such test data and address information to the corresponding memory, thereby supplying in parallel the test data information from the common test bus to a plurality of memories to enable the parallel tests.
Takazawa discloses first circuit (converter circuit) converting first instruction to a format/protocol to be used by the memory circuit and receive data from memory. However, Takazawa did not explicitly disclose combining test result from multiple memory circuits.
Prior art Narayanan et al. (US 20170125125 A1) [Narayanan]: [0037] Teaches receiving output from memory circuits in response to first instruction (in response to applying test data) as one input to the comparator. Narayanan teaches applying test data to all memory circuits and receiving test result (output of the written data) from all memory circuits in parallel and includes first memory circuit as well. Also, teaches providing expected data with same delay for each memory 45 of each group by the response generator 44 simultaneously to each of the local comparators 46 in each group 48. The delay response generator 44 ensures that the expected data response is applied to local comparators 46 at the correct time for those local comparators 46 to compare the output of their associated embedded memories 45 with the corresponding expected response, in parallel with one another. Each local comparator 46 generates a pass/fail signature from the results of these comparisons in the memory test algorithm, and forwards that pass/fail signature to parallel test data comparator 47, which combines the results from local comparators 46 into data for return to BIST controller 40 for this memory type.
Takazawa/Narayanan discloses converting first instruction to a format/protocol to be used by the memory circuit and combining test data from multiple memory circuits.
However, Takazawa/Narayanan did not explicitly disclose combining test result from multiple memory circuits using second circuit/logic/instruction.
Prior art LEE (US 20160180966 A1) [Lee]: [0053] teaches one channel select signal selected between the first to fourth channel select signals CH_s0, CH_s1, CH_s2 and CH_s3 is enabled, the first comparison block 100 outputs the channel data corresponding to the enabled channel select signal as the first comparison signal Com1, and the combined output block 400 outputs the first comparison signal Com1 as the test result signal Test_R. Therefore, by outputting each of all channel data as a test result signal, it is possible to locate which memory cell or if the channel has a defect. Based on spec drawing Fig.2-Fig.4 second circuitry is a select or enable signal that allows (or prevents) test result from one of the memory circuit to be transferred (passed/allowed) to the next logic level to be combined with other test results from other memory circuits that is also transferred (passed/allowed) to the next logic level. In Lee allowed) to the next logic level. In Lee each channel is a memory block/circuit that is tested together and the output is either blocked/prevented or passed/allowed to be transferred to the next level of logic circuitry. In Lee each channel is a memory block/circuit that is tested together and the output is either blocked/prevented or passed/allowed to be transferred to the next level of logic circuitry.
However, Takazawa/Narayanan/Lee teaches comparing actual signature with expected signature for each memory block and then combines the output of compared data of different memory blocks/circuits.
However, no known prior art explicitly teaches combining the first result from first memory circuit with second result from second memory circuit to produce a single endpoint as described in instant art [0027], [0036] and as shown in Fig. 2 and Fig. 3 the output of the interconnect circuitry 108 and use this combined memory output to generate a measured/actual signature that is compared against an expected signature.
Independent claim 12 contains the same allowable claim limitation combining the first and second results to generate a combined result and determining a measured signature based on the combined result as is present in claim 1 and is potentially allowable for the same reasons as of claim 1.
Claims 2-11 are dependent on claim 1 and are therefore potentially allowable due at least to this dependence.
Claims 13-20 are dependent on claim 12 and are therefore potentially allowable due at least to this dependence.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammad Hasan whose telephone number is (571) 270 1737 (email: Mohammad.Hasan@uspto.gov). The examiner can normally be reached on 9am-5pm, Monday through Friday.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138