Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [1 - 20] are rejected under 35 U.S.C. 103 as being unpatentable over [ Lee et al. (Pub No. US 20130080858), hereinafter "Lee", in view of Kim (Pub No. US 20140047269), hereinafter "Kim" ].
As per claim 1, Lee significantly teaches a control circuit coupled to a memory through a plurality of channels, wherein the plurality of channels comprises a first channel (The memory controller 100 and the non-volatile memory device 200 ′ of FIG. 3 are connected to each other through a plurality of channels [Lee PP 106]), and the control circuit comprises (the memory controller 100 [Lee PP 0088]):
a storage circuit configured to store a plurality of read-voltage and an index register (The read retry table 115 stores information about a read level [Lee PP 0094], The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129], The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191]); and
a processor coupled to the storage circuit (the memory controller 100 includes a memory device (e.g., a random access memory (RAM)) 110 , a read retry table 115 , a central processing unit (CPU) 120 [Lee 0088], The CPU 120 controls data transmission among the memory device 110 , the host interface 130 , the ECC circuit 140 , and the non-volatile memory interface 150 through a bus 160 [Lee PP 0097]), wherein when an error occurs in a read operation of the first channel (If an ECC fail occurs in operation S 11 (e.g., the ECC circuit determines detected errors are uncorrectable), the memory controller 100 starts a read retry operation. [Lee PP 0190]), the processor is configured to perform a first retry-read test to the memory through the first channel (issuing a second read command that commands the non-volatile memory to perform a second read … with an operating parameter different than an operating parameter used in performing the first read [Lee PP 0006]) by sequentially using the plurality of read-voltage tables (The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129]) until the first retry-read test is successfully performed by using a target read-voltage table of the plurality of read-voltage tables (repeating these setting and receiving data operations until the error correction coding is completed and when the error correction coding is completed, resetting the non-volatile memory device and terminating the read operation. [Lee PP 0026]);
Lee does not explicitly teach “wherein when the first retry-read test is successfully performed by the processor, the processor determines whether to update the index register according to an analysis of a change history of a stored data in the index register”
However, Kim, in an analogous art, teaches wherein when the first retry-read test is successfully performed by the processor, the processor determines whether to update the index register according to an analysis of a change history of a stored data in the index register (A “history read level” may track read retry iterations that have previously resulted in read pass results. [Kim PP 0043], the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minima valley, and/or an evolving history of read voltage levels. [Kim PP 0056], pass information is accumulated and summed, and may store pass information detected during a previous read operation [Kim PP 0058]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 2, Lee does not explicitly teach “wherein the change history represents an adjustment process of the stored data in the index register within a preset period after the error occurs in the read operation of the first.”
However, Kim, in an analogous art, teaches wherein the change history represents an adjustment process of the stored data in the index register within a preset period after the error occurs in the read operation of the first channel (A “history read level” may track read retry iterations that have previously resulted in read pass results. [Kim PP 0043], pass information is accumulated and summed, and may store pass information detected during a previous read operation in the NVRAM [Kim PP 0058]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read, retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 3, Lee significantly teaches wherein the index register stores an original index value (To track the number of read retries, a read retry count or index i is initialized … The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191]), and the processor perform the first retry-read test through the first channel by using one of the plurality of read-voltage tables corresponding to the original index value (A read level corresponding to the read retry count (index) i may be retrieved from the read level table at that time. [Lee PP 0191], the read level that is set is based on a predetermined value in the read retry table 115 identified by the count i. [Lee PP 192]).
As per claim 4, lee does not explicitly teach “wherein when the first retry-read test is successfully performed by the processor, the processor determines whether the index register has been updated according to the analysis of the change history, so as to decide whether to update the index register.”
However, Kim, in an analogous art teaches wherein when the first retry-read test is successfully performed by the processor (performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell [Kim PP 0006]), the processor determines whether the index register has been updated according to the analysis of the change history (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minima valley, and/or an evolving history of read voltage levels. [Kim PP 0056], The controller 1300 may detect a variation tendency of a bit error rate based on a history of a bit error rate. [Kim PP 0057]), so as to decide whether to update the index register (storing updated pass information associated with the pass read retry iteration in the NVRAM. [Kim PP 007]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 5, Lee does not explicitly teach “wherein when the processor determines the index register has not been updated according to the analysis of the change history in a first period from when the error occurs in the read operation of the first channel to when the first retry-read test is successfully performed, the processor updates the index register by a target index value corresponding to the target read-voltage table; and wherein when the processor determines the index register has been updated according to the analysis of the change history in the first period, the processor does not update the index register by the target index value.”
However, Kim, in an analogous art teaches wherein when the processor determines the index register has not been updated according to the analysis of the change history in a first period from when the error occurs in the read operation of the first channel to when the first retry-read test is successfully performed (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], The controller 1300 may detect a variation tendency of a bit error rate based on a history of a bit error rate. [Kim PP 0057]), the processor updates the index register by a target index value corresponding to the target read-voltage table (the controller 1300 may determine a new read voltage level is mandated due to a detected variation tendency in threshold voltages. [Kim PP 0055]); and
wherein when the processor determines the index register has been updated according to the analysis of the change history in the first period (The controller 1300 may detect pass information of memory cells … from among other memory cells. [Kim PP 0056]), the processor does not update the index register by the target index value (control the NAND flash memory 1100 to perform the read retry operation according to the detected pass information [Kim PP 0056]).
As per claim 6, Lee significantly teaches wherein the plurality of channels comprises a second channel (In the memory system 20 , the memory controller 100 and the non-volatile memory device 200 ′ are connected through four channels A, B, C, and D. [Lee PP 0101]), and an update of the index register (a read retry count or index i is initialized [Lee PP 0191]) in the first period (If an ECC fail occurs … the memory controller 100 starts a read retry operation. [Lee PP 0190]) is associated with a second retry-read test to the memory performed by the processor through the first channel in the first period (the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197], The memory controller 100 determines whether to perform a third read retry (i.e., a fourth read operation on Page#k) according to a result of the ECC operation on the first retry data. [Lee PP 0165]).
As per claim 7, Lee significantly teaches wherein when the first retry-read test is successfully performed (The non-volatile memory device 200 reads data (i.e., first retry data) from the target page Page#k, and temporarily stores the first retry data in the cache register 221 - 11 . [Lee PP 0159], If the ECC is successfully completed in operations S 56 and S 59 , the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 206]), the processor updates the index register (a read retry count or index i is initialized [Lee PP 0191], the index (retry count) i is increased [Lee PP 0197]) by a relationship between the following two obtained by the analysis of the change history (The index i in the read retry table 115 may identify a read level corresponding to the index i [Lee PP 0191-0192], If an ECC fail occurs … the memory controller 100 starts a read retry operation. [Lee PP 0190]): (1) an original index value stored by the index register when the error occurs in the read operation of the first channel (a read retry count or index i is initialized [Lee PP 0191], If an ECC fail occurs … the memory controller 100 starts a read retry operation. [Lee PP 0190]); and (2) a target index value corresponding to the target read-voltage table (The index i in the read retry table 115 may identify a read level corresponding to the index i [Lee PP 0191-0192], The read retry table 115 stores information about a read level [Lee PP 0094]).
As per claim 8, Lee significantly teaches wherein when the processor determines the target index value is equal to the original index value according to the analysis of the change history, the processor does not update the index register by the target index value (If the ECC is successfully completed, the read retry operation is terminated [Lee PP 0206] successful ECC terminates retry, so the index is not changed); and when the processor determines the target index value is different from the original index value according to the analysis of the change history, the processor updates the index register by the target index value (if the ECC fails, the index I is increased [Lee PP 0197] ECC failure causes the index to be increased, updated to a different value).
As per claim 9, Lee significantly teaches an operation method applied to a control circuit, wherein the control circuit is coupled to a memory through a plurality of channels, the plurality of channels comprises a first channel (The memory controller 100 and the non-volatile memory device 200 ′ of FIG. 3 are connected to each other through a plurality of channels [Lee PP 106]), a storage circuit of the control circuit stores an index register and a plurality of read-voltage tables (The read retry table 115 stores information about a read level [Lee PP 0094], The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129], The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191]), and the operation method comprises:
when an error occurs in a read operation of the first channel (If an ECC fail occurs in operation S 11 (e.g., the ECC circuit determines detected errors are uncorrectable), the memory controller 100 starts a read retry operation. [Lee PP 0190]), performing a first retry-read test to the memory through the first channel (issuing a second read command that commands the non-volatile memory to perform a second read … with an operating parameter different than an operating parameter used in performing the first read [Lee PP 0006]) by sequentially using the plurality of read-voltage tables (The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129]) until the first retry-read test is successfully performed by using a target read-voltage table of the plurality of read-voltage tables (repeating these setting and receiving data operations until the error correction coding is completed and when the error correction coding is completed, resetting the non-volatile memory device and terminating the read operation. [Lee PP 0026]);
Lee does not explicitly teach “when the first retry-read test is successfully performed, determining whether to update the index register according to an analysis of a change history of a stored data in the index register”
However, Kim, in an analogous art, teaches when the first retry-read test is successfully performed, determining whether to update the index register according to an analysis of a change history of a stored data in the index register (A “history read level” may track read retry iterations that have previously resulted in read pass results. [Kim PP 0043], the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], pass information is accumulated and summed, and may store pass information detected during a previous read operation [Kim PP 0058]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 10, Lee does not explicitly teach “wherein the change history represents an adjustment process of the stored data in the index register within a preset period after the error occurs in the read operation of the first channel.”
However, Kim, in an analogous art, teaches wherein the change history represents an adjustment process of the stored data in the index register within a preset period after the error occurs in the read operation of the first channel (A “history read level” may track read retry iterations that have previously resulted in read pass results. [Kim PP 0043], pass information is accumulated and summed, and may store pass information detected during a previous read operation in the NVRAM [Kim PP 0058]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read, retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 11, Lee does not explicitly teach “wherein when the first retry-read test is successfully performed, determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises: determining whether the index register has been updated according to the analysis of the change history to decide whether to update the index register.”
However, Kim, in an analogous art, teaches wherein when the first retry-read test is successfully performed (performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell [Kim PP 0006]), determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises: determining whether the index register has been updated according to the analysis of the change history (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], The controller 1300 may detect a variation tendency of a bit error rate based on a history of a bit error rate. [Kim PP 0057]) to decide whether to update the index register (storing updated pass information associated with the pass read retry iteration in the NVRAM. [Kim PP 007]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read, retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 12, Lee does not explicitly teach “wherein determining whether the index register has been updated according to the analysis of the change history to decide whether to update the index register comprises: when determining the index register has not been updated according to the analysis of the change history in a first period from when the error occurs in the read operation of the first channel to when the first retry-read test is successfully performed, updating the index register by a target index value corresponding to the target read-voltage table; and when determining the index register has been updated according to the analysis of the change history in the first period, not updating the index register by the target index value.”
However, Kim, in an analogous art, teaches wherein determining whether the index register has been updated according to the analysis of the change history to decide whether to update the index register comprises: when determining the index register has not been updated according to the analysis of the change history in a first period from when the error occurs in the read operation of the first channel to when the first retry-read test is successfully performed (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], The controller 1300 may detect a variation tendency of a bit error rate based on a history of a bit error rate. [Kim PP 0057]), updating the index register by a target index value corresponding to the target read-voltage table (the controller 1300 may determine a new read voltage level is mandated due to a detected variation tendency in threshold voltages. [Kim PP 0055]); and when determining the index register has been updated according to the analysis of the change history in the first period (The controller 1300 may detect pass information of memory cells … from among other memory cells. [Kim PP 0056]), not updating the index register by the target index value (control the NAND flash memory 1100 to perform the read retry operation according to the detected pass information [Kim PP 0056]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read, retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 13, Lee significantly teaches wherein the plurality of channels comprises a second channel (In the memory system 20 , the memory controller 100 and the non-volatile memory device 200 ′ are connected through four channels A, B, C, and D. [Lee PP 0101]), and an update of the index register (a read retry count or index i is initialized [Lee PP 0191]) in the first period (If an ECC fail occurs … the memory controller 100 starts a read retry operation. [Lee PP 0190]) is associated with a second retry-read test to the memory through the second channel in the first period (the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197], The memory controller 100 determines whether to perform a third read retry (i.e., a fourth read operation on Page#k) according to a result of the ECC operation on the first retry data. [Lee PP 0165]).
As per claim 14, Lee significantly teaches wherein determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises (The memory controller 100 determines whether to perform a third read retry (i.e., a fourth read operation on Page#k) according to a result of the ECC operation on the first retry data. [Lee PP 0165]): updating the index register by a relationship between the following two obtained by the analysis of the change history (To track the number of read retries, a read retry count or index i is initialized [Lee PP 0191], if the ECC fails or otherwise determines errors in the retry data are uncorrectable in operation S 17 , the index (retry count) i is increased [Lee PP 0197]): (1) an original index value stored by the index register when the error occurs in the read operation of the first channel (a read retry count or index i is initialized [Lee PP 0191], If an ECC fail occurs … the memory controller 100 starts a read retry operation. [Lee PP 0190]); and (2) a target index value corresponding to the target read-voltage table (The index i in the read retry table 115 may identify a read level corresponding to the index i [Lee PP 0191-0192], The read retry table 115 stores information about a read level [Lee PP 0094]).
As per claim 15, Lee significantly teaches wherein updating the index register by the relationship obtained by the analysis of the change history comprises (The memory controller 100 determines whether to perform a third read retry (i.e., a fourth read operation on Page#k) according to a result of the ECC operation on the first retry data. [Lee PP 0165]): when determining the target index value is equal to the original index value according to the analysis of the change history, not updating the index register by the target index value (If the ECC is successfully completed in operations S 56 and S 59, the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 0206]); and when determining the target index value is different from the original index value according to the analysis of the change history, updating the index register by the target index value (if the ECC fails or otherwise determines errors in the retry data are uncorrectable in operation S 17, the index (retry count) i is increased [Lee PP 0197]).
As per claim 16, Lee significantly teaches an electronic device, comprising (memory system 20 [Lee PP 0087]): a memory (a non-volatile memory device 200 [Lee PP 0087]); and a control circuit coupled to the memory (The memory controller 100 and the non-volatile memory device 200 ′ of FIG. 3 are connected to each other [Lee PP 0106]), and configured to store a plurality of read-voltage tables and an index register (The read retry table 115 stores information about a read level [Lee PP 0094], The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129], The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191]), wherein the control circuit is configured to perform a first thread (If an ECC fail occurs in operation S 11 (e.g., the ECC circuit determines detected errors are uncorrectable), the memory controller 100 starts a read retry operation. [Lee PP 0190]), and the first thread is configured for: when an error occurs in a read operation of the first thread (If an ECC fail occurs in operation S 11 (e.g., the ECC circuit determines detected errors are uncorrectable), the memory controller 100 starts a read retry operation. [Lee PP 0190]), performing a first retry-read test to the memory (issuing a second read command that commands the non-volatile memory to perform a second read [Lee PP 0006]) by sequentially using the plurality of read-voltage tables (The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129]) until the first retry-read test is successfully performed by using a target read-voltage table of the plurality of read-voltage tables (repeating these setting and receiving data operations until the error correction coding is completed [Lee PP 026], he read level that is set is based on a predetermined value in the read retry table 115 identified by the count i. [Lee PP 0192]); and when the first retry-read test is successfully performed (If the ECC is successfully completed in operations S 56 and S 59 , the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 0206])
Lee does not explicitly teach “determining whether to update the index register according to an analysis of a change history of a stored data in the index register”
However, Kim, in an analogous art, teaches determining whether to update the index register according to an analysis of a change history of a stored data in the index register (A “history read level” may track read retry iterations that have previously resulted in read pass results. [Kim PP 0043], the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], pass information is accumulated and summed, and may store pass information detected during a previous read operation in the NVRAM 1200 . [Kim PP 0058]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 17, Lee significantly teaches wherein the control circuit is further configured to perform a second thread (the memory controller 100 and the non-volatile memory device 200 ′ are connected through four channels A, B, C, and D. [Lee PP 0101], The CPU 120 controls data transmission among the memory device 110 , the host interface 130 , the ECC circuit 140 , and the non-volatile memory interface 150 through a bus 160 . [Lee PP 0097])
determining whether the index register has been updated by the second thread according to the analysis of the change history to decide whether to update the index register (the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197], If the ECC is successfully completed in operations S 56 and S 59 , the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 0206]).
Lee does not explicitly teach “determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises”
However, Kim, in an analogous art, teaches determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 18, Lee significantly teaches updating the index register by a target index value corresponding to the target read-voltage table (The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191], the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197]),
not updating the index register by the target index value (If the ECC is successfully completed in operations S 56 and S 59 , the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 0206]).
Lee does not explicitly teach “wherein determining whether the index register has been updated by the second thread according to the analysis of the change history to decide whether to update the index register comprises: when determining the index register has not been updated by the second thread according to the analysis of the change history in a first period from when the error occurs in the read operation of the first thread to when the first retry-read test is successfully performed, when determining the index register has been updated according to the analysis of the change history in the first period”
However, Kim, in an analogous art, teaches wherein determining whether the index register has been updated by the second thread according to the analysis of the change history to decide whether to update the index register comprises: when determining the index register has not been updated by the second thread according to the analysis of the change history in a first period from when the error occurs in the read operation of the first thread to when the first retry-read test is successfully performed (the controller 1300 may detect variation tendencies for read voltage level(s) in relation to a determined (or newly determined) minimavalley, and/or an evolving history of read voltage levels. [Kim PP 0056], The controller 1300 may detect a variation tendency of a bit error rate based on a history of a bit error rate. [Kim PP 0057])
when determining the index register has been updated according to the analysis of the change history in the first period (The controller 1300 may detect pass information of memory cells, having a program/erase cycle similar to the detected program/erase cycle, from among other memory cells. [Kim PP 0056])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the read retry operation using sequential read voltages disclosed by Lee to incorporate Kim’s teaching of using stored read retry information, in order to improve read retry efficiency and memory system performance (Read retry operations often resolve read fails, but require a significant amount of time. Thus, while read retry operations facilitate data accuracy they tend to reduce memory system operating efficiency. [Kim PP 0005]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Lee’s invention.
As per claim 19, Lee significantly teaches wherein determining whether to update the index register according to the analysis of the change history of the stored data in the index register comprises (The read retry table 115 may store a change in the read level whenever a read count (e.g., an index “i”) increases [Lee PP 0129], The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191]): updating the index register by a relationship between the following two obtained by the analysis of the change history (the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197]): (1) an original index value stored by the index register when the error occurs in the read operation of a first channel (If an ECC fail occurs in operation S 11 … the memory controller 100 starts a read retry operation. [Lee PP 0190], a read retry count or index i is initialized [Lee PP 0191]); and (2) a target index value corresponding to the target read-voltage table (The index i in the read retry table 115 may identify a read level corresponding to the index i. [Lee PP 0191], The read retry table 115 stores information about a read level [Lee PP 0094]).
As per claim 20, Lee significantly teaches wherein updating the index register by the relationship obtained by the analysis of the change history comprises: when determining the target index value is equal to the original index value according to the analysis of the change history, not updating the index register by the target index value (If the ECC is successfully completed in operations S 56 and S 59 , the memory controller 100 transmits a reset command to the non-volatile memory device 200 in operation S 60 to terminate the read retry operation. [Lee PP 0206]); and when determining the target index value is different from the original index value according to the analysis of the change history, updating the index register by the target index value (the index (retry count) i is increased in operation S 18 and a read retry is repeated [Lee PP 0197]).
Conclusion
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112