Prosecution Insights
Last updated: July 17, 2026
Application No. 18/909,271

ASSET CONTROL SYSTEM

Final Rejection §102§103
Filed
Oct 08, 2024
Priority
Dec 23, 2019 — GB 1919132.9 +2 more
Examiner
MA, KAM WAN
Art Unit
2688
Tech Center
2600 — Communications
Assignee
E Track Ltd.
OA Round
2 (Final)
63%
Grant Probability
Moderate
3-4
OA Rounds
1y 0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 63% of resolved cases
63%
Career Allowance Rate
237 granted / 377 resolved
+0.9% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
35 currently pending
Career history
415
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
87.0%
+47.0% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 377 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-5 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maloney (US 2001/0006368 A1). Regarding claim 1, Maloney discloses a system for storing a plurality of tangible assets (e.g. Abstract & [0003-0004] & Figs. 5-9 and 13-17: vehicle keys), the system comprising: an RF component (e.g. Abstract & [0035] & Fig. 9: RFID tag), wherein the RF component is associable with a tangible asset (e.g. vehicle key), and wherein the RF component has a unique identifier (e.g. Fig. 5 & [0014, 0044]) and is configured to receive and modulate a carrier signal, wherein modulation of the carrier signal is based on the unique identifier (e.g. [0044]: RFID tag 62 receives carrier signal from RF sensor 63 and transmit a modulated signal with its identification code to the RF sensor); an RF detection system (e.g. Figs. 5-9 and 13-17), comprising: a plurality of RF coils (e.g. Abstract & [0014, 0065-0070] & Figs. 13-16: antenna), wherein each coil is arranged to emit a carrier signal and detect the modulated carrier signal (e.g. [0054]: antenna on plates 87, 88); a processor (e.g. Fig. 9: 64, 67) in communication with each of the plurality of RF coils, wherein: the processor is part of a microcontroller (e.g. [0006]), the microcontroller comprising a plurality of pin ports (e.g. Figs. 7, 13-14, 17); and each of the plurality of RF coils is connected to a corresponding, respective pin port of the microcontroller; and the processor is configured to: poll the plurality of RF coils by switching the pin ports to be output, one at a time in sequence, to selectively allow current to flow through one or more of the plurality of RF coils at a time [0052-0056, 0061, 0072]; and, identify the RF component based on modulation of the carrier signal (e.g. [0056]). Regarding claim 3, Maloney discloses the microcontroller has a peripheral pin selection (PPS) function allowing each pin port (e.g. [0006]: backplane and matrix) to be configured as an output of the carrier signal (e.g. [0044]: sequentially apply RF carrier signal to each RF sensors/antenna/coils). Regarding claim 4, Maloney discloses each of the pin ports is configured to be an output of the carrier signal in sequence (e.g. [0044]: sequentially apply RF carrier signal to each RF sensors/antenna/coils). Regarding 5, Maloney discloses the plurality of RF coils are connected to a corresponding pin port on a first side, and to the microcontroller on a second side thereof (e.g. Figs. 5, 7, 9, 10, 13, 14, 18 & [0006, 0048-0053]: sensors/antennas connected on one side of a PCB and microcontroller connected to other side of the PCB) Regarding claim 9, Maloney discloses the plurality of RF coils are arranged on a single printed circuit board (e.g. Figs. 7 and 12 & [0048, 0064]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maloney (US 2001/0006368 A1) in view of Hewett et al. (US 2020/0124696 A1). Regarding claim 6, Maloney discloses the plurality of RF coils are connected to a filter to remove the carrier signal on the second side, between the RF coils and the microcontroller (e.g. [0059-0060]: filter blocks DC voltages from being transferred back to RF source implies remove carrier signal since the source provide carrier signal to the sensors). Maloney fails to disclose, but Hewett teaches the plurality of RF coils are connected to a common peak detector (e.g. [0102]). Thus, it would have been obvious before the effective filing date of the claimed invention to have modified the teachings of Maloney with the teachings of Hewett to utilize peak amplitude detection so as to accurately determine location of a RFID tag. Regarding claim 7, Hewett teaches the microcontroller is configured to measure the peak to peak level from the active RF coil to determine returned signal amplitude (e.g. [0102]: distance between peaks corresponds signal strength/amplitude). Regarding claim 8, Hewett teaches the processor is further configured to determine the distance between the RF component and the one of the RF coils based on the peak amplitude of the modulated carrier signal (e.g. [0102]). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maloney (US 2001/0006368 A1). Regarding claim 10, Maloney discloses the plurality of RF coils are printed over 2 layers of a PCB (e.g. Figs. 7, 13 and 16). Maloney fails to disclose the plurality of RF coils are printed over 4 layers of a PCB. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to include plurality of RF coils over 4 layers of a PCB, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980), and mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 3-5 and 9-10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 5 of U.S. Patent No. 12,112,608 in view of Maloney (US 2001/0006368 A1). Regarding claim 1, the patent discloses the claimed invention except “the processor is part of a microcontroller, the microcontroller comprising a plurality of pin ports; and each of the plurality of RF coils is connected to a corresponding, respective pin port of the microcontroller”. However, Maloney teaches the processor is part of a microcontroller (e.g. [0006]), the microcontroller comprising a plurality of pin ports (e.g. Figs. 7, 13-14, 17); and each of the plurality of RF coils is connected to a corresponding, respective pin port of the microcontroller. Thus, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the teachings of the patent with the teachings of Maloney to include plurality of pin ports for each coils so as to allow polling of each coils individually. The patent discloses the claimed polling, but silent on the component for performing the polling. Maloney teaches a known in the art matrix selector for polling plurality of coils. Thus, the combination is merely simple substitutions of one known device with another according to KSR. Regarding claims 3-5, Maloney teaches the claimed invention (see 35 U.S.C. 102 rejections of claims 3-5 above). Regarding claim 9, claim 2 of the patent discloses the claimed invention. Regarding claim 10, claim 5 of the patent discloses the claimed invention. Claims 6-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 5 of U.S. Patent No. 12,112,608 in view of Maloney (US 2001/0006368 A1) and Hewett et al. (US 2020/0124696 A1). Regarding claims 6-8, the patent and Maloney in combination fails to disclose, but Hewett teaches the claimed invention (see rejection under 35 U.S.C. 103 above). Response to Arguments Applicant's arguments filed 04/23/2026 have been fully considered but they are not persuasive. In response to applicant’s arguments with respect to double patenting rejections, rejections have been updated in view of amendment. In response to applicant’s arguments with respect to amended claim 1, the examiner disagrees with the following reasons: Maloney, at least in Figures 5-9 and [0006, 0044], discloses plurality coils are connected to microcontroller (67) via matrix selector (64), and each of the coils respectively connected to a respective pin port of the matrix selector (e.g. Figures 7, 10, 16 and 17). The controller and matrix selector in combination discloses the claimed microcontroller. Therefore, Maloney discloses the claimed invention recited in claim 1. In additions, claims 3-10 are unpatentable at least in view of foregoing reasons and rejections set forth in current Office action. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAM WAN MA whose telephone number is (571)270-3693. The examiner can normally be reached M-F 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached on 571-270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAM WAN MA/Examiner, Art Unit 2688
Read full office action

Prosecution Timeline

Oct 08, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §102, §103
Apr 23, 2026
Response Filed
Jun 02, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
63%
Grant Probability
85%
With Interview (+21.7%)
2y 9m (~1y 0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 377 resolved cases by this examiner. Grant probability derived from career allowance rate.

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