DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 2-3, 5, and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06 February 2026.
Applicant’s election without traverse of Species III, corresponding to originally filed Claims 1, 4, and 6-10, in the reply filed on 06 February 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (hereinafter “Liu” US 2023 / 0274696).
As pertaining to Claim 1, Liu discloses (see Fig. 2 and Fig. 11) a display apparatus comprising:
a display panel (1000) having a display area (200) in which a plurality of subpixels (100) are disposed (see Page 5, Para. [0055]), each of the plurality of subpixels including (see Fig. 11):
a driving transistor (T7) connected to a first power line (VDD);
an emission control transistor (T8) connected to the driving transistor (T7), the emission control transistor (T8) supplied with an emission control signal (EM) at a gate electrode of the emission control transistor (T8);
a first light emitting element (32f);
a second light emitting element (32c), and
a plurality of mode control transistors (SW1, SW2, SW3, SW4, SW5, SW6) connected to the emission control transistor (T8), the first light emitting element (32f), and the second light emitting element (32c), the plurality of mode control transistors (SW1, SW2, SW3, SW4, SW5, SW6) including:
a plurality of first mode control transistors (SW4, SW5) electrically connected in parallel with each other and connected in series to the first light emitting element (32f; i.e., (SW4) and (SW5) are connected in series between a leftmost node of (SW4) and a cathode of (32f) via path (SW6)); and
a plurality of second mode control transistors (SW2, SW6) connected in series with each other and connected to the second light emitting element (32c; see Page 15 through Page 16, Para. [0230] and [0232]-[0234]).
As pertaining to Claim 4, Liu discloses (see Fig. 2 and Fig. 11) that the first light emitting element (32f) emits light when at least one of the plurality of first mode control transistors (SW4, SW5) is turned on, and the second light emitting element (32c) emits light when both of the plurality of second mode control transistors (SW2, SW6) are turned on (again, see Page 15 through Page 16, Para. [0230] and [0232]-[0234]).
As pertaining to Claim 6, Liu discloses (see Fig. 2 and Fig. 11) that a gate electrode of a first transistor (SW4) included in the plurality of first mode control transistors (SW4, SW5) receives a first mode control signal (see (SW4)), a gate electrode of a second transistor (SW5) included in the plurality of first mode control transistors (SW4, SW5) receives a second mode control signal (see (SW5)), a gate electrode of a first transistor (SW2) included in the plurality of second mode control transistors (SW2, SW6) receives a third mode control signal (see (SW2)), and a gate electrode of a second transistor (SW6) included in the plurality of second mode control transistors (SW2, SW6) receives a fourth mode control signal (see (SW6); again, see Page 15 through Page 16, Para. [0230] and [0232]-[0234]).
As pertaining to Claim 7, Liu discloses (see Fig. 2 and Fig. 11) that the display area (200) is divided into a plurality of blocks (i.e., arbitrary groupings of subpixels (100)) that each include subpixels (100) of the plurality of subpixels (100), and the subpixels (100) included in any one of the plurality of blocks (i.e., arbitrary groupings of subpixels) emit light simultaneously or do not emit light simultaneously (see Page 5, Para. [0069], [0071]-[0072], and [0077]; and Page 16, Para. [0233]-[0234]).
As pertaining to Claim 8, Liu discloses (see Fig. 2 and Fig. 11) that each of the plurality of blocks (i.e., arbitrary groupings of subpixels (100)) includes a first subpixel to a fourth subpixel (i.e., see any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2),
wherein the first transistor (SW4) included in the plurality of first mode control transistors (SW4, SW5) that are respectively included in the first subpixel to the fourth subpixel (i.e., again, any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2) are driven in a same manner (i.e., in the manner shown in Fig. 11),
wherein the second transistor (SW5) included in the plurality of first mode control transistors (SW4, SW5) that are respectively included in the first subpixel to the fourth subpixel (i.e., again, any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2) are driven in a same manner (i.e., in the manner shown in Fig. 11),
wherein the first transistor (SW2) included in the plurality of second mode control transistors (SW2, SW6) that are respectively included in the first subpixel to the fourth subpixel (i.e., again, any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2) are driven in a same manner (i.e., in the manner shown in Fig. 11), and
wherein the second transistor (SW6) included in the plurality of second mode control transistors (SW2, SW6) that are respectively included in the first subpixel to the fourth subpixel (i.e., again, any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2) are driven in a same manner (i.e., in the manner shown in Fig. 11; again, see Page 15 through Page 16, Para. [0230] and [0232]-[0234]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Hwang et al. (hereinafter “Hwang” US 2024 / 0420640).
As pertaining to Claim 9, Liu discloses (see Fig. 2 and Fig. 11) that the display panel (1000) further comprises:
a means configured to supply a plurality of mode control signals (see (SW1, SW2, SW3, SW4, SW5, SW6)) to each of the plurality of subpixels (i.e., see any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2), the plurality of mode control signals (again, see (SW1, SW2, SW3, SW4, SW5, SW6)) including the first mode control signal (SW4), the second mode control signal (SW5), the third mode control signal (SW2), and the fourth mode control signal (SW6); and
wherein each of the plurality of mode signal supply lines (again, see (SW1, SW2, SW3, SW4, SW5, SW6)) diverges from at least one node (i.e., any arbitrary node) and supplies the plurality of mode control signals (SW1, SW2, SW3, SW4, SW5, SW6) to the first subpixel to the fourth subpixel (again, see any arbitrary (32) in Fig. 11 corresponding to any (100) in Fig. 2; and see Page 15 through Page 16, Para. [0230] and [0232]-[0234]).
Liu does not explicitly disclose a data driver. However, the implementation of a data driver is implicit in the display panel (1000) disclosed by Liu in order to provide the driving signals necessary for the display panel (1000) to function.
Further, in the same field of endeavor, Hwang discloses (see Fig. 1 and Fig. 3) a display panel (110) having a display area (A) in which a plurality of subpixels (see (PX)) are disposed, wherein the subpixels (see (PX) in Fig. 3) include a driving transistor (T1), and emission control transistor (T6), a first light emitting element (EL1), a second light emitting element (EL2), and a plurality of mode control transistors (T9, T10), and wherein (see Fig. 1) a data driver (150) is connected to a plurality of blocks (i.e., arbitrary groupings of subpixels; see (PX)) through a plurality of mode signal supply lines (MCS) and the data driver (150) is configured to supply a plurality of mode control signals (see (GS_PU, GS_PR) in Fig. 3) to each of the subpixels (see (PX)), wherein each of the plurality of mode signal supply lines (MCS) diverges from at least one node (see (150); and see Page 2 through Page 3, Para. [0044]-[0047], [0051], and [0056]). It is a goal of Hwang to provide an efficient means for independently driving mode control signals in an display panel, analogous to that of Liu, such that viewing modes of the display panel may be effectively controlled and/or changed in various display areas independently (see Page 2, Para. [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liu with the teachings of Hwang, such that the display panel of Liu comprises a data driver as suggested by Hwang that is connected to the plurality of blocks through a plurality of mode signal supply lines to supply a plurality of mode control signals, in order to provide an efficient means for independently driving mode control signals in the display panel such that viewing modes of the display panel may be effectively controlled and/or changed in various display areas independently.
As pertaining to Claim 10, Hwang discloses (see Fig. 1 and Fig. 3) that the data driver (150) is disposed below the display panel (110) in a plan view of the display apparatus, and the plurality of mode signal supply lines (MCS) are disposed in a vertical direction of the display panel (110; again, see Page 2 through Page 3, Para. [0044]-[0047], [0051], and [0056]).
Response to Arguments
Applicant's arguments filed 09 July 2026 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, namely Liu, teach or fairly suggest at least “a plurality of first mode control transistors electrically connected in parallel with each other and connected in series to the first light emitting element” (see Remarks at Page 9). The examiner respectfully disagrees as Liu plainly discloses at Figure 11 a plurality of first mode control transistors (SW4, SW5) electrically connected in parallel with each other and connected in series to the first light emitting element (32f) between a leftmost node of (SW4) and a cathode of (32f) via path (SW6). The applicant has asserted that “Two elements are electrically connected in parallel only if both of their terminals are connected to the same two nodes, such that they share identical voltage potentials across their respective terminals” and “parallel devices must be directly connected between the same pair of nodes without any intervening circuit element” (see Remarks at Page 10). The examiner respectfully points out that the claimed invention neither recites nor requires “first mode control transistors” having “both of their terminals… connected to the same two nodes,” and further neither recites nor requires “directly connected” terminals “without any intervening circuit element.” As plainly shown in Figure 11 of Liu, the first mode control transistor (SW4) and the first mode control transistor (SW5) are electrically connected at a rightmost terminal. Further, leftmost terminals of the first mode control transistor (SW4) and the first mode control transistor (SW5) are electrically connected via (32e) at a leftmost terminal. A parallel connection of components merely requires that each component is placed on a separate branch between nodes such that current is divided between the separate branches. Liu clearly provides this structure with respect to (SW4) and (SW5).
For at least these reasons, the rejection of Claims 1, 4, and 6-10 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sato et al. (US 2024 / 0221665) and Keum et al. (US 11,871,622), submitted by the applicant via Information Disclosure Statement (IDS) on 08 October 2024, both disclose pixel circuits pertinent to that recited in Claim 1.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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