Prosecution Insights
Last updated: April 19, 2026
Application No. 18/909,915

LEVEL SHIFT CIRCUIT AND HIGH-VOLTAGE HALF-BRIDGE DRIVER CHIP

Non-Final OA §102§112
Filed
Oct 08, 2024
Examiner
NGUYEN, LONG T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Suteng Innovation Technology Co. Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
822 granted / 921 resolved
+21.3% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
26 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
18.1%
-21.9% vs TC avg
§102
37.5%
-2.5% vs TC avg
§112
33.9%
-6.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 921 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Specie III (Figures 12-13) in the reply filed on 01/27/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant indicates that claims 1-3 and 5-8 are readable on the elected Specie III (Figures 12-13). However, because claim 3 is found to be allowable and claim 4 depends on claim 3, so claim 4 is rejointed in this office action. Thus, claims 1-8 are being examined in this office action. Claims 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Specie, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/27/26. Specification The disclosure is objected to because of the following informalities: throughout the specification, “switch tube” is objected to because it is not clear what it means by “switch tube”. Based on the drawing, it appears that “switch tube” means “MOS transistor”, so it is suggested to change “switch tube” to “MOS transistor” throughout the specification. Similarly, throughout the specification, it is suggested to change “semiconductor tube” to “semiconductor transistor”. Appropriate correction is required. Claim Rejections - 35 USC § 112 Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For claim 1, throughout the claim, the recitation “switch tube” is indefinite because it is not clear what it means by “switch tube” as it is unclear the meaning of the technical features to which it refers. Based on the drawing, it appears that “switch tube” means “MOS transistor”, so it is suggested to change “switch tube” to “MOS transistor”. Further, claim 1 recites that both switch tubes and both current mirrors are grounded and the claim appears to mean the same ground. However, the disclosure discloses that there are different grounds (ground and VSSH, see the drawings in Figures 12-13), so it is not clear if applicant means the same ground or different ground. Further, the recitation “and a second for receiving the power supply voltage” on line 5 is indefinite because it is not clear what applicant means by “a second” (i.e., a second of what?). Clarification and/or appropriate correction is required. Claims 2-8 are indefinite because it depends on claim 1. Also, in claims 2-6, the recitations “semiconductor tube” throughout the claims are indefinite for the similar reason, and it is suggested to change “semiconductor tube” to “semiconductor transistor”. Clarification and/or appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lam (US 2024/0223190). For claim 1, Figure 2 of Lam teaches a level shift circuit, comprising: a first high-voltage switch tube (208), having a controlled end (118) for receiving a setting signal (Vset), a first end (source) for grounding (VSSL), and a second end (drain) for receiving a power supply voltage (VDDH); a second high-voltage switch tube (210), having a controlled end (120) for receiving a reset signal (Vreset), a first end (source) for grounding (VSSL), and a second end (drain) for receiving the power supply voltage (VDDH); a cross-coupling module (216, 218, 220, 222, 224, 226, 228, 230), comprising a first current mirror (216, 218, 224, 226) and a second current mirror (220, 222, 228, 230), wherein a first end (drain of 216) of the first current mirror (216, 218, 224, 226) is configured to obtain a first current (ISET’ 266) when the first high-voltage switch tube (208) is turned on, and a second end (ground end) of the first current mirror (216, 218, 224, 226) is grounded (VSSL); and a first end (drain of 220) of the second current mirror (220, 222, 228, 230) is configured to obtain a second current (IRESET’ 268) when the second high-voltage switch tube (210) is turned on, and a second end (ground end) of the second current mirror (220, 222, 228, 230) is grounded (VSSL), wherein the first current (266) is greater than or equal to N times the second current (268), and N is a positive integer; and a conversion module (232, 234, 108, 110), having a first end (gate of 234) connected to the first end (drain of 216) of the first current mirror (216, 218, 224, 226) through a first node (drain of 216), a second end (gate of 232) connected to the first end (drain of 220) of the second current mirror (220, 222, 228, 230) through a second node (drain of 220), a third end (238) respectively connected to a third end (238) of the first current mirror (216, 218, 224, 226) and the second node (via 232), a fourth end (236) respectively connected to a third end (236) of the second current mirror (220, 222, 228, 230) and the first node (via 234), and a fifth end (248) configured to output an output signal (SIG_OUT). For claim 2, Figure 2 of Lam teaches wherein the first current mirror (216, 218, 224, 226) comprises a first N-type metal-oxide-semiconductor tube (224) and a second N-type metal-oxide-semiconductor tube (226), wherein a drain of the first N-type metal-oxide-semiconductor tube (224) is configured to obtain the first current (ISET’ 266 via 216-218), a drain of the second N-type metal-oxide-semiconductor tube (226) is configured to obtain a third current (NISET’), and a width-to-length ratio of the second N-type metal-oxide-semiconductor tube (226) is greater than a width-to-length ratio of the first N-type metal-oxide-semiconductor tube (224); and the second current mirror (220, 222, 228, 230) comprises a third N-type metal-oxide-semiconductor tube (228) and a fourth N-type metal-oxide-semiconductor tube (230), a drain of the third N-type metal-oxide-semiconductor tube (228) is configured to obtain the second current (IRESET’ 268 via 220-222), a drain of the fourth N-type metal-oxide-semiconductor tube (236) is configured to obtain a fourth current (NIRESET’), and a width-to-length ratio of the fourth N-type metal-oxide-semiconductor tube (230) is greater than a width-to-length ratio of the third N-type metal-oxide-semiconductor tube (228), wherein the first current (ISET’ 266) is greater than or equal to the fourth current (IRESET’ 268). Allowable Subject Matter Claims 3-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2842
Read full office action

Prosecution Timeline

Oct 08, 2024
Application Filed
Feb 21, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Mar 31, 2026
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DISTRIBUTED FEEDBACK IN SCALE UP SIGNAL PATHS
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2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.5%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 921 resolved cases by this examiner. Grant probability derived from career allow rate.

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