DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to amendments filed 23 January 2026.
Claims 1 and 4 – 22 are pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show, in Fig. 2B, process 200 providing data to host in block 280 as described in ¶[67] of the specification. Rather block 280 discloses writing data from host. Examiner suggests amending block 280 to recite “Perform a read operation to obtain the host data”.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 – 7, 10 – 11 and 15 – 22 are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “based on the data type information, determining whether the data type is i) a first data type associated with single-level cell data storage or ii) a second data type associated with triple-level cell data storage or quad-level cell data storage”. This is to clarify what (determining or first data type) is associated with second data type (see spec Fig. 2A).
Claim 10 should be amended to “store, based on the first logical block addresses, the first data in a first portion, of the memory device, dedicated to data of the first data type
Claim 11 should be amended to “store, based on the second logical block addresses, the second data in a second portion, of the memory device, dedicated to data of the second data type
Claim 15 should be amended to “select a sector size of a sector of [[a]] the memory device based on determining whether the data is associated with the single-level cell data storage”. This is so that subsequent “the memory device” is not unclear whether it is referring to the one here or the one in the beginning of claim 15.
Claim 19 should be amended to “select the first value as the sector size based on i) determining that the data is not associated with single-level cell data storage and ii) determining that the data is to be stored using the sequential write operation”. This is to clarify what (selection of first value or determination of non-association with SLC) is associated with sequential storing of data (see spec Fig. 2A-2B and corresponding paragraphs).
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8 – 11, 14 – 16, 18 and 20 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Meiri (US 20210240628) in view of Saxena (US 20200401334).
Regarding claim 1, Meiri teaches
A method comprising:
determining data type information regarding a data type to be written to a memory device (memory device = Fig. 1 non-volatile data storage devices 118);
based on the data type information, determining whether the data type is a first data type [associated with single-level cell data storage] or a second data type [associated with triple-level cell data storage or quad-level cell data storage]; (Meiri teaches monitoring (determine) types (data type information, data type) of host I/O requests (which store (written) host data (data) to non-volatile data storage devices (see ¶[3])) wherein said types are either sequential (first data type) or random (second data type) (see ¶[54]).) (It is noted that, in the interest of compact prosecution, second data type is mapped. However, due to use of “or”, mapping to this second data type is not necessary.)
based on determining that the data type is the first data type, selecting a first value as the sector size;
based on determining that the data type is the second data type and that the second data type is to be written to the memory device using a sequential write operation, selecting the first value as the sector size; (claim interpretation: This limitation is recited in contingent manner and thus is not performed when its condition is not met (see MPEP 2111.04(II)). It is noted that use of “based on” merely specifies a step to be taken as a result of said condition but does not require said condition to occur. In this instance, data type is either first type or second type but not both. Therefore, for said data type that is first type, said data type is not second type (unmet condition) and therefore, this limitation is not performed.)
based on determining that the data type is the second data type and that the second data type is to be written to the memory device using a random write operation, selecting a second value as the sector size, (claim interpretation: This limitation is recited in contingent manner and thus is not performed when its condition is not met (see MPEP 2111.04(II)). It is noted that use of “based on” merely specifies a step to be taken as a result of said condition but does not require said condition to occur. In this instance, data type is either first type or second type but not both. Therefore, for said data type that is first type, said data type is not second type (unmet condition) and therefore, this limitation is not performed.)
wherein the first value exceeds the second value (claim interpretation: This limitation is not performed because it depends upon a contingent limitation that is not performed (see MPEP 2111.04(II)). In this instance, this limitation depends on setting of second value which is not performed (see previous claim interpretation). Therefore, there is no second value for which first value is to exceed.)
selecting, based on the data type information, the sector size for the memory device, (Meiri teaches calculating (selecting) optimal page size (sector size) based on said types (data type information) of said host I/O requests (see ¶[54]) wherein i) when said types are sequential (first data type), said optimal page size is 32KB (first value) and ii) when said types are random (second data type), said optimal page size is 8KB (second value) (see ¶[54-56]). Note that 32 KB (first value) is larger than (exceeds) 8KB (second value). Meiri also teaches said optimal page size (sector size) corresponds to size of physical pages of said non-volatile data storage devices (memory device) (see ¶[59]).)
generating a logical to physical (L2P) data structure based on the sector size; and (Meiri teaches changing (generating) indication of size, in mapping tree (L2P data structure), from default page size to said optimal page size (see ¶[63]) wherein said mapping tree maps LBAs (logical) to corresponding physical pages (physical) in said non-volatile data storage devices (see Fig. 2, ¶[50]). Note said changing is subsequent to (based on) determination to change said default page size to said optimal page size (sector size) (see Fig. 4/5 and corresponding paragraphs).)
storing the L2P data structure in a memory of a controller of the memory device (Meiri teaches said mapping tree (L2P data structure) is located (storing) in memory 130 (memory) of storage processor (controller) that is associated with (of) said non-volatile data storage devices 118 (memory device) (see Fig. 1, ¶[37]).)
As noted in claim 1, Meiri teaches two types (data type information) of host I/O requests that writes host data (data) to non-volatile data storage devices, sequential (first data type) and random (second data type) but does not appear to explicitly teach associating of said sequential and said random in the following manner.
a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage
However, Saxena teaches
a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage (Saxena teaches i) writing data to sequential addresses (first data type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (second data type) of MLC memory cells (triple/quad-level cell data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data (triple) per memory cell or four bits of data (quad) per memory cell (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) host I/O requests that are sequential (first data type), write host data (data) to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (second data type), write host data (data) to MLC memory cells (single-level cell data storage) that is 3/4-bits per memory cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 6, Meiri in view of Saxena teach the method of claim 1 and first data type associated with single-level cell data storage where Meiri also teaches
receiving information regarding the first data type associated with single-level cell data storage; and (Meiri teaches host I/O requests (which store host data (data) to non-volatile data storage devices (see ¶[3])) are mostly sequential (information regarding the first data type) (see ¶[56]) wherein said host I/O requests are conveyed (receiving) from host (see Fig. 1, ¶[39]). Note that, in claim 1, Meiri has been modified such that host I/O requests that are sequential (first data type), writes (associated) said host data (data) to SLC memory cells (single-level cell data storage).)
receiving a request to store data of an operating system (Meiri teaches logical storage volume may store (store) host data (data) generated by (receiving) application that generated host I/O requests (request) (see ¶[44]) wherein said application is embodied as firmware (operating system) (see ¶[115]).)
Regarding claim 8, Meiri teaches
A system (system = Fig. 1 data storage system 116) comprising:
a controller (controller = Fig. 1 storage processor 120) to: (Meiri teaches storage processor 120, in data storage system 116 (see ¶[36]), include processing circuity 124 that performs disclosed method/function (see Fig. 1, ¶[42]).)
receive, from an operating system, a request to store first data,
receive, from the operating system, first data type information regarding a first data type, [wherein the first data type is associated with single-level cell data storage]; (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (first data) (see ¶[44]) wherein i) said host I/O requests are mostly sequential (first data type information, first data type) (see ¶[56]) and ii) said applications are embodied using firmware (operating system) (see ¶[115]).)
select, based on the first data type information, a first sector size of a first sector of a memory device; (Meiri teaches in a case (based on) where said host I/O requests are mostly sequential (first data type information), for logical storage volume 1, calculate (select) optimal page size (first sector) of 32KB (first sector size) (see ¶[54], [56]).)
generate, for the first data, first logical block addresses, of a logical to physical (L2P) data structure, based on the first sector size; (claim interpretation: “for the first data” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation. In addition, “for the first data” is redundant because it would be met by next limitation reciting storage of first data based on first logical block address.) (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB, for said logical storage volume 1, repeating storing (generate) pointer (first logical block addresses) in virtual (logical) block (see Fig. 4, ¶[76], [81-82], [84]) of mapping tree (L2P data structure) (see ¶[49-50]) that maps LBAs (logical) to physical pages (physical) in non-volatile data storage devices (see ¶[47]).)
store the first data based on the first logical block addresses; (Meiri teaches repeating combining host data (first data) into (store) single page that is indicated by (based on) pointer (first logical block addresses) in virtual (logical) block (see Fig. 4, ¶[82], [84]).)
receive, from the operating system, a request to store second data;
receive, from the operating system, second data type information regarding a second data type, [wherein the second data type is associated with triple-level cell data storage or quad-level cell data storage] (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (second data) (see ¶[44]) wherein i) said host I/O requests are mostly random (second data type information, second data type) (see ¶[56]) and ii) said applications are embodied using firmware (operating system) (see ¶[115]).)
wherein the first sector size is for the second data type for a sequential write operation, (claim interpretation: “for the second data type” and “for a sequential write operation” are intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation.)
wherein a second sector size, of a second sector, is for the second data type for a random write operation, and (claim interpretation: “for the second data type” and “for a random write operation” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation.) (In the interest of compact prosecution, the mapping below maps to this limitation as well.)
wherein the first sector size exceeds the second sector size;
select, based on the second data type information, [the first sector size] or the second sector size; (Meiri teaches in a case (based on) where said host I/O requests are mostly random (second data type information, second data type information for a random write operation), for logical storage volume 2 (see ¶[64]), calculate (select) optimal page size (second sector) of 8KB (second sector size) (see ¶[54], [56]). Note that 32KB (first sector size) is larger (exceeds) than 8KB (second sector size).)
generate, for the second data, second logical block addresses, of the L2P data structure, based on [the first sector size] or the second sector size; and (claim interpretation: “for the second data” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation. Also, “for the second data” is redundant because it would be met by next limitation reciting storage of second data based on second logical block address.) (Meiri teaches upon (based on) determination to change page size to said optimal page size of 8KB, for said logical storage volume 2, repeating storing (generate) pointer (second logical block addresses) in virtual (logical) block (see Fig. 4, ¶[76], [81-82], [84]) of mapping tree (L2P data structure) (see ¶[49-50]) that maps LBAs (logical) to physical pages (physical) in non-volatile data storage devices (see ¶[47]).)
store the second data based on the second logical block addresses (Meiri teaches repeating combining host data (second data) into (store) single page that is indicated by (based on) pointer (second logical block addresses) in virtual (logical) block (see Fig. 4, ¶[82], [84]).)
As noted in claim 8, Meiri teaches host I/O requests that are i) sequential (first data type) and ii) random (second data type) but does not appear to explicitly teach associating said sequential and said random in the following manner.
wherein the first data type is associated with single-level cell data storage
wherein the second data type is associated with triple-level cell data storage or quad-level cell data storage
However, Saxena teaches
wherein [the] first data type is associated with single-level cell data storage
wherein [the] second data type is associated with triple-level cell data storage or quad-level cell data storage (Saxena teaches i) writing data to sequential addresses (first data type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (second data type) of MLC memory cells (triple/quad-level cell data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data (triple) per memory cell or four bits of data (quad) per memory cell (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) host I/O requests that are sequential (first data type), write data to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (second data type), write data to MLC memory cells (triple/quad-level cell data storage) that is 3/4-bits per memory cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 9, Meiri in view of Saxena teach the system of claim 8 where Meiri also teaches
store the L2P data structure in a memory of the controller of the memory device (Meiri teaches mapping tree (L2P data structure) is located (store) in memory 130 (memory) of storage processor (controller) (see Fig. 1) in data storage system 116 (memory device) (see ¶[36]).)
Regarding claim 10, Meiri in view of Saxena teach the system of claim 8 where Meiri also teaches
store the first data in a first portion, of the memory device, [dedicated to data of the first data type] based on the first logical block addresses (claim objection: This limitation should read “store, based on the first logical block addresses, the first data in a first portion, of the memory device, dedicated to data of the first data type”.) (Meiri teaches repeating combining host data (first data) into (store) single page (first portion) that is indicated by (based on) pointer (first logical block addresses) in virtual (logical) block (see Fig. 4, ¶[82], [84]) wherein i) said host data corresponds to host I/O requests (see ¶[44]) that is mostly sequential (first data type) to said logical storage volume 1 (see ¶[56]) and ii) said single page is located in non-volatile data storage devices 118 (see ¶[37]) of data storage system 116 (memory device) (see ¶[36]).)
Saxena teaches
a first portion, of [the] memory device, dedicated to data of [the] first data type (Saxena teaches creating SLC memory cells (first portion) to store (dedicated) data (data) written to sequential (first data type) addresses (see ¶[52]).)
In view of Saxena, modified Meiri is further modified such that said single page (first portion), storing first data of host I/O requests that are sequential (first data type), is SLC memory cells that is created to store sequential (first data type) data (data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 11, Meiri in view of Saxena teach the system of claim 10 where Meiri also teaches
store the second data in a second portion, of the memory device, [dedicated to data of the second data type] based on the second logical block addresses (claim objection: This limitation should read “store, based on the second logical block addresses, the second data in a first portion, of the memory device, dedicated to data of the second data type”.) (Meiri teaches repeating combining host data (second data) into (store) single page (second portion) that is indicated by (based on) pointer (second logical block addresses) in virtual (logical) block (see Fig. 4, ¶[82], [84]) wherein i) said host data corresponds to host I/O requests (see ¶[44]) that is mostly random (second data type) to said logical storage volume 2 (see ¶[55], [[64]) and ii) said single page is located in non-volatile data storage devices 118 (see ¶[37]) of data storage system 116 (memory device) (see ¶[36]).)
Saxena teaches
a second portion, of [the] memory device, dedicated to data of [the] second data type (Saxena teaches creating MLC memory cells (second portion) to store (dedicated) data (data) written to random (second data type) addresses (see ¶[52]).)
In view of Saxena, modified Meiri is further modified such that said single page (second portion), storing second data of host I/O requests that are random (second data type), is MLC memory cells that is created to store random (second data type) data (data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 14, Meiri in view of Saxena teach the system of claim 8 where Meiri also teaches
the first data includes [firmware metadata or] data of the operating system (Meiri teaches host data (first data) corresponds to (of) applications (see ¶[44]) that are embodied using firmware (operating system) (see ¶[115]).)
Regarding claim 15, Meiri teaches
A memory device (memory device = Fig. 1 data storage system 116) comprising:
one or more storage media (one or more storage media = Fig. 1 non-volatile data storage devices 118);
a controller (controller = Fig. 1 storage processor 120) configured to: (Meiri teaches storage processor 120, in data storage system 116 (see ¶[36]), include processing circuity 124 that performs disclosed method/function (see Fig. 1, ¶[42]).)
receive, from an operating system of a host computing device, a request to store data on the memory device, wherein the memory device is associated with different values for a sector size; (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (data) (see ¶[44]) wherein i) said applications are embodied using firmware (operating system) (see ¶[115]) and ii) said applications execute on host computers (host computing device) (see ¶[36]).) (It is noted that i) “store data on the memory device” is taught by mapping in subsequent limitation “store the data on the one or more storage media based on the logical block addresses, and ii) “memory device associated with different values for a sector size” is taught by mapping in subsequent limitations “select a sector size of a sector size of a memory device based on determining whether the data is associated with the single-level cell data storage”, “wherein the sector size, for the single level cell data storage, is a first value”, “wherein the sector size, for a random write operation, on the different data storage, is a second value” and “wherein the second value is different than the first value”.)
determine whether the data is associated with first type [the single-level cell data storage];
select a sector size of a sector of a memory device based on determining whether the data is associated with the first type [single-level cell data storage],
wherein the sector size, for the first type [single-level cell data storage], is a first value, (claim interpretation: “for the single-level cell data storage” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation.)
wherein the sector size, for a sequential write operation on a second type [a different data storage], is the first value, and (claim interpretation: “for a sequential write operation on a different data storage” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation.)
wherein the sector size, for a random write operation on the second type [different data storage], is a second value, and (claim interpretation: “for a random write operation on a different data storage” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation.) (In the interest of compact prosecution, the mapping below maps to this limitation as well.)
wherein the second value is different than the first value (Meiri teaches calculating optimal page size (sector size) based on types of said host I/O requests (see ¶[54]) that corresponds to said host data (data) (see ¶[44]) wherein i) when said host I/O requests are mostly sequential (first type), said optimal page size is 32KB (first value) (see ¶[56]) and ii) when said host I/O requests are mostly random (second type), said optimal page size is 8KB (second value) (see ¶[55]). Note that 32KB (first value) is different than 8KB (second value).)
generate logical block addresses, of a logical to physical (L2P) data structure, based on the sector size; and (Meiri teaches upon (based on) determination to change page size to said optimal page size, repeating storing (generate) pointer (second logical block addresses) in virtual (logical) block (see Fig. 4, ¶[76], [81-82], [84]) of mapping tree (L2P data structure) (see ¶[49-50]) that maps LBAs (logical) to physical pages (physical) in non-volatile data storage devices (see ¶[47]).)
store the data on the one or more storage media based on the logical block addresses (Meiri teaches repeating combining host data (data) into (store) single page that is indicated by (based on) pointer (logical block addresses) in virtual (logical) block wherein said single page is in physical block (see Fig. 4, ¶[82], [84]) that is in non-volatile data storage devices 118 (the one or more storage media) (see ¶[50]).)
As noted in claim 15, Meiri teaches host I/O requests that are i) sequential (first type) with 32KB (first value) and ii) random (second type) with 8KB (second value) but does not appear to explicitly teach said sequential (with 32KB) is associated with SLC and said random (with 8KB) is associated with different data storage.
However, Saxena teaches i) writing data to sequential addresses (first type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (second type) of MLC memory cells (different data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data per memory cell or four bits of data per memory cells (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) said host I/O requests that are sequential (first type) (with 32KB (first value)), write data to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (second type) (with 8KB (second value)), write data to MLC memory cells (different data storage) that is 3/4-bits per cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 16, Meiri in view of Saxena teach the memory device of claim 15 where Meiri also teaches
determine that the data is associated with single-level cell data storage; and
select the first value as the sector size based on determining that the data is associated with single-level cell data storage (Meiri teaches in case (based on) host I/O requests (with corresponding host data (data) (see ¶[44])) that are (determine) mostly sequential, said optimal page size (sector size) is 32KB (first value) (see ¶[56]). Note that Meiri has been modified in claim 15 such that said host I/O requests that are sequential, stores said host data (data) to SLC (single-level cell data storage).)
Regarding claim 18, Meiri in view of Saxena teach the memory device of claim 16 where Meiri also teaches
wherein the data includes firmware metadata or data of the operating system (see mapping in claim 14 supra)
Regarding claim 20, Meiri in view of Saxena teach the memory device of claim 15 where Meiri also teaches
wherein the controller is configured to select the second value when the data is associated with triple-level cell data storage or quad-level cell data storage and when the data is to be stored using the random write operation (Meiri teaches in case (based on) host I/O requests (with corresponding host data (data) (see ¶[44])) that are (determine) mostly random (random write operation), said optimal page size (sector size) is 8KB (second value) (see ¶[55]). Note that Meiri has been modified in claim 15 such that said host I/O requests that are random, stores said host data (data) to MLC (triple/quad-level cell data storage) that stores 3/4-bits (triple/quad-level) per memory cell.)
Regarding claim 21, Meiri in view of Saxena teach the memory device of claim 15 where modified Meiri also teaches
wherein the data is associated with the single-level cell data storage, and (In claim 15, Meiri has been modified such that host I/O requests that are sequential, stores said host data (data) to (associated) SLC (single-level cell data storage) (see claim 15).)
wherein the data includes data of an operating system (Meiri teaches host data (first data) corresponds to (of) applications (see ¶[44]) that are embodied using firmware (operating system) (see ¶[115]).)
Regarding claim 15, Meiri in view of Saxena teach the memory device of claim 15 where modified Meiri also teaches
wherein the different data storage includes triple-level cell data storage or quad-level cell data storage (In claim 15, Meiri has been modified such that host I/O requests that are random, stores said host data (data) to MLC (triple/quad-level cell data storage) that stores 3/4-bits (triple/quad-level) per memory cell.)
Claims 4 – 5, 12 – 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena, and further in view of Yurzola (US 20110154158).
Regarding claim 4, Meiri in view of Saxena teach the method of claim 1 where Meiri also teaches
encoding data[, using an error correction code (ECC) component,] to obtain encoded data,
wherein a size of the data is based on the sector size, and
wherein the data is received from a host computing device; and
storing, based on the L2P data structure, the encoded data in a location of the memory device (Meiri teaches using (based on) mapping tree (L2P data structure) to identify N pages that are combined into (storing) a single page (location) of optimal page size wherein i) host data (data), from said N pages, are compressed (encoding) into said single page (see Fig. 4, ¶[78-82]) and ii) said single page is in non-volatile data storage devices (memory device) (see ¶[37]). Note that i) compression of said host data (data) results in compressed host data (encoded data) that is stored in said single page and ii) said N (size) pages (with (of) said host data (data)) is selected in accordance with (based on) said single page of said optimal page size (sector size). Meiri also teaches said host data is generated by (received from) application (see ¶[44]) that is executing on host computer (host computing device) (see ¶[36]).)
As noted in claim 4, modified Meiri teaches compressing host data (data) into compressed host data (encoded data) but does not appear to explicitly teach said compressing is done by ECC component.
However, Yurzola teaches ECC enhancement compression module (ECC component) is used to compress (encode) control data (data) into compressed control data (encoded data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (data) is compressed (encoded), using ECC enhancement compression module (ECC module), into compressed host data (encoded data).
Meiri, Saxena and Yurzola are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Regarding claim 5, Meiri in view of Saxena and Yurzola teach the method of claim 4 where Meiri also teaches
wherein the size of the data is the first value when the sector size is the first value, and (Meiri teaches combining N (size) pages (with (of) host data (data)) that are combined into a single page of optimal page size (sector size) (see ¶[82]) wherein when host I/O requests types are sequential, said optimal page size is 32KB (first value). Note that said N (size) pages is the same as said one single page of said optimal page size of 32KB (first value).)
wherein the size of the data is the second value when the sector size is the second value (claim interpretation: This limitation is recited in a contingent manner (via use of “when”) and thus is not performed when its condition is not met (see MPEP 2111.04(II)). In this instance, sector size of second value is not met because it is not performed in claim 1 (see claim interpretation in claim 1). Therefore, this limitation is not performed.)
Regarding claim 12, Meiri in view of Saxena teach the system of claim 8 where Meiri also teaches
encoding a portion of the first data[, using an error correction code (ECC) component,] to obtain encoded first data,
wherein a size of the portion of the first data is based on the first sector size; and
storing the encoded first data in a first location of the memory device (Meiri teaches optimal page size is 32KB (first sector size) for host I/O requests that are mostly sequential (see ¶[56]). Meiri also teaches N pages that are combined into (storing) a single page (first location) of said optimal page size wherein i) host data (portion of the first data), from said N pages, are compressed (encoding) into said single page (see Fig. 4, ¶[78-82]) and ii) said single page is in non-volatile data storage devices (see ¶[37]) of data storage system 116 (memory device) (see ¶[36]). Note that i) compression of said host data (portion of the first data) results in compressed host data (encoded first data) that is stored in said single page and ii) said N (size) pages (with (of) said host data (portion of the first data)) is selected in accordance with (based on) said single page of said optimal page size (first sector size).)
As noted in claim 12, modified Meiri teaches compressing host data (portion of the first data) into compressed host data (encoded first data) but does not appear to explicitly teach said compressing is done by ECC component.
However, Yurzola teaches ECC enhancement compression module (ECC component) is used to compress (encode) control data (portion of first data) into compressed control data (encoded first data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (portion of the first data) is compressed (encoded), using ECC enhancement compression module (ECC module), into compressed host data (encoded first data).
Meiri, Saxena and Yurzola are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Regarding claim 13, Meiri in view of Saxena and Yurzola teach the system of claim 12 where Meiri also teaches
encoding a portion of the second data[, using an error correction code ECC) component,] to obtain encoded second data,
wherein a size of the portion of the second data is based on the second sector size; and
storing the encoded second data in a second location of the memory device (Meiri teaches optimal page size is 8KB (second sector size) for host I/O requests that are mostly random (see ¶[56]). Meiri also teaches N pages that are combined into (storing) a single page (second location) of said optimal page size wherein i) host data (portion of the second data), from said N pages, are compressed (encoding) into said single page (see Fig. 4, ¶[78-82]) and ii) said single page is in non-volatile data storage devices (see ¶[37]) of data storage system 116 (memory device) (see ¶[36]). Note that i) compression of said host data (portion of the second data) results in compressed host data (encoded second data) that is stored in said single page and ii) said N (size) pages (with (of) said host data (portion of the second data)) is selected in accordance with (based on) said single page of said optimal page size (second sector size).)
As noted in claim 13, modified Meiri teaches compressing host data (portion of the second data) into compressed host data (encoded second data).
Yurzola teaches ECC enhancement compression module (ECC component) is used to compress (encode) control data (portion of second data) into compressed control data (encoded second data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (portion of the second data) is compressed (encoded), using ECC enhancement compression module (ECC module), into compressed host data (encoded second data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Regarding claim 17, Meiri in view of Saxena and Yurzola teach claim 17 (see claim 4 mapping). Note that claim 4 recites similar limitations as claim 17.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena, and further in view of Koo (US 20220156007).
Regarding claim 7, Meiri in view of Saxena teach the method of claim 1 where Meiri also teaches
receiving information regarding the first data type associated with single-level cell data storage (Meiri teaches host I/O requests (which store host data (data) to non-volatile data storage devices (see ¶[3])) are mostly sequential (information regarding first data type) (see ¶[56]) wherein said host I/O requests are conveyed (receiving) from host (see Fig. 1, ¶[39]). Note that, in claim 1, Meiri has been modified such that said host I/O requests that are sequential (first data type), write (associated) said host data (data) to SLC memory cells (single-level cell data storage).)
As noted in claim 7, modified Meiri teaches the method of claim 1 but does not appear to explicitly teach
receiving a request to store firmware metadata
However, Koo teaches
receiving a request to store firmware metadata (Koo teaches receiving, from host, ADMIN command (request) that is write (store) command for metadata (metadata) of firmware (firmware) where said ADMIN command is distributed to plurality of cores (see Fig. 2, ¶[50], [52], [54]).)
In view of Koo, modified Meiri is further modified such that ADMIN command (request) (which is write (store) command for metadata of firmware) is received (receiving) from host.
Meiri, Saxena, Koo are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner described supra because distribution of commands results in efficient utilization of cores (Koo, ¶[57]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena, and further in view of Chatterjee (US 8108580).
Regarding claim 19, Meiri in view of Saxena teach the memory device of claim 15 where Meiri also teaches
determine that the data is not associated with single-level cell data storage; and
select the [first] second value as the sector size based on determining that the data is not associated with single-level cell data storage [and determining that the data is to be stored using the sequential write operation] (Meiri teaches in case (based on) host I/O requests (with corresponding host data (data) (see ¶[44])) that are (determine) mostly random, said optimal page size (sector size) is 8KB (second value) (see ¶[56]). Note that Meiri has been modified in claim 15 such that said host I/O requests that are random, stores said host data (data) to MLC (not associated with single-level cell data storage).)
As noted in claim 19, modified Meiri teaches selecting 8KB (second value as sector size) based on determining that data is random writes to MLC (not associated with single-level cell data storage) but does not appear to explicitly teach selecting 32KB (first value as sector size) based on determining that the data is to be stored using sequential write operation.
However, Chatterjee teaches serializing random access data writes into sequential data writes (sequential write operation) (see col 6 ln 47-51).
In view of Chatterjee, modified Meiri is further modified such that said random writes of said data to said MLC (not associated with single-level cell data storage) is serialized into sequential data writes (determining that the data is to be stored using the sequential write operation). Modified Meiri already teaches in claim 15 that sequential host I/O requests use optimal page size (sector size) of 32KB (first value). As such, said random writes, having been serialized into sequential data writes (sequential write operation), would use said optimal page size of 32KB (first value).
Meiri, Saxena and Chatterjee are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modifed Meiri in the manner described supra because serializing random writes into sequential writes improve completion time (and reduce bottleneck) at storage (Chatterjee, col 6 ln 47-51).
Response to Remarks
Applicant’s remarks, with respect to objections, have are persuasive (with the exception of objections to claims 10 – 11). Therefore, said objections (with the exception of said objections to claims 10 – 11) are withdrawn. It is noted that Applicant appears to have missed addressing said objections to claims 10 – 11.
Applicant’s remarks, with respect to prior art rejections, have been considered but are not persuasive. It is noted that due to i) contingent limitations in claim 1 and ii) intended use in claims 8 and 15, features, recited by Applicant that overcome prior art of record, do not limit the claims. Therefore, claims 1, 8 and 15 are taught by prior art of record as noted supra.
Additional Remarks
In the interest of compact prosecution, it is noted that even if Applicant amends claims 1, 8 and 15, to avoid reciting said claims as contingent limitation or intended use, said claims would be taught by newly identified prior art Chatterjee. Specifically, Meiri in view of Saxena teach i) random I/O operations (random write operation) (to TLC/MLC) using optimal page size (sector size) of 8KB (second value), and ii) sequential I/O operations (sequential write operation) (to SLC) using optimal page size (sector size) of 32KB (first value) (see claims 1, 8 and 15) where Chatterjee teaches serializing said random I/O operations into said sequential I/O operations (see Chatterjee mapping in claim 19 supra). Since said random I/O operations (random write operation) has been serialized into said sequential I/O operations, optimal page size (sector size) would now be 32KB (first value).
It is further noted, to avoid reciting method claims 1 – 7 in a contingent manner, said claims would need to recite conditions as true/occurring. It is noted that reciting a limitation as “based on” would not be sufficient because “based on” merely recites an action that is performed as a result to a condition. There is no recitation of said condition occurring (or being true), and thus “based on” would not be sufficient. It is further noted that due to data type information being either first type or second type (but not both), contingent limitations would inherently occur. In order to avoid said contingent limitations, said first and second types would each need to be associated with its own data (and not the same one).
The prior art made of record and not relied upon is considered pertinent to Applicant's invention.
Kanno (US 20210042033) teaches i) when write data (data type information) is metadata (first data type), writing said write data to SLC (single-level cell), and ii) when said write data (data type information) is user data (second data type), writing said write data to MLC/TLC/QLC (triple-level/quad-level cell data storage) (see Kanno ¶[76], [78]). This appears relevant to claims 1, 8 and 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHIE YEW/ Primary Examiner, Art Unit 2139
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