DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to RCE filed 02 July 2026.
Claims 1, 4 – 6, 8 – 15, 17 – 21 and 23 – 25 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02 July 2026 has been entered.
Claim Objections
Claims 1, 4 – 6, 10 – 11 and 23 are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “the first entry comprising a first number of bytes corresponding to physical address[[es]] of the first sector, the second entry comprising a second number of bytes corresponding to physical address[[es]] of the second sector”. This is a typo as the instant specification is clear that 4 bytes map to singular physical address (not plural physical addresses) (see spec ¶[27-28]). There is also no support for 4 bytes being mapped to plural physical addresses.
Claim 10 should be amended to “storing, based on the first logical block addresses, the first data [[in]] in the first sector of the memory device”. This is a typo.
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8 – 15, 17 – 21 and 24 – 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 8, “generate, for the first data, a first entry of first logical block addresses and first physical block addresses, of a logical to physical (L2P) data structure, based on the first sector size” and “generate, for the second data, a second entry of second logical block addresses and second physical block addresses, of the L2P data structure, based on the second sector size” lack written support and introduces new matter. As recited, the limitations recite L2P with entries, each mapping plural logical block addresses to plural physical block addresses. The instant specification does not appear to disclose single L2P entry mapping plural logical addresses to plural physical addresses. Rather, the instant specification discloses single L2P entry mapping single logical address to single physical address (see spec ¶[27-28]). Therefore, the limitations in question lacks written support and introduces new matter.
Regarding claim 15, “generate a first entry of first logical block addresses and first physical block addresses associated with the first sector size value, of a logical to physical (L2P) data structure” and “generate a second entry of second logical block addresses and second physical block addresses associated with the second sector size value, of the L2P data structure” lack written support and introduces new matter. This is the same issue as claim 8.
Claims, dependent upon above identified claims, are also rejected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8 – 11, 14 – 15, 18 and 20 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Meiri (US 20210240628) in view of Saxena (US 20200401334) and Yamada (US 6088780).
Regarding claim 1, Meiri teaches
A method comprising:
receiving data to be written to a memory device (memory device = Fig. 1 non-volatile data storage devices 118);
determining first data type information regarding a data type of the data;
based on the first data type information, determining that the data is of a first data type [associated with single-level cell data storage];
based on determining that the data is of the first data type, selecting a first sector size value for the data;
receiving additional data to be written to the memory device;
determining second data type information regarding a data type of the additional data;
based on the second data type information, determining that the additional data is of a second data type [associated with triple-level cell data storage or quad-level cell data storage];
based on determining that the additional data is of the second data type, selecting a second sector size value for the additional data, wherein the first sector size value exceeds the second sector size value (Meiri teaches monitoring (determine) types (data type information, data type) of host I/O requests (which store (written) host data (data, additional data) to non-volatile data storage devices (see ¶[3])) wherein said types are either sequential (first data type) or random (second data type) (see ¶[54]). Meiri also teaches said host I/O requests are from (receiving) hosts 110 (see ¶[39]).) (Meiri teaches calculating (selecting) optimal page size (first sector size value, second sector size value) based on said types (data type information) of said host I/O requests (see ¶[54]) wherein i) when said types are sequential (first data type), said optimal page size is 32KB (first sector size value) and ii) when said types are random (second data type), said optimal page size is 8KB (second sector size value) (see ¶[54-56]). Note that 32 KB (first value) is larger than (exceeds) 8KB (second value).)
generating a logical to physical (L2P) data structure based on the first and second sector size values, the L2P data structure including a first entry for a first sector of the memory device associated with the first sector size value and a second entry for a second sector of the memory device associated with the second sector size value, the first entry comprising a first number of bytes corresponding to physical addresses of the first sector, the second entry comprising a second number of bytes corresponding to physical addresses of the second sector (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB (first sector size value), for said logical storage volume 1, repeating storing (generate), in virtual (logical) block (first entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (first number of bytes) pointing to single physical page (first sector) that stores combined host data (first data) (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (physical addresses of first sector) of said single physical page (see Fig. 2, ¶[65]).) (Meiri teaches upon (based on) determination to change page size to said optimal page size of 8KB (second sector size values), for said logical storage volume 2, repeating storing (generate), in virtual (logical) block (second entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (second number of bytes) pointing to single physical page (second sector) that stores combined host data (second data) (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (physical addresses of second sector) of said single physical page (see Fig. 2, ¶[65]).)
storing the L2P data structure in a memory of a controller of the memory device (Meiri teaches said mapping tree (L2P data structure) is located (storing) in memory 130 (memory) of storage processor (controller) that is associated with (of) said non-volatile data storage devices 118 (memory device) (see Fig. 1, ¶[37]).)
As noted in claim 1, Meiri teaches two types (data type information) of host I/O requests that writes host data (data) to non-volatile data storage devices, sequential (first data type) and random (second data type) but does not appear to explicitly teach associating of said sequential and said random in the following manner.
a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage
However, Saxena teaches
a first data type associated with single-level cell data storage or a second data type associated with triple-level cell data storage or quad-level cell data storage (Saxena teaches i) writing data to sequential addresses (first data type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (second data type) of MLC memory cells (triple/quad-level cell data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data (triple) per memory cell or four bits of data (quad) per memory cell (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) host I/O requests that are sequential (first data type), write host data (data) to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (second data type), write host data (data) to MLC memory cells (single-level cell data storage) that is 3/4-bits per memory cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
As noted in claim 1, modified Meiri teaches i) for an optimal page size of 32KB (first sector size value), first entry with pointer (first number of bytes) pointing to single physical page (first sector), and ii) for an optimal page size of 8KB (second sector size value), second entry with pointer (second number of bytes) pointing to single physical page (second sector), but does not appear to explicitly teach said first and second number of bytes are equal to each other.
However, Yamada teaches
the L2P data structure including a first entry for a first sector of the memory device associated with the first sector size value and a second entry for a second sector of the memory device associated with the second sector size value, the first entry comprising a first number of bytes corresponding to physical addresses of the first sector, the second entry comprising a second number of bytes corresponding to physical addresses of the second sector, the first number of bytes being equal to the second number of bytes (claim objection: This limitation should read “the first entry comprising a first number of bytes corresponding to physical address of the first sector, the second entry comprising a second number of bytes corresponding to physical address of the second sector”) (Yamada teaches i) first address (first number of bytes) of (comprising) a first entry (first entry), in page table 310 (L2P data structure), mapping to large (first sector size value) page (first sector) and ii) second virtual address (second number of bytes) of (comprising) a second entry (second entry), in said page table 310, mapping to small (second sector size value) page (second sector) (see Fig. 3A, col 6 ln 56 – col 7 ln 4) wherein said large page and said small page, each are mapped to physical addresses (physical addresses of first and second sectors) (see col 1 ln 29-32). Note that in Fig. 3A, same sized virtual address (first number of bytes being equal to second number of bytes) is used to map to both said lager page and said small page, where an exemplary size of said virtual address is 64-bit (number of bytes) but is not limited to 64-bit (see Fig. 4, col 8 ln 9-21).)
In view of Yamada, modified Meiri is further modified such that i) a first 64-bit virtual address (first number of bytes) of first entry, in said L2P data structure, maps to said first sector size (or large) of a page (first sector), and ii) a second 64-bit virtual address (second number of bytes) of a second entry, in said L2P data structure, maps to said second sector size (or small) of a page (second sector), wherein same 64-bit (number of bytes) is used to map to both said first sector size and said second sector size.
Meiri, Saxena and Yamada are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner described supra because Yamada’s mapping of same size virtual address to different page sizes would reduce number of entries in a page table by selecting a correct page size for said virtual address (Yamada, col 4 ln 34-41).
Regarding claim 6, Meiri in view of Saxena and Yamada teach the method of claim 1 and first data type associated with single-level cell data storage where Meiri also teaches
the receiving of the data including receiving a request to store data of an operating system [or a request to store firmware metadata] (Meiri teaches logical storage volume may store (the receiving, store) host data (the data, data) generated by (receiving) application that generated host I/O requests (request) (see ¶[44]) wherein said application is embodied as firmware (operating system) (see ¶[115]).)
Regarding claim 8, Meiri teaches
A system (system = Fig. 1 operational environment) comprising:
a storage device (storage device = Fig. 1 data storage system 116) including a memory device (memory device = Fig. 1 non-volatile data storage devices 118) and a controller (controller = Fig. 1 storage processor 120), the memory device including a plurality of sectors, the controller to: (Meiri teaches data storage system 116 includes non-volatile data storage devices 118 and storage processor 120 (see Fig. 1, ¶[36]) that include processing circuity 124 that performs disclosed method/function (¶[42]). Meiri also teaches physical pages (plurality of sectors) located in said non-volatile data storage devices 118 (see ¶[37]).)
receive, from an operating system, a request to store first data;
receive, from the operating system, first data type information regarding a first data type, [wherein the first data type is associated with single-level cell data storage]; (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (first data) (see ¶[44]) wherein i) said host I/O requests are mostly sequential (first data type information, first data type) (see ¶[56]) and ii) said applications are embodied using firmware (operating system) (see ¶[115]).)
select, based on the first data type information, a first sector size of a first sector of the plurality of sectors; (Meiri teaches in a case (based on) where said host I/O requests are mostly sequential (first data type information), for logical storage volume 1, calculate (select) optimal page size of 32KB (first sector size) (see ¶[54], [56]).)
generate, for the first data, a first entry of first logical block addresses and first physical addresses, of a logical to physical (L2P) data structure, based on the first sector size, [the first entry comprising a first number of bytes corresponding to the first physical block addresses]; (claim interpretation: “for the first data” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation. In addition, “for the first data” is redundant because it would be met by next limitation reciting storage of first data based on first logical block address.)
store the first data in the memory device based on the first logical block addresses; (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB, for said logical storage volume 1, repeating storing (generate), in virtual (logical) block (first entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (first logical block addresses) pointing to (based on) single physical page (first sector) that stores combined host data (first data) (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (first physical block addresses) of said single physical page (see Fig. 2, ¶[65]).)
receive, from the operating system, a request to store second data;
receive, from the operating system, second data type information regarding a second data type, [wherein the second data type is associated with triple-level cell data storage or quad-level cell data storage] (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (second data) (see ¶[44]) wherein i) said host I/O requests are mostly random (second data type information, second data type) (see ¶[56]) and ii) said applications are embodied using firmware (operating system) (see ¶[115]).)
select, based on the second data type information, a second sector size of a second sector of the plurality of sectors, the first sector size exceeding the second sector size; (Meiri teaches in a case (based on) where said host I/O requests are mostly random (second data type information, second data type information for a random write operation), for logical storage volume 2 (see ¶[64]), calculate (select) optimal page size of 8KB (second sector size) (see ¶[54], [56]). Note that 32KB (first sector size) is larger (exceeds) than 8KB (second sector size).)
generate, for the second data, a second entry of second logical block addresses and second physical block addresses, of the L2P data structure, based on the second sector size, [the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to the second number of bytes]; and (claim interpretation: “for the second data” is intended use of this limitation. Intended use merely recites a context in which this limitation operates, and thus does not further limit this limitation. Also, “for the second data” is redundant because it would be met by next limitation reciting storage of second data based on second logical block address.)
store the second data in the memory device based on the second logical block addresses (Meiri teaches upon (based on) determination to change page size to said optimal page size of 8KB, for said logical storage volume 2, repeating storing (generate), in virtual (logical) block (second entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (second logical block addresses) pointing to (based on) single physical page (second sector) that stores combined host data (second data) (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (second physical block addresses) of said single physical page (see Fig. 2, ¶[65]).)
As noted in claim 8, Meiri teaches host I/O requests that are i) sequential (first data type) and ii) random (second data type) but does not appear to explicitly teach associating said sequential and said random in the following manner.
wherein the first data type is associated with single-level cell data storage
wherein the second data type is associated with triple-level cell data storage or quad-level cell data storage
However, Saxena teaches
wherein [the] first data type is associated with single-level cell data storage
wherein [the] second data type is associated with triple-level cell data storage or quad-level cell data storage (Saxena teaches i) writing data to sequential addresses (first data type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (second data type) of MLC memory cells (triple/quad-level cell data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data (triple) per memory cell or four bits of data (quad) per memory cell (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) host I/O requests that are sequential (first data type), write data to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (second data type), write data to MLC memory cells (triple/quad-level cell data storage) that is 3/4-bits per memory cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
As noted in claim 8, modified Meiri teaches i) generating first entry of first logical block addresses and first physical block addresses and ii) generating second entry of second logical block addresses and second physical block addresses but does not appear to explicitly teach mapping to said first and second entries in the following manner.
the first entry comprising a first number of bytes corresponding to the first physical block addresses
the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to second number of bytes
However, Yamada teaches
the first entry comprising a first number of bytes corresponding to the first physical block addresses
the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to the second number of bytes (Yamada teaches i) first address (first number of bytes) of a first entry (first entry), in page table 310 (L2P data structure), mapping to large page and ii) second virtual address (second number of bytes) of a second entry (second entry), in said page table 310, mapping to small page (see Fig. 3A, col 6 ln 56 – col 7 ln 4) wherein said large page and said small page, each is mapped to physical addresses (first physical block addresses, second physical block addresses) (see col 1 ln 29-32). Note that in Fig. 3A, same sized virtual address (first number of bytes being equal to second number of bytes) is used to map to both said lager page and said small page, where an exemplary size of said virtual address is 64-bit (number of bytes) (see Fig. 4, col 8 ln 9-21).)
In view of Yamada, modified Meiri is further modified such that i) a first 64-bit virtual address (first number of bytes) of first entry, in said L2P data structure, maps to said first physical block addresses, and ii) a second 64-bit virtual address (second number of bytes) of a second entry, in said L2P data structure, maps to said second physical block addresses, wherein same 64-bit (number of bytes) is used to map to both said first and second physical block addresses.
Meiri, Saxena and Yamada are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner described supra because by mapping same size virtual address to different physical addresses of different page sizes, number of entries (in a page table) can be reduced by selecting a correct page size for said virtual address (Yamada, col 4 ln 34-41).
Regarding claim 9, Meiri in view of Saxena and Yamada teach the system of claim 8 where Meiri also teaches
the controller including a memory
store the L2P data structure in the memory (Meiri teaches mapping tree (L2P data structure) is located (store) in memory 130 (memory) of storage processor (controller) (see Fig. 1).)
Regarding claim 10, Meiri in view of Saxena and Yamada teach the system of claim 8 where Meiri also teaches
the storage of the first data including storing, based on the first logical block addresses, the first data in in the first sector of the memory device, [the first sector being dedicated to data of the first data type] (Meiri teaches repeating storing, in virtual block of mapping tree (see ¶[49-50]), pointer (first logical block addresses) pointing to (based on) single physical page (first sector) that stores combined host data (first data) (see Fig. 4, ¶[76], [82-84]) wherein said host data corresponds to host I/O requests (see ¶[44]) that is mostly sequential (first data type) (see ¶[56]).)
Saxena teaches
[the] first sector being dedicated to data of [the] first data type (Saxena teaches creating SLC memory cells (first portion) to store (dedicated) data (data) written to sequential (first data type) addresses (see ¶[52]).)
In view of Saxena, modified Meiri is further modified such that said single physical page (first sector), storing first data of host I/O requests that are sequential (first data type), is SLC memory cells that is created to store sequential (first data type) data (data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 11, Meiri in view of Saxena and Yamada teach the system of claim 10 where Meiri also teaches
the storage of the second data including storing, based on the second logical block addresses, the second data in the second sector, [the second sector being dedicated to data of the second data type] (Meiri teaches repeating storing, in virtual block of mapping tree (see ¶[49-50]), pointer (second logical block addresses) pointing to (based on) single physical page (second sector) that stores combined host data (second data) (see Fig. 4, ¶[76], [82-84]) wherein said host data corresponds to host I/O requests (see ¶[44]) that is mostly random (second data type) (see ¶[55], [64]).)
Saxena teaches
[the] second sector being dedicated to data of [the] second data type (Saxena teaches creating MLC memory cells (second sector) to store (dedicated) data (data) written to random (second data type) addresses (see ¶[52]).)
In view of Saxena, modified Meiri is further modified such that said single physical page (second sector), storing second data of host I/O requests that are random (second data type), is MLC memory cells that is created to store random (second data type) data (data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
Regarding claim 14, Meiri in view of Saxena and Yamada teach the system of claim 8 where Meiri also teaches
the first data includes [firmware metadata or] data of the operating system (Meiri teaches host data (first data) corresponds to (of) applications (see ¶[44]) that are embodied using firmware (operating system) (see ¶[115]).)
Regarding claim 15, Meiri teaches
A memory device (memory device = Fig. 1 data storage system 116) comprising:
a plurality of sectors associated with respective sector size values;
one or more computer readable storage media (one or more computer readable storage media = Fig. 1 non-volatile data storage devices 118);
a controller (controller = Fig. 1 storage processor 120) configured to: (Meiri teaches storage processor 120, in data storage system 116 (see ¶[36]), include processing circuity 124 that performs disclosed method/function (see Fig. 1, ¶[42]).)
receive, from an operating system of a host computing device, a request to store data on the memory device; (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (data) (see ¶[44]) wherein said applications are embodied using firmware (operating system) (see ¶[115]).)
determine that the data is associated with first type [the single-level cell data storage];
based on determination that the data is associated with the first type [single-level cell data storage], select a first sector size value of the respective sector size values, (Meiri teaches in a case (based on) where said host I/O requests are mostly sequential (first type), for logical storage volume 1, calculate (select) optimal page size of 32KB (first sector size value, respective sector size values) (see ¶[54], [56]).)
receive, from the operating system, a request to store additional data on the memory device; (Meiri teaches applications (operating system) conveying (receiving from) host I/O requests (request) (see ¶[39]) that store (store) host data (additional data) (see ¶[44]) wherein said applications are embodied using firmware (operating system) (see ¶[115]).)
determine that the additional data is not associated with the first type [single-level cell data storage];
based on the determination that the additional data is not associated with the first type [single-level cell data storage], select one of [i) the first sector size value] or ii) a second sector size value of the respective sector size values for the additional data, wherein the second sector size value is different than the first sector size value (Meiri teaches in a case (based on) where said host I/O requests are mostly random (not associated with the first type), for logical storage volume 2 (see ¶[64]), calculate (select) optimal page size of 8KB (second sector size value, respective sector size values) (see ¶[54], [56]). Note that 32KB (first sector size value) is larger (exceeds) than 8KB (second sector size value).)
generate a first entry of first logical block addresses and first physical block addresses associated with the first sector size value, of a logical to physical (L2P) data structure, [the first entry comprising a first number of bytes corresponding to the first physical block addresses];
store the data on the one or more computer readable storage media based on the first entry (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB (first sector size value), for said logical storage volume 1, repeating storing (generate), in virtual (logical) block (first entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (first logical block addresses) pointing to (based on) single physical page (plurality of sectors) that stores combined host data (data), said single physical page having (associated with) said optimal page size of 32KB (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (first physical block addresses) of said single physical page (see Fig. 2, ¶[65]).)
generate a second entry of second logical block addresses and second physical block addresses associated with the second sector size value, of the L2P data structure, [the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to the second number of bytes] (Meiri teaches upon (based on) determination to change page size to said optimal page size of 8KB (second sector size value), for said logical storage volume 2, repeating storing (generate), in virtual (logical) block (second entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer (second logical block addresses) pointing to (based on) single physical page (plurality of sectors) that stores combined host data (additional data), said single physical page having (associated with) said optimal page size of 8KB (see Fig. 4, ¶[76], [82-84]). Meiri also teaches said pointer points to a location (second physical block addresses) of said single physical page (see Fig. 2, ¶[65]).)
As noted in claim 15, Meiri teaches host I/O requests that are i) sequential (first type) with 32KB (first sector size value) and ii) random (not first type) with 8KB (second sector size value) but does not appear to explicitly teach said sequential (with 32KB) is associated with SLC and said random (with 8KB) is associated with different data storage.
However, Saxena teaches i) writing data to sequential addresses (first type) of SLC memory cells (single-level cell data storage) and ii) writing data to random addresses (not first type) of MLC memory cells (not single-level cell data storage) (see ¶[52]) wherein said MLC memory cells store three bits of data per memory cell or four bits of data per memory cells (see ¶[49]).)
In view of Saxena, Meiri is modified such that i) said host I/O requests that are sequential (first type) (with 32KB (first sector size value)), write data to SLC memory cells (single-level cell data storage) and ii) host I/O requests that are random (not first type) (with 8KB (second sector size value)), write data to MLC memory cells (not single-level cell data storage) that is 3/4-bits per cell.
Meiri and Saxena are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Meiri in the manner described supra because configuring multiple regions for different data types would result in compact storage of data and higher write performance (Saxena, ¶[28-29]).
As noted in claim 15, modified Meiri teaches i) generating first entry of first logical block addresses and first physical block addresses and ii) generating second entry of second logical block addresses and second physical block addresses but does not appear to explicitly teach mapping to said first and second entries in the following manner.
the first entry comprising a first number of bytes corresponding to the first physical block addresses
the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to second number of bytes
However, Yamada teaches
the first entry comprising a first number of bytes corresponding to the first physical block addresses
the second entry comprising a second number of bytes corresponding to the second physical block addresses, the first number of bytes being equal to the second number of bytes (Yamada teaches i) first address (first number of bytes) of a first entry (first entry), in page table 310 (L2P data structure), mapping to large page and ii) second virtual address (second number of bytes) of a second entry (second entry), in said page table 310, mapping to small page (see Fig. 3A, col 6 ln 56 – col 7 ln 4) wherein said large page and said small page, each is mapped to physical addresses (first physical block addresses, second physical block addresses) (see col 1 ln 29-32). Note that in Fig. 3A, same sized virtual address (first number of bytes being equal to second number of bytes) is used to map to both said lager page and said small page, where an exemplary size of said virtual address is 64-bit (number of bytes) (see Fig. 4, col 8 ln 9-21).)
In view of Yamada, modified Meiri is further modified such that i) a first 64-bit virtual address (first number of bytes) of first entry, in said L2P data structure, maps to said first physical block addresses, and ii) a second 64-bit virtual address (second number of bytes) of a second entry, in said L2P data structure, maps to said second physical block addresses, wherein same 64-bit (number of bytes) is used to map to both said first and second physical block addresses.
Meiri, Saxena and Yamada are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner described supra because by mapping same size virtual address to different physical addresses of different page sizes, number of entries (in a page table) can be reduced by selecting a correct page size for said virtual address (Yamada, col 4 ln 34-41).
Regarding claim 18, Meiri in view of Saxena and Yamada teach the memory device of claim 15 where Meiri also teaches
wherein the data includes firmware metadata or data of the operating system (see mapping in claim 14 supra)
Regarding claim 20, Meiri in view of Saxena and Yamada teach the memory device of claim 15 where Meiri also teaches
determine that the additional data is to be stored using a random write operation
wherein the determination that the additional data is not associated with the single-level cell data storage includes determining that the additional data is associated with one of triple-level cell data storage or quad-level cell data storage
wherein the determination to select one of [i) the first sector size value] or ii) the second sector size value for the additional data includes selecting the second sector size value for the additional data based on the determination that the additional data is to be stored using the random write operation and the determination that the additional data is associated with one of triple-level cell data storage or quad-level cell data storage (Meiri teaches in case (based on) host I/O requests (with corresponding host data (additional data) (see ¶[44])) that are (determine) mostly random (random write operation), said optimal page size is 8KB (second sector size value) (see ¶[55]). Note that Meiri has been modified in claim 15 such that said host I/O requests that are random, stores said host data (additional data) to MLC (triple/quad-level cell data storage) that stores 3/4-bits (triple/quad-level) per memory cell.)
Regarding claim 21, Meiri in view of Saxena and Yamada teach the memory device of claim 15 where modified Meiri also teaches
wherein the data includes data of an operating system (Meiri teaches host data (first data) corresponds to (of) applications (see ¶[44]) that are embodied using firmware (operating system) (see ¶[115]).)
Claims 4 – 5, 12 – 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena and Yamada, and further in view of Yurzola (US 20110154158).
Regarding claim 4, Meiri in view of Saxena and Yamada teach the method of claim 1 where Meiri also teaches
encoding the data[, using an error correction code (ECC) component,] to obtain encoded data, wherein a size of the encoded data is based on the first sector size, and
storing, based on the first entry stored in the L2P data structure, the encoded data in the first sector (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB (first sector size), for said logical storage volume 1, repeating storing, in virtual (logical) block (first entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer pointing to (based on) single physical page (first sector) in which host data (data), from N pages, is compressed (encoding) into said single physical page (see Fig. 4, ¶[76], [82-84]). Note that i) compression of said host data (data) results in compressed host data (encoded data) that is stored in said single physical page and ii) said N (size) pages (with (of) said host data (data)) is selected in accordance with (based on) said single page of said optimal page size (sector size).)
encoding the additional data[, using the ECC component,] to obtain additional encoded data
storing, based on the second entry of the L2P data structure, the additional encoded data in the second sector (Meiri teaches upon (based on) determination to change page size to said optimal page size of 8KB (second sector size), for said logical storage volume 2, repeating storing, in virtual (logical) block (second entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer pointing to (based on) single physical page (second sector) in which host data (additional data), from N pages, is compressed (encoding) into said single physical page (see Fig. 4, ¶[76], [82-84]). Note that i) compression of said host data (data) results in compressed host data (encoded additional data) that is stored in said single physical page.)
As noted in claim 4, modified Meiri teaches compressing host data (data, additional data) into compressed host data (encoded data, encoded additional data) but does not appear to explicitly teach said compressing is done by ECC component.
However, Yurzola teaches ECC enhancement compression module (ECC component) is used to compress (encode) control data (data, additional) into compressed control data (encoded data, encoded additional data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (data, additional data) is compressed (encoded), using ECC enhancement compression module (ECC module), into compressed host data (encoded data, encoded additional data).
Meiri, Saxena, Yamada and Yurzola are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Regarding claim 5, Meiri in view of Saxena, Yamada and Yurzola teach the method of claim 4 where Meiri also teaches
wherein the size of the encoded data is the first sector size, and (Meiri teaches combining N (size) pages (with (of) host data (data)) that are combined into a single page of optimal page size (see ¶[82]) wherein when host I/O requests types are sequential, said optimal page size is 32KB (first sector size value) (see ¶[56]). Note that said N (size) pages is the same as said one single page of said optimal page size of 32KB (first sector size value).)
wherein a size of the additional encoded data is the second sector size (Meiri teaches combining N (size) pages (with (of) host data (additional data)) that are combined into a single page of optimal page size (see ¶[82]) wherein when host I/O requests types are random, said optimal page size is 8KB (second sector size value) (see ¶[54], [56]). Note that said N (size) pages is the same as said one single page of said optimal page size of 8KB (second sector size value).)
Regarding claim 12, Meiri in view of Saxena and Yamada teach the system of claim 8 where Meiri also teaches
the controller including an error correction code (ECC) component
encoding a portion of the first data[, using the ECC component,] to obtain encoded first data,
wherein a size of the portion of the first data is based on the first sector size; and
storing the encoded first data in the first sector (Meiri teaches optimal page size is 32KB (first sector size) for host I/O requests that are mostly sequential (see ¶[56]). Meiri also teaches N pages that are combined into (storing) a single physical page (first sector) of said optimal page size wherein host data (portion of the first data), from said N pages, are compressed (encoding) into said single page (see Fig. 4, ¶[78-82]). Note that i) compression of said host data (portion of the first data) results in compressed host data (encoded first data) that is stored in said single page and ii) said N (size) pages (with (of) said host data (portion of the first data)) is selected in accordance with (based on) said single page of said optimal page size (first sector size).)
As noted in claim 12, modified Meiri teaches compressing host data (portion of the first data) into compressed host data (encoded first data) but does not appear to explicitly teach said compressing is done by ECC component in controller.
However, Yurzola teaches ECC enhancement compression module (ECC component), in controller (controller) (see Yurzola Fig. 1), is used to compress (encode) control data (portion of first data) into compressed control data (encoded first data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (portion of the first data) is compressed (encoded), using ECC enhancement compression module (ECC module) in said controller, into compressed host data (encoded first data).
Meiri, Saxena, Yamada and Yurzola are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Regarding claim 13, Meiri in view of Saxena, Yamada and Yurzola teach the system of claim 12 where Meiri also teaches
encoding a portion of the second data[, using an error correction code ECC) component,] to obtain encoded second data,
wherein a size of the portion of the second data is based on the second sector size; and
storing the encoded second data in the second sector (Meiri teaches optimal page size is 8KB (second sector size) for host I/O requests that are mostly random (see ¶[56]). Meiri also teaches N pages that are combined into (storing) a single page (second sector) of said optimal page size wherein host data (portion of the second data), from said N pages, are compressed (encoding) into said single page (see Fig. 4, ¶[78-82]). Note that i) compression of said host data (portion of the second data) results in compressed host data (encoded second data) that is stored in said single page and ii) said N (size) pages (with (of) said host data (portion of the second data)) is selected in accordance with (based on) said single page of said optimal page size (second sector size).)
As noted in claim 13, modified Meiri teaches compressing host data (portion of the second data) into compressed host data (encoded second data).
Yurzola teaches ECC enhancement compression module (ECC component), in controller (controller) (see Yurzola Fig. 1), is used to compress (encode) control data (portion of second data) into compressed control data (encoded second data) (see Yurzola ¶[12]).
In view of Yurzola, modified Meiri is further modified such that said host data (portion of the second data) is compressed (encoded), using ECC enhancement compression module (ECC module) in said controller, into compressed host data (encoded second data).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Meiri in the manner describe supra because it would enhance error correction capabilities of ECC engine (Yurzola, ¶[5]).
Claim 17 is the device claim corresponding to system claim 12, and is rejected on the same grounds as claim 12. Meiri also teaches
wherein the storage of the data includes storing the encoded data in a location of the memory device based on the first entry (Meiri teaches upon (based on) determination to change page size to said optimal page size of 32KB, for said logical storage volume 1, repeating storing, in virtual (logical) block (first entry) of mapping tree (L2P data structure) (see ¶[49-50]), pointer pointing to (based on) single physical page (a location of the memory device) (in said non-volatile data storage devices 118 (one or more computer readable storage media)) (see ¶[37])) in which host data (data), from N pages, is compressed (encoding) into said single physical page (see Fig. 4, ¶[76], [82-84]). Note that i) compression of said host data (data) results in compressed host data (encoded data) that is stored in said single physical page and ii) said N (size) pages (with (of) said host data (data)) is selected in accordance with (based on) said single page of said optimal page size (sector size).)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena and Yamada, and further in view of Chatterjee (US 8108580).
Regarding claim 19, Meiri in view of Saxena and Yamada teach the memory device of claim 15 where modified Meiri teaches selecting 8KB (second sector size value) based on determining that data (additional data) is random writes to MLC (not associated with single-level cell data storage) but does not appear to explicitly teach selecting 32KB (first sector size value) based on determining that said data is to be stored using sequential write operation.
However, Chatterjee teaches serializing random access data writes into sequential data writes (sequential write operation) (see col 6 ln 47-51).
In view of Chatterjee, modified Meiri is further modified such that said random writes of said data to said MLC (not associated with single-level cell data storage) is serialized into sequential data writes (determining that the data is to be stored using the sequential write operation). Modified Meiri already teaches in claim 15 that sequential host I/O requests use optimal page size of 32KB (first sector size value). As such, said random writes, having been serialized into sequential data writes (sequential write operation), would use said optimal page size of 32KB (first sector size value).
Meiri, Saxena, Yamada and Chatterjee are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modifed Meiri in the manner described supra because serializing random writes into sequential writes improve completion time (and reduce bottleneck) at storage (Chatterjee, col 6 ln 47-51).
Claims 23 – 24 are rejected under 35 U.S.C. 103 as being unpatentable over Meiri in view of Saxena and Yamada, and further in view of Ozimek (US 20110228580).
Regarding claim 23, Meiri in view of Saxena and Yamada teach the method of claim 1.
As noted in claim 1, modified Meiri teaches 64-bit virtual address (first number of bytes, second number of bytes), but not limited to 64-bit, associated with optimal page sizes of 32KB (first sector size value) and 8KB (second sector size value) The claimed invention improves upon said base method by using virtual address of 4 bytes (or 32-bit).
This improvement to said base method is an application of known technique from Ozimek – using 32-bit virtual address for different page sizes (see Ozimek ¶[25]).
One of ordinary skill in the art would recognize that this known technique of using 32-bit virtual address for different page sizes can also be applied to modified Meiri’s different optimal page sizes, and the result would have been predictable. In this instance, 32-bit virtual address would be used for said optimal page sizes of 32KB and 8KB. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Ozimek’s known technique would have yielded i) predictable result of 32-bit virtual address (first and second number of bytes being 4 bytes) being used (associated) with said optimal page sizes of 32KB and 8KB, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 24 is the system claim corresponding to method claim 1, and is rejected on the same grounds as claim 1.
Claim 25 is the device claim corresponding to method claim 1, and is rejected on the same grounds as claim 1.
Response to Remarks
Applicant’s remarks have been fully considered and are persuasive. Therefore, the rejection (and objection) has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly identified prior art. As noted supra, Yamada teaches using mapping same virtual address to different page sizes.
Additional Remarks
The prior art made of record and not relied upon is considered pertinent to Applicant's invention.
Ostiguy (US 9058268) teaches same sized virtual address (first number of bytes being equal to second number of bytes) is used for different page sizes (see Ostiguy col 2 ln 5-20). This appears relevant to claims 1, 8 and 15.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139
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