Prosecution Insights
Last updated: July 17, 2026
Application No. 18/909,942

ISOLATED POWER CONVERTER WITH ADJUSTABLE CHARACTERISTIC OF A BODE PLOT AND RELATED ADJUSTMENT CIRCUIT

Non-Final OA §103
Filed
Oct 09, 2024
Priority
Dec 27, 2023 — TW 112151008
Examiner
LEE, JYE-JUNE
Art Unit
Tech Center
Assignee
Leadtrend Technology Corp.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
387 granted / 456 resolved
+24.9% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
72.6%
+32.6% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 456 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is in response to the application filed on 10/09/2024. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/09/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claims 7, 13, and 17 are objected to because of the following informalities: Regarding claim 7, in line 11, “an N-type metal oxide semi-transistor” appears that it should read as “an N-type metal-oxide-semiconductor transistor.” Regarding claim 13, in line 18, “an N-type metal oxide semi-transistor” appears that it should read as “an N-type metal-oxide-semiconductor transistor.” Regarding claim 17, in line 16, “an N-type metal oxide semi-transistor” appears that it should read as “an N-type metal-oxide-semiconductor transistor.” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 2, 5, 7, 8, 11, 12, 13, 14, 15, 17, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muller (US Patent US 4,559,592) in view of Li et al. (US Patent Application Publication US 2020/0382006 A1, hereinafter “Li”), and further in view of Huang et al. (US Patent Application Publication US 2016/0141966 A1, hereinafter “Huang”). Regarding claim 1, Muller discloses (see Fig. 2) an adjustment circuit (the secondary-side feedback network comprising comparator amplifier 44, three-terminal regulator 46 and opto-coupler 48), wherein the adjustment circuit is comprised in a secondary-side controller (the secondary-side feedback control circuitry) installed at a secondary side of an isolated power converter (the secondary side, referenced to ground 2, of the isolating flyback switching power supply 20; col. 5), the adjustment circuit comprising: a voltage divider (the series-connected resistor 102, potentiometer 104 and resistor 106 connected between the output terminal 92 and ground; col. 7); a first variable resistor (potentiometer 104); an amplifier (comparator amplifier 44); and a first external capacitor, a bias resistor (resistor 94) and an optocoupler (opto-coupler 48) installed outside the secondary-side controller (col. 7). Muller does not disclose a buffer. However, Huang teaches (see Fig. 10) a buffer (2075). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller to include a buffer, as taught by Huang, because it can help provide a high input impedance, low output impedance isolating function without loading the output sensing circuit. Muller does not disclose a second variable resistor coupled to the first variable resistor and the buffer, the amplifier being coupled to the first variable resistor and the second variable resistor, wherein the first variable resistor and the second variable resistor are used for adjusting a characteristic of a Bode plot of the isolated power converter. However, Huang teaches (see Fig. 10, Fig. 13) a second variable resistor (Rsw) coupled to the first variable resistor (R1), the amplifier (2073) being coupled to the first and second variable resistors, the first variable resistor and the second variable resistor being used for adjusting a characteristic of a Bode plot (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller to include a first variable resistor and a second variable resistor coupled to the amplifier for adjusting a characteristic of a Bode plot, as taught by Huang, because it can adaptively adjust both the frequency of the zero and the mid-frequency gain of the compensator gain function to maintain a stable system response across varying operating conditions (see Huang [0009] and [0014]). Muller does not disclose an N-type metal-oxide-semiconductor transistor coupled to the amplifier. However, Li teaches (see Fig. 2) an N-type metal-oxide-semiconductor transistor (M1) coupled to the amplifier (215) (NMOS transistor M1 driven by a differential amplifier 215, the drain of M1 being in series with the diode of optocoupler 110; see [0020] “a differential amplifier 215 that drives a gate of an NMOS transistor M1”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller so that an N-type metal-oxide-semiconductor transistor is coupled to the amplifier, as taught by Li, because it can convert a control voltage into a well-defined optocoupler diode current that is proportional to the control voltage (see Li [0020]). Regarding claim 2, Muller discloses (see Fig. 2) wherein the voltage divider comprises: a first resistor (resistor 102) coupled to an output terminal of the secondary side of the isolated power converter (output terminal 92) and the buffer; and a second resistor (resistor 106) coupled to the first resistor, the buffer and ground (col. 7). Regarding claim 5, Muller does not explicitly disclose wherein the secondary-side controller is an integrated circuit. However, Li teaches (see Fig. 2) wherein the secondary-side controller is an integrated circuit (the integrated circuit forming the secondary side controller 115; see [0017] “the integrated circuit forming the remainder of secondary side controller 115”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller wherein the secondary-side controller is an integrated circuit, as taught by Li, because it can reduce the manufacturing cost and complexity associated with discrete external components (see Li [0017]). Regarding claim 7, Muller discloses (see Fig. 2) an adjustment circuit (the secondary-side feedback network comprising comparator amplifier 44, three-terminal regulator 46 and opto-coupler 48), wherein the adjustment circuit is comprised in a secondary-side controller (the secondary-side feedback control circuitry) and the secondary-side controller is installed at a secondary side of an isolated power converter (the secondary side, referenced to ground 2, of the isolating flyback switching power supply 20; col. 5), the adjustment circuit comprising: a voltage divider (the series-connected resistor 102, potentiometer 104 and resistor 106 connected between the output terminal 92 and ground; col. 7); a variable resistor (potentiometer 104) coupled to an external resistor (resistor 106) and the voltage divider; an amplifier (comparator amplifier 44) coupled to the variable resistor and the voltage divider (the comparator amplifier 44 is coupled to the tap connection of the potentiometer 104; col. 7); and a first external capacitor, a bias resistor (resistor 94) and an optocoupler (opto-coupler 48 having light-emitting diode 116) installed outside the secondary-side controller (col. 7). Muller does not disclose an N-type metal oxide semi-transistor coupled to the amplifier and a first external capacitor, a bias resistor and an optocoupler installed outside the secondary-side controller. However, Li teaches (see Fig. 2) an N-type metal-oxide-semiconductor transistor (M1) coupled to the amplifier (215) and an optocoupler (110) installed outside the secondary-side controller (200) (NMOS transistor M1 driven by a differential amplifier 215, the drain of M1 being in series with the diode of optocoupler 110; see [0020] “a differential amplifier 215 that drives a gate of an NMOS transistor M1”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller so that an N-type metal-oxide-semiconductor transistor is coupled to the amplifier and to the first external capacitor, the bias resistor and the optocoupler, as taught by Li, because it can convert a control voltage into a well-defined optocoupler diode current that is proportional to the control voltage (see Li [0020]). Muller does not disclose wherein the variable resistor is used for adjusting a characteristic of a Bode plot of the isolated power converter. However, Huang teaches (see Fig. 10, Fig. 13) wherein the variable resistor (comprising R1, Rsw) is used for adjusting a characteristic of a Bode plot of the isolated power converter (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the variable resistor of the adjustment circuit of Muller so that it is used for adjusting a characteristic of a Bode plot of the isolated power converter, as taught by Huang, because it can adaptively adjust the frequency of the zero and the mid-frequency gain of the compensator gain function to maintain a stable system response across varying operating conditions (see Huang [0009] and [0014]). Regarding claim 8, Muller discloses (see Fig. 2) wherein the voltage divider comprises: a first resistor (resistor 102) coupled to an output terminal of the secondary side of the isolated power converter (output terminal 92), the variable resistor (potentiometer 104) and the amplifier (comparator amplifier 44); and a second resistor (resistor 106) coupled to the first resistor, the variable resistor, the amplifier and ground (col. 7). Regarding claim 11, Muller does not disclose wherein the secondary-side controller is an integrated circuit. However, Li teaches (see Fig. 2) wherein the secondary-side controller is an integrated circuit (the integrated circuit forming the secondary side controller 115; see [0017] “the integrated circuit forming the remainder of secondary side controller 115”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller wherein the secondary-side controller is an integrated circuit, as taught by Li, because it can reduce the manufacturing cost and complexity associated with discrete external components (see Li [0017]). Regarding claim 12, Muller does not disclose wherein the variable resistor adjusts the characteristic of the Bode plot through a position of zero of the Bode plot. However, Huang teaches (see Fig. 10, Fig. 13) wherein the variable resistor adjusts the characteristic of the Bode plot through a position of zero of the Bode plot (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the variable resistor of the combination so that it adjusts the characteristic of the Bode plot through a position of a zero, as taught by Huang, because it can place the compensator zero to cancel a pole of the system loop gain function and thereby maintain stability (see Huang [0014]). Regarding claim 13, Muller discloses (see Fig. 1 and Fig. 2) an isolated power converter (the isolating flyback switching power supply 20) with adjustable characteristic of a Bode plot, comprising: a secondary-side controller (the secondary-side feedback control circuitry) installed at a secondary side of the isolated power converter and controlling the secondary side of the isolated power converter to receive energy from a primary side of the isolated power converter and generate an output voltage (the regulated +5 V output at terminal 92) accordingly (col. 5–col. 7), wherein the secondary-side controller comprises an adjustment circuit comprising: a voltage divider (resistor 102, potentiometer 104 and resistor 106 between output terminal 92 and ground; col. 7); a first variable resistor (potentiometer 104); an amplifier (comparator amplifier 44); and a first external capacitor, a bias resistor (resistor 94) and an optocoupler (opto-coupler 48) installed outside the secondary-side controller. Muller does not disclose a buffer. However, Huang teaches (see Fig. 10) a buffer (2075). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller to include a buffer, as taught by Huang, because it can help provide a high input impedance, low output impedance isolating function without loading the output sensing circuit. Muller does not disclose a second variable resistor coupled to the first variable resistor and the buffer; wherein the first variable resistor and the second variable resistor are used for adjusting the characteristic of the Bode plot. However, Huang teaches (see Fig. 10, Fig. 13) a second variable resistor (Rsw) coupled to the first variable resistor (R1) and the buffer (2075); wherein, the first variable resistor and the second variable resistor are used for adjusting the characteristic of the Bode plot (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller to include a second variable resistor coupled to the first variable resistor and the buffer; wherein the first variable resistor and the second variable resistor are used for adjusting the characteristic of the Bode plot, as taught by Huang, because it can adaptively adjust both the frequency of the zero and the mid-frequency gain of the compensator gain function to maintain a stable system response across varying operating conditions (see Huang [0009] and [0014]). Muller does not disclose an N-type metal-oxide-semiconductor transistor coupled to the amplifier. However, Li teaches (see Fig. 2) an N-type metal-oxide-semiconductor transistor (M1) coupled to the amplifier (215) (NMOS transistor M1 driven by a differential amplifier 215, the drain of M1 being in series with the diode of optocoupler 110; see [0020] “a differential amplifier 215 that drives a gate of an NMOS transistor M1”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller so that an N-type metal-oxide-semiconductor transistor is coupled to the amplifier, as taught by Li, because it can convert a control voltage into a well-defined optocoupler diode current that is proportional to the control voltage (see Li [0020]). Regarding claim 14, Muller discloses (see Fig. 1 and Fig. 2) further comprising: a primary-side controller (the primary-side control circuitry comprising integrated-circuit timer device 36 and MOS switching transistor 38) installed at the primary side of the isolated power converter and controlling the primary side of the isolated power converter to transmit the energy of the primary side of the isolated power converter to the secondary side of the isolated power converter (the timer device 36 controls switching of transistor 38 to power the primary winding 52 of transformer 40; col. 5–col. 6). Regarding claim 15, Muller does not disclose wherein the secondary-side controller is an integrated circuit. However, Li teaches (see Fig. 2) wherein the secondary-side controller is an integrated circuit (the integrated circuit forming the secondary side controller 115; see [0017] “the integrated circuit forming the remainder of secondary side controller 115”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Muller wherein the secondary-side controller is an integrated circuit, as taught by Li, because it can reduce the manufacturing cost and complexity associated with discrete external components (see Li [0017]). Regarding claim 17, Muller discloses (see Fig. 1 and Fig. 2) an isolated power converter (the isolating flyback switching power supply 20) with adjustable characteristic of a Bode plot, comprising: a secondary-side controller (the secondary-side feedback control circuitry) installed at a secondary side of the isolated power converter and controlling a secondary side of the isolated power converter to receive energy from a primary side of the isolated power converter and generate an output voltage (the regulated +5 V output at terminal 92) accordingly (col. 5–col. 7), wherein the secondary-side controller comprises an adjustment circuit comprising: a voltage divider (resistor 102, potentiometer 104 and resistor 106; col. 7); a variable resistor (potentiometer 104) coupled to an external resistor (resistor 106) and the voltage divider; an amplifier (comparator amplifier 44) coupled to the variable resistor and the voltage divider; and a first external capacitor, a bias resistor (resistor 94) and an optocoupler (opto-coupler 48) installed outside the secondary-side controller. Muller does not disclose an N-type metal-oxide-semiconductor transistor coupled to the amplifier. However, Li teaches (see Fig. 2) an N-type metal-oxide-semiconductor transistor (M1) coupled to the amplifier (215) (NMOS transistor M1 driven by a differential amplifier 215, the drain of M1 being in series with the diode of optocoupler 110; see [0020] “a differential amplifier 215 that drives a gate of an NMOS transistor M1”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller so that an N-type metal-oxide-semiconductor transistor is coupled to the amplifier, as taught by Li, because it can convert a control voltage into a well-defined optocoupler diode current that is proportional to the control voltage (see Li [0020]). Muller does not disclose wherein the variable resistor is used for adjusting the characteristic of the Bode plot. However, Huang teaches (see Fig. 10, Fig. 13) a second variable resistor (Rsw) coupled to the first variable resistor (R1), the amplifier (2073) being coupled to the first and second variable resistors, the first variable resistor and the second variable resistor being used for adjusting a characteristic of a Bode plot (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller to include a first variable resistor and a second variable resistor coupled to the amplifier for adjusting a characteristic of a Bode plot, as taught by Huang, because it can adaptively adjust both the frequency of the zero and the mid-frequency gain of the compensator gain function to maintain a stable system response across varying operating conditions (see Huang [0009] and [0014]). Regarding claim 18, Muller discloses (see Fig. 1 and Fig. 2) further comprising: a primary-side controller (the primary-side control circuitry comprising integrated-circuit timer device 36 and MOS switching transistor 38) installed at the primary side of the isolated power converter and controlling the primary side of the isolated power converter to transmit the energy of the primary side of the isolated power converter to the secondary side of the isolated power converter (col. 5–col. 6). Regarding claim 19, Muller does not explicitly disclose wherein the secondary-side controller is an integrated circuit. However, Li teaches (see Fig. 2) wherein the secondary-side controller is an integrated circuit (the integrated circuit forming the secondary side controller 115; see [0017] “the integrated circuit forming the remainder of secondary side controller 115”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Muller wherein the secondary-side controller is an integrated circuit, as taught by Li, because it can reduce the manufacturing cost and complexity associated with discrete external components (see Li [0017]). Regarding claim 20, Muller does not disclose wherein the variable resistor adjusts the characteristic of the Bode plot through a position of zero of the Bode plot. However, Huang teaches (see Fig. 10, Fig. 13) wherein the variable resistor adjusts the characteristic of the Bode plot through a position of zero of the Bode plot (variable RC circuit comprising C1, R1, and Rsw that adjusts the frequency of the zero and the mid-frequency gain of the compensator gain function; see [0009] “adaptively adjusting a frequency of a zero of a compensator gain function and/or a mid-frequency gain”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the variable resistor of the combination so that it adjusts the characteristic of the Bode plot through a position of a zero, as taught by Huang, because it can place the compensator zero to cancel a pole of the system loop gain function and thereby maintain stability (see Huang [0014]). Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Muller in view of Li and Huang, and further in view of Yen et al. (US Patent Application Publication US 2008/0218221 A1, hereinafter “Yen”). Regarding claim 6, Muller does not disclose wherein the first variable resistor and the second variable resistor adjust the characteristic of the Bode plot through positions of poles and zero of the Bode plot. However, Yen teaches (see Fig. 1) wherein the first variable resistor (R1) and the second variable resistor (R2) adjust the characteristic of the Bode plot through positions of poles and zero of the Bode plot (see [0007] “when the variable resistors R1 or R2 are adjusted, the originally feedback-controlled equivalent input resistance Rin and equivalent output resistance Rout are affected…, and further, the positions of the zero point and pole point of the feedback control are also affected.”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustment circuit of Muller wherein the first variable resistor and the second variable resistor adjust the characteristic of the Bode plot through positions of poles and zero of the Bode, as taught by Yen, because it can adjust the compensator frequency response (poles, zeroes and gains) to obtain a desired response bandwidth and dynamic behavior. Regarding claim 16, Muller does not disclose wherein the first variable resistor and the second variable resistor adjust the characteristic of the Bode plot through positions of poles and zero of the Bode plot. However, Yen teaches (see Fig. 1) wherein the first variable resistor (R1) and the second variable resistor (R2) adjust the characteristic of the Bode plot through positions of poles and zero of the Bode plot (see [0007] “when the variable resistors R1 or R2 are adjusted, the originally feedback-controlled equivalent input resistance Rin and equivalent output resistance Rout are affected…, and further, the positions of the zero point and pole point of the feedback control are also affected.”). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Muller wherein the first variable resistor and the second variable resistor adjust the characteristic of the Bode plot through positions of poles and zero of the Bode, as taught by Yen, because it can adjust the compensator frequency response (poles, zeroes and gains) to obtain a desired response bandwidth and dynamic behavior. Claims 3, 4, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Muller in view of Li and Huang, and further in view of Falco (E. Falco, “ANP113 – Feedback loop compensation of a current-mode Flyback converter with optocoupler,” Application Note ANP113a, Würth Elektronik eiSos, 2023/08/18). Regarding claim 3, Muller modified in view of Li and Huang teaches an adjustment circuit forming a Type 2 compensator implemented with an amplifier and an N-type metal-oxide-semiconductor transistor (simulating a TL431) driving an optocoupler, but does not explicitly disclose the transfer function G(s) of the Bode plot as recited. However, Falco teaches (see Section 5.3) the transfer function G(s) of the Bode plot as recited (a Type 2 compensator implemented with a TL431 and an optocoupler having the transfer function C(s) = −(Rc·CTR/RLED)·(R2/R1)·(1 + 1/(sR2C1)) / (1 + sRc(Ccol + Copto)) (see Eq. (34)); a midband gain |Gm| = (Rc·CTR/RLED)·(R2/R1) (see Eq. (35)); an origin pole; a zero at fz = 1/(2πR2C1) (see Eq. (36)); and a pole at fp = 1/(2πRc(Ccol + Copto)) (see Eq. (37)), where Rc is the primary-side optocoupler pull-up resistor and Copto is the optocoupler parasitic capacitance (see ANP113a §5.3, Eqs. (34)–(37)). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the adjustment circuit of the combination, being a Type 2 TL431/optocoupler compensator, has the recited transfer function G(s), as taught by Falco, since the recited G(s) is the inherent mathematical characterization of such a Type 2 compensator and its terms map directly onto the compensator parameters — the current transfer ratio CTR; the primary-side pull-up resistance Rpullup (i.e. Rc); the optocoupler resistor RLED; the voltage-divider ratio Rdn/(Rup + Rdn); the zero-setting resistance Rs (the first variable resistor of Huang) in series with the external resistance R2 and the capacitance C1; the integrator resistance Ri (the second variable resistor of Huang); and the pole-setting capacitances C2 and Copto (see Falco, ANP113a §5.3). Regarding claim 4, Muller in view of Li and Huang does not explicitly disclose the zeroth pole, the first pole and the zero as recited. However, Falco teaches (see Section 5.3) the zeroth pole, the first pole and the zero as recited (an origin/integrator pole; a zero at fz = 1/(2πR2C1) (see Eq. (36)); and a pole at fp = 1/(2πRc(Ccol + Copto)) (see Eq. (37)) (see ANP113a §5.3, Eqs. (36)–(37)). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the zeroth pole ωp0 = 1/(RiC1), the first pole ωp1 = 1/(Rpullup(C2 + Copto)), and the zero ωz1 = 1/(C1(Rs + R2)) are the inherent poles and zero of the Type 2 compensator of the combination, as taught by Falco, since the recited 1/(RC) expressions are the standard pole and zero locations of such a compensator (see Falco, ANP113a §5.3). Regarding claim 9, Muller modified in view of Li and Huang teaches an adjustment circuit forming a Type 2 compensator implemented with an amplifier and an N-type metal-oxide-semiconductor transistor (simulating a TL431) driving an optocoupler, but does not explicitly disclose the transfer function G(s) of the Bode plot as recited. However, Falco teaches (see Section 5.3) the transfer function G(s) of the Bode plot as recited (a Type 2 compensator implemented with a TL431 and an optocoupler having the transfer function C(s) = −(Rc·CTR/RLED)·(R2/R1)·(1 + 1/(sR2C1)) / (1 + sRc(Ccol + Copto)) (see Eq. (34)); a midband gain |Gm| = (Rc·CTR/RLED)·(R2/R1) (see Eq. (35)); an origin pole; a zero at fz = 1/(2πR2C1) (see Eq. (36)); and a pole at fp = 1/(2πRc(Ccol + Copto)) (see Eq. (37)), where Rc is the primary-side optocoupler pull-up resistor and Copto is the optocoupler parasitic capacitance (see ANP113a §5.3, Eqs. (34)–(37)). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the adjustment circuit of the combination, being a Type 2 TL431/optocoupler compensator, has the recited transfer function G(s), as taught by Falco, since the recited G(s) is the inherent mathematical characterization of such a Type 2 compensator and its terms map directly onto the compensator parameters — the current transfer ratio CTR; the primary-side pull-up resistance Rpullup (i.e. Rc); the optocoupler resistor RLED; the voltage-divider ratio Rdn/(Rup + Rdn); the zero-setting resistance Rs (the first variable resistor of Huang) in series with the external resistance R2 and the capacitance C1; the integrator resistance Ri (the second variable resistor of Huang); and the pole-setting capacitances C2 and Copto (see Falco, ANP113a §5.3). Regarding claim 10, Muller in view of Li and Huang does not explicitly disclose the zeroth pole, the first pole and the zero as recited. However, Falco teaches (see Section 5.3) the zeroth pole, the first pole and the zero as recited (an origin/integrator pole; a zero at fz = 1/(2πR2C1) (see Eq. (36)); and a pole at fp = 1/(2πRc(Ccol + Copto)) (see Eq. (37)) (see ANP113a §5.3, Eqs. (36)–(37)). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the zeroth pole ωp0 = 1/(RiC1), the first pole ωp1 = 1/(Rpullup(C2 + Copto)), and the zero ωz1 = 1/(C1(Rs + R2)) are the inherent poles and zero of the Type 2 compensator of the combination, as taught by Falco, since the recited 1/(RC) expressions are the standard pole and zero locations of such a compensator (see Falco, ANP113a §5.3). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2015/0029762 A1 discloses a secondary-side regulated flyback converter having an output-sense voltage divider, a TL431/differential-amplifier regulation feedback controller, and an optocoupler. US 2021/0050777 A1 discloses a reconfigurable compensator having a switchable resistor network that causes a zero of the compensator transfer function to move in frequency steps. US 2017/0366091 A1 discloses an isolated USB-PD power converter providing multiple output voltages with a secondary-side controller and a resistance divider. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JYE-JUNE LEE/Examiner, Art Unit 2838 /JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Oct 09, 2024
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683514
CIRCUIT AND METHOD OF CURRENT SENSING FOR LDO-FREE BASED RECTIFIER IN WIRELESS CHARGER SYSTEM
2y 7m to grant Granted Jul 14, 2026
Patent 12669841
CONTROL DEVICE FOR SOLAR POWER GENERATION SYSTEM
2y 1m to grant Granted Jun 30, 2026
Patent 12651971
ACTIVE CLAMP FLYBACK CONVERTER WITH ACCURATE CURRENT SENSE AND THE METHOD THEREOF
2y 6m to grant Granted Jun 09, 2026
Patent 12647023
SYSTEMS AND METHODS FOR ADAPTIVE DEAD TIME CONTROL OF A DEVICE INTEGRATED WITH CONVERTERS THAT IMPLEMENT SOFT SWITCHING
2y 3m to grant Granted Jun 02, 2026
Patent 12640640
GATE DRIVE CIRCUIT AND POWER CONVERSION DEVICE
2y 6m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
88%
With Interview (+3.3%)
2y 3m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 456 resolved cases by this examiner. Grant probability derived from career allowance rate.

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