CTNF 18/909,979 CTNF 79960 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Introduction This is a response to the applicant’s filing filed on 10/09/2024. In virtue of this filing, claims 1-20 are currently presented in the instant application. Priority 02-26 AIA Receipt is acknowledged of papers submitted under 35 U.S.C 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/09/2024 has been considered by Examiner and made of record in the application file. Drawings The drawing submitted on 10/09/2024 has been considered by Examiner and made of record in the application file. Specification The specification submitted on 10/09/2024 has been considered by Examiner and made of record in the application file. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1-3 and 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over NOMURA et al. (US Pub. No.: 2012/0043583, hereinafter, “NOMURA”) in view of YAMAGUCHI (US Pub. No.: 2021/0399758) . Regarding claims 1 and 13 , NOMURA teaches a communication device comprising (see figures 2A, 4A-4B): a high frequency including (see figure 2A, high frequency module 1a, [0031]) a mounting substrate having a first main surface and a second main surface which face each other (see figure 2A, wiring board 2, [0031]); a first electronic component disposed on the first main surface of the mounting substrate, the first electronic component being one of chip of inductor or chip of capacitor (see figure 2, electronic component 3a, [0035]); a second electronic component disposed on the first main surface of the mounting substrate, the second electronic component being chip of inductor or chip of capacitor (see figure 2, electronic component 3a, [0035]); a third electronic component disposed between the first electronic component and the second electronic component on the first main surface of the mounting substrate, of chip of inductor or chip of capacitor (see figure 2, electronic component 3b, [0035]); and a side surface shield electrode provided on at least one side surface of the third electronic component (see figure 2A, 4A-4B, side surface electro 3b1, electronic component 3b, [0035, 0055-0056]). wherein the mounting substrate includes a ground layer (see [0055]), and the side surface shield electrode is connected to the ground layer (see [0055]). It should be noticed that NOMURA fails to teach a first electronic component, a second electronic component, and a third electronic component are filter or amplifier or matching network; and a signal processing circuit connected to the high frequency module to perform signal processing on a high frequency signal. However, YAMAGUCHI teaches a first electronic component, a second electronic component, and a third electronic component are filter or amplifier or matching network; and a signal processing circuit connected to the high frequency module to perform signal processing on a high frequency signal (see figures 1 and 4, RFIC or BBIC, filter, PA and matching circuit, [0027, 0040], it is clearly seen that one skill in the art can modified a first electronic component is a filter, a second electronic component is amplified, and a third electronic component is filter to be an obvious matter of design choice. Rearrangement of Parts In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of YAMAGUCHI into view of YAMAGUCHI in order to prevent the interference between the components. Regarding claims 2 and 14 , NOMURA further teaches a resin provided on the first main surface of the mounting substrate to cover the first electronic component, the second electronic component, the third electronic component, and the side surface shield electrode; and an outer shield electrode provided on at least an outer surface of the resin and connected to the ground layer, wherein the side surface shield electrode is connected to the outer shield electrode (see figure 2A, resin 4, shielding electrode layer 95, shield film 6, electronic component 3a, 3b, [0031]). Regarding claims 3 and 15 , NOMURA further teaches a top surface shield electrode provided on a main surface on a side opposite to a side of the mounting substrate in the third electronic component and connected to the side surface shield electrode; and a recessed conductor layer that connects the top surface shield electrode and the outer shield electrode (see figure 4c, recess 5a, wiring electro, [0033]). Regarding claim 10 , NOMURA further teaches a fourth electronic component disposed between the first electronic component and the second electronic component on the first main surface of the mounting substrate and adjacent to the third electronic component; and a bonding wire provided between the third electronic component and the fourth electronic component on the first main surface of the mounting substrate, wherein both ends of the bonding wire are connected to pad electrodes provided between the third electronic component and the fourth electronic component on the first main surface of the mounting substrate and connected to the ground layer (see figure 3A, components 3a, 3b). Regarding claim 11 , YAMAGUCHI further teaches the third electronic component includes a piezoelectric substrate (see [0040]). Regarding claim 12 , NOMURA further teaches the resin includes a through hole that exposes a predetermined region of a main surface of the side surface shield electrode of the third electronic component, and the outer shield electrode further covers an inner peripheral surface of the through hole and the predetermined region of the side surface shield electrode and is connected to the side surface shield electrode by coming into contact with the predetermined region (see figure 4c, recess 5a, wiring electro, [0033]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-9 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 4 and 16 , the prior art made of record fails to clearly teach or fairly suggest the feature of a top surface shield electrode provided on a main surface on a side opposite to a side of the mounting substrate in the third electronic component and connected to the side surface shield electrode; and a bonding wire, wherein the bonding wire has a first end portion and a predetermined portion which is a portion different from the first end portion, the first end portion of the bonding wire is connected to the top surface shield electrode, and the predetermined portion of the bonding wire is connected to the outer shield electrode. Regarding claims 7 and 19 , the prior art made of record fails to clearly teach or fairly suggest the feature of a first top surface shield electrode provided on a main surface on a side opposite to a side of the mounting substrate in the third electronic component and connected to a first side surface shield electrode which is the side surface shield electrode; a fourth electronic component disposed between the first electronic component and the second electronic component on the first main surface of the mounting substrate and adjacent to the third electronic component; a second side surface shield electrode provided on at least one side surface of the fourth electronic component and connected to the ground layer; a second top surface shield electrode provided on a main surface on a side opposite to the side of the mounting substrate in the fourth electronic component and connected to the second side surface shield electrode; and a bonding wire having a first end portion and a second end portion, wherein the first end portion of the bonding wire is connected to the first top surface shield electrode or the second top surface shield electrode, and the second end portion of the bonding wire is connected to a pad electrode provided between the third electronic component and the fourth electronic component on the first main surface of the mounting substrate. Regarding claims 8 and 20 , the prior art made of record fails to clearly teach or fairly suggest the feature of a first top surface shield electrode provided on a main surface on a side opposite to a side of the mounting substrate in the third electronic component and connected to a first side surface shield electrode which is the side surface shield electrode; a fourth electronic component disposed between the first electronic component and the second electronic component on the first main surface of the mounting substrate and adjacent to the third electronic component; a second side surface shield electrode provided on at least one side surface of the fourth electronic component and connected to the ground layer; a second top surface shield electrode provided on a main surface on a side opposite to the side of the mounting substrate in the fourth electronic component and connected to the second side surface shield electrode; and a bonding wire having a first end portion and a second end portion, wherein the first end portion of the bonding wire is connected to the first top surface shield electrode, and the second end portion of the bonding wire is connected to the second top surface shield electrode. Regarding claim 9 , the prior art made of record fails to clearly teach or fairly suggest the feature of a resin provided on the first main surface to cover the first electronic component, the second electronic component, the third electronic component, and the side surface shield electrode; an outer shield electrode provided on at least an outer surface of the resin and connected to the ground layer; a top surface shield electrode provided on a main surface on a side opposite to a side of the mounting substrate in the third electronic component and connected to the side surface shield electrode; and a bonding wire having a first end portion and a second end portion, wherein the outer shield electrode has a plurality of side surface portions provided on a plurality of side surfaces of the resin, the third electronic component is adjacent to one side surface portion of the plurality of side surface portions, the first end portion of the bonding wire is connected to the top surface shield electrode provided in the third electronic component, and the second end portion of the bonding wire is connected to the one side surface portion of the outer shield electrode. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuan A. Pham whose telephone number is (571) 272-8097, the fax number is (571) 273-8097 and the email is tuan.pham01@uspto.gov. The examiner can normally be reached on Monday through Friday, 8:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yuwen (Kevin) Pan can be reached on (571) 272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN PHAM/ Primary Examiner, Art Unit 2649 Application/Control Number: 18/909,979 Page 2 Art Unit: 2649 Application/Control Number: 18/909,979 Page 3 Art Unit: 2649 Application/Control Number: 18/909,979 Page 4 Art Unit: 2649 Application/Control Number: 18/909,979 Page 5 Art Unit: 2649 Application/Control Number: 18/909,979 Page 6 Art Unit: 2649 Application/Control Number: 18/909,979 Page 7 Art Unit: 2649 Application/Control Number: 18/909,979 Page 8 Art Unit: 2649 Application/Control Number: 18/909,979 Page 9 Art Unit: 2649 Application/Control Number: 18/909,979 Page 10 Art Unit: 2649
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