Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 10/09/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2, 3, 5, 7, 9, 10, 12, and 14 are objected to because of the following informalities:
Regarding claim 2, in line 1, “wherein said low-side is said longer phase” appears that it should read as “wherein said low-side phase is said longer phase”.
Regarding claim 3, in line 7, “in said low-side phases” appears that it should read as “in said low-side phase”;
in line 7-8, “in said high-side phases” appears that it should read as “in said high-side phase”.
Regarding claim 5, in line 12, “said second gate drive signal” appears that it should read as “said second drive signal”;
in line 15, “said sensed-signal” appears that it should read as “said sensed-current signal”.
Regarding claim 7, in line 19, “the junction of said resistor” appears that it should read as “the junction of said first resistor”.
Regarding claim 9, in line 1, “wherein said low-side is said longer phase” appears that it should read as “wherein said low-side phase is said longer phase”.
Regarding claim 10, in line 7, “in said low-side phases” appears that it should read as “in said low-side phase”;
in line 8, “in said high-side phases” appears that it should read as “in said high-side phase”.
Regarding claim 12, in line 1, “claim10” appears that it should read as “claim 10”;
in line 12, “said second gate drive signal” appears that it should read as “said second drive signal”;
in line 15, “said sensed-signal” appears that it should read as “said sensed-current signal”.
Regarding claim 14, in line 1, “The power stage of claim 13” appears that it should read as “The VRM of claim 13”;
in line 19, “the junction of said resistor” appears that it should read as “the junction of said first resistor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Patent Application Publication US 2024/0223065 A1, hereinafter “Su”) in view of Wu et al. (US Patent Application Publication US 2022/0045605 A1, hereinafter “Wu”) and Yang et al. (US Patent Application Publication US 2014/0253061 A1, hereinafter “Yang”).
Regarding claim 1, Su discloses (see Fig. 1 and Fig. 3 of Su) a power stage of a switching converter (buck converter, see [0027] of Su) comprising: a high-side switch (HS) and a low-side switch (LS) respectively operated by a first drive signal and a second drive signal (gate signals TG and BG) to drive respective currents through an inductor (L) in a high-side phase and a low-side phase (the inductor current increasing during the on-time of HS and decreasing during the on-time of LS, see [0030] and [0070] of Su); a gate driver to generate said first drive signal and said second drive signal (the circuit that generates the gate signals TG and BG); and a current-sense block to generate a sensed-current signal representing an instantaneous magnitude of inductor-current flowing through said inductor (the sampled voltage Vcs is generated based on the current through the conducting switch, see [0028]-[0030] of Su).
Su further discloses (see Fig. 1 and Fig. 3 of Su) that said sensed-current signal is blanked for a first duration upon start of a longer phase of said high-side phase and said low-side phase, with the other one being a shorter phase, and is un-blanked upon end of said first duration (the on-time of the sensed switch includes an initial blanking interval t1 in which Vcs is not tracked, followed by a detection interval t2 in which Vcs is tracked, see [0041] and [0046]-[0047] of Su), wherein a duration of said longer phase is greater than or equal to a duration of said shorter phase, the sampling being performed during whichever on-time is longer and the inductor current being reconstructed during the other, shorter on-time (see [0019], [0040], and [0052] of Su).
Su does not disclose a gate driver to generate said first and second drive signals based on a control signal received from a phase controller, wherein said control signal is received with a first logic level in a first interval and with a second logic level in a second interval; nor that said current-sense block generates a first pulse starting synchronous with said start of said longer phase and with pulse-width equaling said first duration; nor that said gate driver receives said first pulse and generates a delayed pulse starting synchronous with said start of said longer phase and with pulse-width equaling a sum of said first duration and a second duration.
However, Wu teaches (see Fig. 4 and Fig. 7) a power stage (smart power stage 420) in which a gate driver (PWM logic and FET driver 422) generates the drive signals for the high-side switch (Q1) and the low-side switch (Q2) based on a control signal (PWM signal PWM1) received from a phase controller (power controller 410), wherein the gate driver receives the control signal with a first logic level in a first interval (a high state of the PWM signal) and drives the high-side switch (Q1), and receives the control signal with a second logic level in a second interval (a low state of the PWM signal) and drives the low-side switch (Q2) (see [0023]-[0024] of Wu); wherein a first pulse is generated with pulse-width equaling said first duration (a blanking time TBlank that begins when the low-side gate driver signal LG is asserted) (see [0019] and [0025] of Wu); and wherein a delayed pulse is generated with pulse-width equaling a sum of said first duration and a second duration (the blanking time TBlank followed by a sense time TSense), the low-side switch (Q2) being held on at least through said sum so that a second low-side current (Isense2) is detected at the sense time TSense after the blanking time TBlank while the low-side switch (Q2) is turned on (see [0025] and [0029] of Wu).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su such that the gate driver generates said first and second drive signals based on a control signal received from a phase controller with a first logic level in a first interval and a second logic level in a second interval, and such that the current-sense block generates a first pulse equaling said first duration and the gate driver generates a delayed pulse equaling a sum of said first duration and a second duration, as taught by Wu, because doing so provides a defined blanking interval followed by a sensing window within the on-time so that the inductor current can be sampled accurately after the switching noise has subsided (see [0019] and [0025] of Wu).
Su does not disclose that said gate driver generates drive signal for the switch being driven with said longer phase, said drive signal being with said first logic level for a duration of at least said pulse-width of said delayed pulse.
However, Yang teaches a current-mode switching converter (see Fig. 3 of Yang) in which a minimum-on-time pulse (Min_on) is generated, the rising edge of which is aligned with the rising edge of the periodic turn-on clock signal (Clk_shot), to ensure that the sensed switching element (high-side switching element 40) is turned on for a minimum amount of time during each switching cycle, the Min_on pulse being applied through an inverter (81) and an AND gate (73) to the OR gate (72) so that the SR latch (70) cannot be reset until the Min_on pulse falls, said minimum on-time (also known as blanking time) being employed to prevent noise generated by an off-to-on transition “from corrupting the sensing of the inductor current” (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su such that the gate driver drives the switch being driven with said longer phase with said first logic level for a duration of at least said pulse-width of said delayed pulse, as taught by Yang, because doing so guarantees that the switch remains on through the entire blanking interval and the following sensing window so that a valid, uncorrupted inductor current sample is captured during the longer phase in every switching cycle (see [0034] of Yang).
Regarding claim 2, Su discloses (see Fig. 1 and Fig. 3 of Su) that the low-side switch is the longer phase in applications with a small duty cycle, the on-time of the low-side switch being sufficiently long to allow detection while the on-time of the high-side switch is short (see [0042] and [0052] of Su).
Su does not disclose that said sum represents a desired minimum duration for which said low-side switch is to be ON in said low-side phase.
However, Yang teaches (see Fig. 3 of Yang) forcing a minimum on-time (Min_on) on the sensed switch (high-side switching element 40) so that the switch remains conducting long enough for valid current sensing (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su wherein said sum represents a desired minimum duration for which said low-side switch is to be ON, as taught by Yang, because it can ensure that the blanking interval and the sensing window both fall within the low-side on-time so that a valid inductor current sample is captured each cycle.
Regarding claim 8, Su discloses (see Fig. 1 and Fig. 3 of Su) a voltage regulator module comprising a power stage (buck power stage voltage regulator of Fig. 1) comprising: a high-side switch (HS) and a low-side switch (LS) respectively operated by a first drive signal and a second drive signal (gate signals TG and BG) to drive respective currents through an inductor (L) in a high-side phase and a low-side phase (the inductor current increasing during the on-time of HS and decreasing during the on-time of LS, see [0030] and [0070] of Su); a gate driver to generate said first drive signal and said second drive signal (the circuit that generates the gate signals TG and BG); and a current-sense block to generate a sensed-current signal representing an instantaneous magnitude of inductor-current flowing through said inductor (the sampled voltage Vcs is generated based on the current through the conducting switch, see [0028]-[0030] of Su).
Su further discloses (see Fig. 1 and Fig. 3 of Su) that said sensed-current signal is blanked for a first duration upon start of a longer phase of said high-side phase and said low-side phase, with the other one being a shorter phase, and is un-blanked upon end of said first duration (the on-time of the sensed switch includes an initial blanking interval t1 in which Vcs is not tracked, followed by a detection interval t2 in which Vcs is tracked, see [0041] and [0046]-[0047] of Su), wherein a duration of said longer phase is greater than or equal to a duration of said shorter phase, the sampling being performed during whichever on-time is longer and the inductor current being reconstructed during the other, shorter on-time (see [0019], [0040], and [0052] of Su).
Su does not disclose comprising a phase controller to generate a regulated supply voltage on a first supply node based on an input voltage received at an input node, and a smart power stage (SPS) comprising said high-side switch, low-side switch, gate driver, and current-sense block; nor that said current-sense block generates a first pulse equaling said first duration and that said gate driver generates a delayed pulse equaling a sum of said first duration and a second duration. However, Wu teaches (see Fig. 4 and Fig. 7) a voltage regulator module (power system 400) in which a phase controller (power controller 410) generates a regulated supply voltage on a first supply node (the load voltage Vload) based on an input voltage received at an input node (the supply voltage Vss), the module comprising a smart power stage (420) having the high-side switch (Q1), the low-side switch (Q2), and the gate driver (PWM logic and FET driver 422), the low-side FET current being detected with a blanking time (TBlank) followed by a sense time (TSense) (see [0023]-[0025] and [0029] of Wu).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su to comprise a phase controller and a smart power stage, and such that the current-sense block generates a first pulse equaling said first duration and the gate driver generates a delayed pulse equaling a sum of said first duration and a second duration, as taught by Wu, because doing so provides a defined blanking interval followed by a sensing window within the on-time so that the inductor current can be sampled accurately after the switching noise has subsided (see [0019] and [0025] of Wu). Su does not disclose that said gate driver generates drive signal for the switch being driven with said longer phase with said first logic level for a duration of at least said pulse-width of said delayed pulse.
However, Yang teaches (see Fig. 3 of Yang) the minimum-on-time pulse (Min_on) and its enforcement by way of the inverter (81), AND gate (73), and OR gate (72) controlling the reset of the SR latch (70) so that the sensed switching element (high-side switching element 40) cannot be turned off until the Min_on pulse falls (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su such that the gate driver drives the switch being driven with said longer phase with said first logic level for a duration of at least said pulse-width of said delayed pulse, as taught by Yang, because doing so guarantees that the switch remains on through the entire blanking interval and the following sensing window so that a valid, uncorrupted inductor current sample is captured during the longer phase in every switching cycle (see [0034] of Yang).
Regarding claim 9, Su discloses (see Fig. 1 and Fig. 3 of Su) that the low-side switch is the longer phase in applications with a small duty cycle, the on-time of the low-side switch being sufficiently long to allow detection while the on-time of the high-side switch is short (see [0042] and [0052] of Su).
Su does not disclose that said sum represents a desired minimum duration for which said low-side switch is to be ON in said low-side phase.
However, Yang teaches (see Fig. 3 of Yang) forcing a minimum on-time (Min_on) on the sensed switch (high-side switching element 40) so that the switch remains conducting long enough for valid current sensing (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator module of Su wherein said sum represents a desired minimum duration for which said low-side switch is to be ON, as taught by Yang, because it can ensure that the blanking interval and the sensing window both fall within the low-side on-time so that a valid inductor-current sample is captured each cycle.
Claims 3, 4, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Wu, Yang, and Chen et al. (US Patent Application Publication US 2009/0015069 A1, hereinafter “Chen”).
Regarding claim 3, Su discloses (see Fig. 1 and Fig. 3 of Su) a current-measuring block to measure said instantaneous magnitude of inductor-current flowing through said inductor in said low-side phase and to emulate said inductor-current in said high-side phase (the inductor current sampling circuit detects the current through the low-side switch during its on-time to output Vcs, and the inductor current generator circuit generates a reconstructed signal during the on-time of the high-side switch, see [0030]-[0031] and [0049] of Su).
Su does not disclose a first delay block to receive said control signal and to generate a delayed control signal by delaying high-to-low transitions of said control signal by said first duration, and an XOR gate to receive said control signal and said delayed control signal and to generate said first pulse.
However, Chen teaches (see Fig. 5, Fig. 7, and Fig. 8) an edge detector (edge detector 604 of Fig. 7 and Fig. 8) of a multi-channel switching converter (see 400 of Fig. 5 of Chen) that generates a blanking pulse (signal Se) by means of an RC delay circuit (700) that delays the pulse-width-modulation signal (PWM1) to produce a delayed signal (PWM1′) and an exclusive-OR (XOR) gate (702) that generates the blanking pulse (Se) according to the modulation signal (PWM1) and the delayed signal (PWM1′) (see Fig. 8 and [0024] of Chen).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power stage of Su to comprise a first delay block and an XOR gate to generate said first pulse, as taught by Chen, because it can help provide a simple and accurate means of generating a blanking pulse whose width corresponds to said first duration directly from the control signal.
Regarding claim 4, Su does not disclose that said gate driver comprises a second delay block to receive said first pulse and to delay ending edges of said first pulse by said second duration to generate ending edges of said delayed pulse.
However, Wu teaches (see Fig. 5 and Fig. 7 of Wu) that the sensed low-side window comprises a blanking duration (TBlank) followed by a sense duration (TSense), so that the delayed interval extends beyond the blanking interval by the sense duration (see [0025] and [0029] of Wu).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate driver of Su to comprise a second delay block that extends the ending edges of said first pulse by said second duration to generate said delayed pulse, as taught by Wu, because doing so extends the on-time beyond the blanking interval by the sense duration so that a valid current sample can be taken within the sensing window (see [0025] of Wu).
Su does not disclose that said gate driver comprises an OR gate to receive said delayed pulse and a complement of said control signal and to generate said drive signal for said low-side switch.
However, Yang teaches (see Fig. 3 of Yang) that the minimum-on-time pulse (Min_on) is combined into the switch-control path through an OR gate (72) so as to hold the switch on for the pulse duration, the minimum-on-time pulse (Min_on) being applied by way of an AND gate (73) and an inverter (81) to the OR gate (72) that controls the reset of the SR latch (70) and thereby the turn-off of the switch (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate driver of Su to comprise an OR gate that receives said delayed pulse and a complement of said control signal to generate said drive signal for said low-side switch, as taught by Yang, because doing so holds the low-side switch on for at least the delayed pulse duration, thereby guaranteeing a valid inductor current sample each cycle (see [0034] of Yang).
Regarding claim 10, Su discloses (see Fig. 1 and Fig. 3 of Su) a current-measuring block to measure said instantaneous magnitude of inductor-current flowing through said inductor in said low-side phase and to emulate said inductor-current in said high-side phase (the inductor current sampling circuit detects the current through the low-side switch during its on-time to output Vcs, and the inductor current generator circuit generates a reconstructed signal during the on-time of the high-side switch, see [0030]-[0031] and [0049] of Su).
Su does not disclose a first delay block to receive said control signal and to generate a delayed control signal by delaying high-to-low transitions of said control signal by said first duration, and an XOR gate to receive said control signal and said delayed control signal and to generate said first pulse.
However, Chen teaches (see Fig. 5, Fig. 7, and Fig. 8) an edge detector (edge detector 604 of Fig. 7 and Fig. 8) of a multi-channel switching converter (see 400 of Fig. 5 of Chen) that generates a blanking pulse (signal Se) by means of an RC delay circuit (700) that delays the pulse-width-modulation signal (PWM1) to produce a delayed signal (PWM1′) and an exclusive-OR (XOR) gate (702) that generates the blanking pulse (Se) according to the modulation signal (PWM1) and the delayed signal (PWM1′) (see Fig. 8 and [0024] of Chen).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator module of Su to comprise a first delay block and an XOR gate to generate said first pulse, as taught by Chen, because it can provide a simple and accurate means of generating a blanking pulse whose width corresponds to said first duration directly from the control signal.
Regarding claim 11, Su does not disclose that said gate driver comprises a second delay block to receive said first pulse and to delay ending edges of said first pulse by said second duration to generate ending edges of said delayed pulse.
However, Wu teaches (see Fig. 5 and Fig. 7 of Wu) that the sensed low-side window comprises a blanking duration (TBlank) followed by a sense duration (TSense), so that the delayed interval extends beyond the blanking interval by the sense duration (see [0025] and [0029] of Wu).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate driver of the voltage regulator module of Su to comprise a second delay block that extends the ending edges of said first pulse by said second duration to generate said delayed pulse, as taught by Wu, because doing so extends the on-time beyond the blanking interval by the sense duration so that a valid current sample can be taken within the sensing window (see [0025] of Wu).
Su does not disclose that said gate driver comprises an OR gate to receive said delayed pulse and a complement of said control signal and to generate said drive signal for said low-side switch.
However, Yang teaches (see Fig. 3 of Yang) that the minimum-on-time pulse (Min_on) is combined into the switch-control path through an OR gate (72) so as to hold the switch on for the pulse duration, the minimum-on-time pulse (Min_on) being applied by way of an AND gate (73) and an inverter (81) to the OR gate (72) that controls the reset of the SR latch (70) and thereby the turn-off of the switch (see [0034] of Yang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate driver of the voltage regulator module of Su to comprise an OR gate that receives said delayed pulse and a complement of said control signal to generate said drive signal for said low-side switch, as taught by Yang, because doing so holds the low-side switch on for at least the delayed pulse duration, thereby guaranteeing a valid inductor current sample each cycle (see [0034] of Yang).
Allowable Subject Matter
Claims 5-7, and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 5, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “…a first capacitor and a second capacitor; a first switch coupled to a first terminal in said pair of terminals and operable to be closed for a duration corresponding to the interval from the end of a blanking phase of said low-side phase to the end of said low-side phase to charge said first capacitor; a second switch coupled to a second terminal in said pair of terminals and operable to be also closed for said duration to charge said second capacitor; a first inverter to receive said first pulse and to generate a first-inverted signal; and an AND gate to receive said second gate drive signal and said first-inverted signal and to generate an un-blank-output signal that controls the opening and closing of said first and second switches.”. Claims 6-7 are objected due to their dependency on claim 5. Regarding Claim 12, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “…a first capacitor and a second capacitor; a first switch coupled to a first terminal in said pair of terminals, and operable to be closed for a duration corresponding to the interval from the end of a blanking phase of said low-side phase to the end of said low-side phase to charge said first capacitor; a second switch coupled to a second terminal in said pair of terminals, and operable to be also closed for a duration corresponding to the interval from the end of said blanking phase of said low-side phase to the end of said low-side phase to charge said second capacitor; a first inverter to receive said first pulse and to generate a first-inverted signal; and an AND gate to receive said second gate drive signal and said first-inverted signal and to generate an un-blank-output signal, wherein said un-blank-output signal is operable to control the opening and closing of said first switch and said second switch such that said sensed-signal is blanked for said first duration and un-blanked upon end of said first duration.”. Claims 13-14 are objected due to their dependency on claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2005/0035748 A1 discloses selective high-side and low-side current sensing in a switching regulator in which the current sense signal having the longer sense window is selected and the initial portion of the sensed signal is masked off to ensure an adequate sensing window. US 2001/0046145 A1 discloses a synchronous buck converter inductor current sensor which senses the voltage drop across the synchronous MOSFET of the half-bridge and reconstructs the current using a sample and hold technique.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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