Prosecution Insights
Last updated: April 19, 2026
Application No. 18/910,114

OPTICAL SENSOR

Non-Final OA §102
Filed
Oct 09, 2024
Examiner
KO, TONY
Art Unit
2878
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lite-On Technology Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
90%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
773 granted / 879 resolved
+19.9% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
16 currently pending
Career history
895
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
26.8%
-13.2% vs TC avg
§102
48.7%
+8.7% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 879 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Singapore on 10/23/2023. It is noted, however, that applicant has not filed a certified copy of the 10202302989V application as required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 7, 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (EP 3745103). Regarding claim 1, Lin et al teach (Figs. 1-4) An optical sensor, comprising: a photodiode (10); and a differential current integrator (20) including a first input terminal (-), a second input terminal (+), a first output terminal (+) and a second output terminal (-), wherein the first input terminal of the differential current integrator is connected to the photodiode (10), and the second input terminal of the differential current integrator is coupled to a first reference voltage (V = I*R, in this case I from current source and R from resistance in the wire). Regarding claim 2, Lin et al teach a first current source (14) connected to the differential current integrator. Regarding claim 3, Lin et al teach the first current source is connected to the first input terminal of the differential current integrator. Regarding claim 4, Lin et al teach a first switch (8) connected between the first current source and the first input terminal of the differential current integrator. Regarding claim 7, Lin et al teach the differential current integrator comprises: an operational amplifier (20) having an inverting input terminal (-), a non-inverting input terminal (+), a first output terminal and a second output terminal, wherein the inverting input terminal is connected to the first input terminal of the differential current integrator, the non-inverting input terminal is connected to the second input terminal of the differential current integrator, the first output terminal of the operational amplifier is connected to the first output terminal of the differential current integrator, and the second output terminal of the operational amplifier is connected to the second output terminal of the differential current integrator; a first integrating capacitor (22a) connected between the first input terminal and the first output terminal of the differential current integrator; and a second integrating capacitor (22b) connected between the second input terminal and the second output terminal of the differential current integrator. Regarding claim 12, Lin et al teach the first current source is connected to the second input terminal of the differential current integrator. Regarding claim 13, Lin et al teach a first switch (8) connected between the first current source (14) and the second input terminal of the differential current integrator. Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizuno (US 20010040212). Regarding claim 1, Mizuno teaches (Figs. 1-7) a photodiode (PD); and a differential current integrator (A0) including a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal (-) of the differential current integrator is connected to the photodiode, and the second input terminal of the differential current integrator is coupled to a first reference voltage (Vref). Regarding claim 8, Mizuno teaches (Fig. 6) a photodiode current switch connected between the photodiode and the first input terminal of the differential current integrator. Allowable Subject Matter Claims 5, 6, 9, 10 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 5, prior art of record does not teach a first voltage comparator, wherein a first input terminal of the first voltage comparator is connected to the second output terminal of the differential current integrator, a second input terminal of the first voltage comparator is connected to the first output terminal of the differential current integrator, a third input terminal of the first voltage comparator is coupled to a second reference voltage, and a fourth input terminal of the first voltage comparator is coupled to a third reference voltage. Regarding claim 9, prior art of record does not teach a first input current source, wherein a first terminal of the first input current source is coupled to a common voltage; and a first power switch, wherein a first terminal of the first power switch is connected to a second terminal of the first input current source, and a second terminal of the first power switch is connected to the first input terminal of the differential current integrator. Regarding claim 11, prior art of record does not teach the differential current integrator comprises: a first reset switch, wherein a first terminal of the first reset switch is connected to the first input terminal of the differential current integrator, and a second terminal of the first reset switch is connected to the second input terminal of the differential current integrator; and a second reset switch, wherein a first terminal of the second reset switch is connected to the first output terminal of the differential current integrator, and a second terminal of the second reset switch is connected to the second output terminal of the differential current integrator. Regarding claim 14, prior art of record does not teach a second switch connected between the first reference voltage and the first input terminal of the differential current integrator. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY KO whose telephone number is (571)272-1926. The examiner can normally be reached Monday-Friday 9-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached at 571-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONY KO/Primary Examiner, Art Unit 2878 TK
Read full office action

Prosecution Timeline

Oct 09, 2024
Application Filed
Feb 25, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
90%
With Interview (+2.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 879 resolved cases by this examiner. Grant probability derived from career allow rate.

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