DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Definitions/Terminology Disclosed in Instant Application (IA) and Dictionary
Acceleration Unit (AU) – modular, operate vector processors, GPUs, AI processor, machine learning processors
Die - A die is the individual semiconductor chip in a package
Interposer Dies - special substrate (passive or semi-active) act as electrical bridge between multiple-semiconductor dies (e.g. CPU, GPU, memory) in a package
Connection Circuitry - actual electrical pathways - wires, vias, pads - that physically and electrically link components (TSV, RDL, BGA)
Compute Dies - active function dies that perform the actual computation or logic in a system
Partition – State of Dividing or being divided into parts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (U.S. Publication 2024/0403254), hereinafter Ma in view of Coudrain et al., Non-Patent Literature/Publication, “Active interposer technology for chiplet-based advanced 3D system architecture”, hereinafter Coudrain.
Referring to claim 1, Dokania teaches, as claimed, an accelerator unit (AU) (a machine learning accelerator, see Paragraph 42; and Fig. 5, 501), comprising:
a connection circuitry (via electrical connection, see Paragraph 30; see Fig. 2, electrical connection 112; and Fig. 3, electrical connection 352);
one or more memory stacks (memory stacks 504a-d, see Paragraph 42; and Fig. 5, 522 and 504a-e) disposed on the connection circuitry; and
one or more interposer dies (interposer 508, see Paragraph 42; and Fig. 5, 550a) disposed on the connection circuitry such that each interposer die of the one or more interposer dies (memory stacks 504a-e are then connected to one of the interposers 550a-d, see Paragraph 42) is communicatively coupled to a corresponding memory (memory stat 504a is connected to IO die 508a via connection 531, see Paragraph 43; Note, when memory is inputting or outputting, it is communicatively coupled via interposer dies) stack of the one or more memory stacks via the connection circuitry, wherein each interposer die of the one or more interposer dies is configured to support a compute die (Compute and IO die 508, see Paragraph 42; and Fig. 5, 508a to 508d).
Ma does not disclose expressly configured to concurrently support two or more compute dies.
Coudrain does disclose configured to concurrently (parallel computing architectures, see Page 1/569, Column 2, Section A) support two or more compute dies (The 3D stack is composed of six identical multiprocessor 22 mm chiplets, see Page 1/569, Section 1; and see Fig. 1, two CPUs, on Page 2/570).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Coudrain’s 3D stack of processors along with Ma’s 3D DRAM chiplets.
The suggestion/motivation for doing so would have been to increase chip-to-chip bandwidth and limits overall power consumption (see Coudrain Page 1/569 Section 1).
As to claim 2, the modification teaches the AU of claim 1, wherein each compute die includes a chiplet (The 3D stack is composed of six identical multiprocessor 22 mm chiplets, see Coudrain Page 1/569, Section 1; and see Fig. 1, two CPUs, on Page 2/570) having one or more compute units.
As to claim 3, the modification teaches the AU of claim 1, wherein an interposer die of the one or more interposer dies is configured to concurrently (parallel computing architectures, see Coudrain Page 1/569, Section A) support a compute die having a first type (still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph) and a compute die having a second type (Benefits of an active interposer, see Coudrain Page 2/570, Section B), wherein the first type is different from the second type.
As to claim 5, the modification teaches the AU of claim 3, wherein the interposer die of the one or more interposer dies includes a first set of circuitry to support the compute die having the first type (still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph; Note, a set of circuitry around passive interposers is implicit) and a second set of circuitry to support the compute die having the second type (Benefits of an active interposer, see Coudrain Page 2/570, Section B; Note, a set of circuitry around active interposers is implicit), wherein the first set of circuitry is different from the second set of circuitry.
As to claim 8, the modification teaches the AU of claim 1, wherein the one or more interposer dies are disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to one or more other interposer dies (interposer 550a-d, see Ma Paragraph 42; and see Ma Fig. 5, 530; Note 530 connects all four interposer dies communicatively coupled to one another).
Referring to claim 9, Dokania teaches, as claimed, a processing system, comprising:
a memory; and
an accelerator unit (AU) (a machine learning accelerator, see Paragraph 42; and Fig. 5, 501), comprising:
a connection circuitry (via electrical connection, see Paragraph 30; see Fig. 2, electrical connection 112; and Fig. 3, electrical connection 352);
one or more memory stacks (memory stacks 504a-d, see Paragraph 42; and Fig. 5, 522 and 504a-e) disposed on the connection circuitry; and
one or more interposer dies (interposer 508, see Paragraph 42; and Fig. 5, 550a) disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled (memory stat 504a is connected to IO die 508a via connection 531, see Paragraph 43; Note, when memory is inputting or outputting, it is communicatively coupled via interposer dies) to a corresponding memory stack (memory stacks 504a, see Paragraph 42; and Fig. 5, 522 and 504a) of the one or more memory stacks via the connection circuitry, wherein each interposer die of the one or more interposer dies is configured to support compute die (Compute and IO die 508, see Paragraph 42; and Fig. 5, 508a to 508d).
Ma does not disclose expressly configured to concurrently support two or more compute dies.
Coudrain does disclose configured to concurrently (parallel computing architectures, see Page 1/569, Column 2, Section A) support two or more compute dies (The 3D stack is composed of six identical multiprocessor 22 mm chiplets, see Page 1/569, Section 1; and see Fig. 1, two CPUs, on Page 2/570).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Coudrain’s 3D stack of processors along with Ma’s 3D DRAM chiplets.
The suggestion/motivation for doing so would have been to increase chip-to-chip bandwidth and limits overall power consumption (see Coudrain Page 1/569 Section 1).
As to claim 10, the modification teaches the processing system of claim 9, wherein an interposer die of the one or more interposer dies includes interconnection circuitry configured to communicatively couple the AU to the memory using a communication protocol (PCIe connection… configured to communicate, see Paragraph 27).
As to claim 11, the modification teaches the processing system of claim 10, wherein the communication protocol comprises peripheral component interconnect express (PCIe) protocols (PCIe connection… configured to communicate, see Paragraph 27).
As to claim 12, the modification teaches the processing system of claim 9, wherein an interposer die is configured to concurrently (parallel computing architectures, see Coudrain Page 1/569, Section A) support a compute die having a first type (still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph) and a compute die having a second type (Benefits of an active interposer, see Coudrain Page 2/570, Section B), wherein the first type is different from the second type.
As to claim 13, the modification teaches the processing system of claim 12, wherein the interposer die of the one or more interposer dies includes a first set of circuitry to support the compute die having the first type (still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph; Note, a set of circuitry around passive interposers is implicit) and a second set of circuitry to support the compute die having the second type (Benefits of an active interposer, see Coudrain Page 2/570, Section B; Note, a set of circuitry around active interposers is implicit), wherein the first set of circuitry is different from the second set of circuitry.
As to claim 14, the modification teaches the processing system of claim 9, wherein the one or more interposer dies are disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to one or more other interposer dies (interposer 550a-d, see Ma Paragraph 42; and see Ma Fig. 5, 530; Note 530 connects all four interposer dies communicatively coupled to one another).
As to claim 15, the modification teaches the processing system of claim 12 wherein the AU includes configured to set one or more partitions of the AU, wherein a partition of the one or more partitions includes at least one compute die of the AU.
Ma/Coudrain does not expressly disclose a set of registers configured to set one more partitions.
Common knowledge discloses memory/registers are used to identify configuration including partitions.
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate existing memory as set of registers to store configuration.
The suggestion/motivation for doing so would have been to better specify functionality of each partition.
Referring to claim 16, Dokania teaches, as claimed an accelerator unit (AU), comprising:
one or more memory stacks (memory stacks 504a-d, see Paragraph 42; and Fig. 5, 522 and 504a-e) disposed on a connection circuitry (via electrical connection, see Paragraph 30; see Fig. 2, electrical connection 112; and Fig. 3, electrical connection 352);
an interposer die (interposer 508, see Paragraph 42; and Fig. 5, 550a) disposed on the connection circuitry such that the interposer die is communicatively coupled to the one or more memory stacks (memory stat 504a is connected to IO die 508a via connection 531, see Paragraph 43; Note, when memory is inputting or outputting, it is communicatively coupled via interposer dies) via the connection circuitry;
one or more compute dies (Compute and IO die 508, see Paragraph 42; and Fig. 5, 508a to 508d) disposed on the interposer die and
a respective memory stack (memory stacks 504a, see Paragraph 42; and Fig. 5, 522 and 504a) of the one or more memory stacks (memory stacks 504a-d, see Paragraph 42; and Fig. 5, 522 and 504a-e).
Ma does not disclose expressly one or more partitions each including a respective compute die of the one or more compute dies and a respective memory stack of the one or more memory stacks.
Coudrain does disclose one or more partitions (Chiplet portioning… first successful technology integration chiplets on an active silicon interposer fully packaged and tested, see Page 1/569 Section 1) each including a respective compute die (one of six identical multiprocessor 22 mm chiplets, see Page 1/569, Section 1; and see Fig. 1, one of two CPUs, on Page 2/570) of the one or more compute dies (The 3D stack is composed of six identical multiprocessor 22 mm chiplets, see Page 1/569, Section 1; and see Fig. 1, two CPUs, on Page 2/570) and a respective memory stack (one of the memories, see Page 1/569, Section A; and see Fig. 1, one of two CPUs, on Page 2/570) of the one or more memory stacks (Stacking high bandwidth memories, see Page 1/569, Section A; and see Fig. 1, two CPUs, on Page 2/570; Note, chiplets includes both compute dies and memory dies).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Coudrain’s partitioning of a single large die in to a multitude of smaller dies.
The suggestion/motivation for doing so would have been to reduce cost and allow for diversity of specializations (see Coudrain Page 2/570 Paragraphs 1 and 2).
As to claim 17, the modification teaches the AU of claim 16.
Ma/Coudrain does not expressly disclose a set of registers configured to set one more partitions.
Common knowledge discloses memory/registers are used to identify configuration including partitions.
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate existing memory as set of registers to store configuration.
The suggestion/motivation for doing so would have been to better specify functionality of each partition.
As to claim 18, the modification teaches the AU of claim 16, wherein the one or more compute dies includes a compute die of a first type still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph) and a compute die of a second type (Benefits of an active interposer, see Coudrain Page 2/570, Section B) that is different from the first type.
As to claim 19, the modification teaches the AU of claim 18, wherein the interposer die includes a first set of circuitry to support the compute die of the first type (still currently integrated onto passive 2.5D interposers, see Coudrain Page 2/570, 4th Paragraph; Note, a set of circuitry around passive interposers is implicit) and a second set of circuitry to support the compute die of the second type, wherein the first set of circuitry is different from the second set of circuitry (Benefits of an active interposer, see Coudrain Page 2/570, Section B; Note, a set of circuitry around active interposers is implicit).
As to claim 20, the modification teaches the AU of claim 16, wherein the interposer die is disposed on the connection circuitry such that the interposer die is communicatively coupled to one or more other interposer dies (interposer 550a-d, see Ma Paragraph 42; and see Ma Fig. 5, 530; Note 530 connects all four interposer dies communicatively coupled to one another).
Allowable Subject Matter
Claims 4 and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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