Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the amendment filed on July 15th 2026. Claims 5 and 15 have been canceled. Claims 1-2, 7, and 13-14 have been amended. The amended claims limitations have been fully considered but are not persuasive. Claims 1-2, 7, and 13-14 remain rejected in the application.
Response to Arguments
Applicant's arguments filed July 15 have been fully considered but they are not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Thom and Jamieson are analogous art in the field of quantum compute.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that Thom; Fig. 6 discloses two nodes coupling only two nodes) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's arguments that Thom does not teach or suggest each variable node indicating a state of each of at least three different quantum bits, Examiner respectfully disagrees. Thom, Figs. 7A-7D and ¶0162, displays a node for each different qubit and its state and, Thom; Fig. 7D and ¶0024, show a node for a variable mapped to a chain of more than seven qubits, as discussed below.
In response to applicant's arguments that Jamieson does not teach or suggest each variable node indicating a state of each of at least three different quantum bits, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. Jamieson is not relied upon in the combination for that teaching, Thom (Figs. 7A-7D, ¶0024, and ¶0162) is, as discussed below. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant’s arguments regarding independent claims 7 and 13: claims 7 and 13 have been amended in a manner similar to claim 1. As the rejection for the independent claim is maintained, the arguments are not persuasive.
In response to applicant’s arguments regarding dependent claims 2-6, 8-12, and 14-19: since the rejection for the independent claim is maintained, the arguments regarding the dependent claims are not persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Thom (US20210263643A1) and Jamieson (US20220215284A1)
Regarding claim 1, Thom teaches a display control device comprising: at least one memory configured to store instructions; and at least one processor configured to execute the instructions to generate data for displaying (Thom; ¶0030, describes the digital computer system including memory and one or more processors and, ¶0031, describes the output including a display.) at least three variable nodes, wherein each variable node indicates a state of each of at least three different quantum bits (Thom; Figs. 7A-D and ¶0162, describes a Quantum Processing Unit (QPU) view or “target graph” where nodes visually represent physical or logical qubits and the edges representing available coupling devices, each node representing a different qubit; (Fig. 7D showing node 1094 and its solution:
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Thom; Fig. 6 and ¶0144, describes nodes in the target or quantum processor graph may use the same or similar visual cues for programmed state and solution states as employed in a source graph, including colors, patterns, shapes, characters and/or icons. Thom; ¶0024 describes a “chain” refers to a set of qubits that are mapped to a single variable and, Thom; Fig. 7D 708b, showing a node for variable CARRY4,2 that has a chain length greater than 7 (at least 3 different quantum bits). This teaches displaying at least three variable nodes, each corresponding to a quantum bit and that each variable node indicates a state of the corresponding quantum bit.)
However, Thom does not expressly disclose a parity node indicating a parity of the at least three quantum bits and edges coupling between each variable nodes and the parity node.
Jamieson teaches a parity node and edges coupling between each variable nodes and the parity node (Jamieson; Fig. 2 and ¶0034-0035, describes an LDPC parity check matrix where each row represents a check node constraint and a Tanner graph with check nodes and bit nodes connected by edges.), the parity node indicating a parity of the at least three quantum bits (¶0056 describes the constraint on LDPC encoding is that a modulo two bit sum at every check node is zero, and, ¶0065, describes a check constraint where [qa, qb, qc] participate in the check node. The parity node indicating a parity of at least three qubits (qa, qb, and qc) with edges coupling the parity node to each associated variable. In the combination, Thom’s graph representation displays Jamieson’s check node (parity node), with displayed edges between the parity node and the displayed variable nodes corresponding to the associated quantum bits.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the quantum processor display of Thom to show the parity relationships as taught by Jamieson. The motivation for such a combination would have been to provide the benefit of improved visualization for analyzing/debugging.
Claim 7, has similar limitations as of claim 1, therefore it is rejected under the same rationale as claim 1, except claim 7 further recites perform a computation on a target problem serving as a target problem addressed by a quantum computer.
Thom; ¶0028, describes a digital computer system coupled and interfaced to an analog computer that may take the form of a quantum computer and the digital computer system to perform tasks including analyzing, debugging, embedding, and modifying problems executed via the analog (quantum) computer system. This teaches performing a computation on a target problem addressed by a quantum computer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the computation system of Thom to display the parity checking as taught by Jamieson (see claim 1). The motivation for such a combination would have been to provide the benefit of improved visualization for analyzing/debugging.
Claim 13, has similar limitations as of claim 1, therefore it is rejected under the same rationale as claim 1.
Regarding claim 2, Thom in view of Jamieson teaches the display control device according to claim 1, wherein the at least one processor is configured to execute the instructions to generate the data for displaying variable nodes each indicating a state of a plurality of quantum bits in a target problem addressed by a quantum computer, and the at least three different quantum bits are included in the plurality of quantum bits (Thom; ¶0162, describes a QPU with nodes representing respective physical or logical qubits of a quantum processor in which the problem is embedded, ¶0154, describes the presentation may tie target variables to physical qubits, and, ¶0169, a corresponding node in the target graph (QPU view) represents a qubit or coupler assigned to represent the variable. This teaches displaying nodes (including the at least three different quantum bits in claim 1) indicating states of quantum bits in a target problem addressed by a quantum computer.)
Claim 14, has similar limitations as of claim 2, therefore it is rejected under the same rationale as claim 2.
Regarding claim 3, Thom in view of Jamieson teaches the display control device according to claim 2, wherein the at least one processor is configured to execute the instructions to generate the data for displaying a graph showing a physical problem, which is the target problem, converted so as to be implementable in a quantum computer (Thom; ¶0156, describes a second graph panel presents a target graph where nodes represent respective qubits in an embedding formulation of a problem and a solution. This teaches displaying a graph showing the target problem after conversion into a form implementable in a quantum computer.)
Claim 9, has similar limitations as of claim 3, therefore it is rejected under the same rationale as claim 3.
Claim 16, has similar limitations as of claim 3, therefore it is rejected under the same rationale as claim 3.
Regarding claim 4, Thom in view of Jamieson teaches the display control device according to claim 2, wherein the at least one processor is configured to execute the instructions to generate the data for displaying a graph showing a logical problem, which is the target problem, before being converted so as to be implementable in a quantum computer (Thom; ¶0156, describes a first graph panel presents a source graph where nodes represent respective variables in a logical problem formulation of a problem and solution. This teaches displaying a graph showing the logical problem before conversion into an embedding formulation implementable in a quantum computer.)
Claim 10, has similar limitations as of claim 4, therefore it is rejected under the same rationale as claim 4.
Claim 17, has similar limitations as of claim 4, therefore it is rejected under the same rationale as claim 4.
Regarding claim 5, Thom in view of Jamierson teaches the display control device according to claim 3, wherein the at least one processor is configured to execute the instructions to generate the data for displaying a graph representing the physical problem such that the graph shows a correspondence between physical bits, which are quantum bits used in the physical problem, and logical bits, which are quantum bits used in a logical problem serving as the target problem before being converted to the physical problem, in a representation method in which representation methods assigned to the logical bits are combined (As previously described in claim 2, Thom; ¶0162, describes a QPU with nodes representing respective physical or logical qubits of a quantum processor in which the problem is embedded, ¶0154, describes the presentation may tie target variables to physical qubits, and, ¶0169, a corresponding node in the target graph (QPU view) represents a qubit or coupler assigned to represent the variable. Thom; ¶0024, describes a chain, which is a set of physical qubits mapped to a single logical variable. This teaches physical qubits in the target graph may correspond to a single logical variable.)
Claim 11, has similar limitations as of claim 5, therefore it is rejected under the same rationale as claim 5.
Claim 18, has similar limitations as of claim 5, therefore it is rejected under the same rationale as claim 5.
Regarding claim 6, Thom in view of Jamieson teaches the display control device according to claim 1, wherein the at least one processor is configured to execute the instructions to generate the data for switchably displaying a plurality of combinations of values of the quantum bits corresponding to one value of the parity node, in association with each of the variable nodes (Thom; ¶00155, describes the plot of solutions is user selectable and the system automatically updates the graph representation in response to user selection. The display of solution information (associated with the displayed nodes) is switchable. As previously discussed in claim 1, Jamieson; ¶0056, describes multiple combinations of qubit values can satisfy the same check node constraint. Jamieson; ¶0070 describes the processor identifies and ranks multiple solutions, reads on displaying a plurality of different quantum bit value combinations. In the combination, this teaches switchably displaying in association with the variable nodes, a plurality of quantum bit value combinations corresponding to a parity node.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the quantum processor display of Thom to switchably display the qubit value combinations of Jamieson. The motivation for such a combination would have been to provide the benefit of improved visualization for analyzing/debugging.
Regarding claim 8, Thom in view of Jamieson teaches the computing system according to claim 7, wherein the at least one processor is configured to execute the instructions to generate the data for displaying a graph such that setting values for the variable nodes and setting values for the parity nodes in the target problem are both represented by color, shading, or a combination thereof, and values of quantum bits indicated by the variable nodes and parities indicated by the parity nodes are both represented by an orientation of icons indicating nodes (Thom; ¶0105, describes that each icon that represents a node or an associated qubit may include an indication of a programmed bias state using a set of colors to represent each of the different possible bias states, each icon may include an indication of a read-out solution state using a set of colors to represent different possible solution states, and the nodes may be represented by icons with visual indications of both programmed and solution states. This teaches that setting values for nodes are represented by color and that values indicated by the nodes are represented by an orientation of icons indicating nodes.)
Claim 15, has similar limitations as of claim 8, therefore it is rejected under the same rationale as claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAN F KALHORI whose telephone number is (571)272-5475. The examiner can normally be reached Mon-Fri 8:30-5:30 ET.
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/DAN F KALHORI/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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