Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-7 and 16-20 are presented for examination.
Election/Restriction
3. Applicant’s election without traverse of Species 1 (claims 1-7 and 16-20) is acknowledged.
4. Therefore, claims 8-15 are withdrawn from further consideration.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
6. Claims 1-7 and 16-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-5 or 8-12 of U.S. Patent No. 11756594. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1 and 3-7 of the examined application are anticipated and the same scope of invention by claims 1-5 or 8-12 of the reference such as a memory device comprising: an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; a plurality of data lines, each data line of the plurality of data lines connected to a respective subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells via respective select gates of a plurality of select gates; a plurality of select lines, each select line of the plurality of select lines connected to a control gate of a respective select gate of the plurality of select gates for a respective subset of the plurality of select gates; and control logic configured to: open the array of memory cells for multiple read operations; bias a first select line of the plurality of select lines to connect via respective select gates of the plurality of select gates each data line of the plurality of data lines to a respective first string of series-connected memory cells of the plurality of strings of series-connected memory cells; read first page data from respective memory cells coupled to a first selected access line of the plurality of access lines for the respective first strings of series-connected memory cells; and read second page data from the respective memory cells coupled to the first selected access line for the respective first strings of series-connected memory cells without closing the array of memory cells following the reading of the first page data.
The claim 2 of examined application are obvious over the claims of reference because the claim 1 or 8 seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites read second page data from the respective memory cells coupled to the second selected access line for the respective first strings of series-connected memory cells without closing the array of memory cells following the reading of the first page data from the respective memory cells coupled to the second selected access line while in the reference was silence. However, a claim 14 of Zang (US Pub. 20210202011) discloses these limitation.
Claims 16-20 of the examined application are anticipated and the same scope of invention by claims 1-5 or 8-12 of the reference such as a memory device comprising: an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; a plurality of data lines, each data line of the plurality of data lines connected to a respective subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells via respective select gates of a plurality of select gates; a plurality of select lines, each select line of the plurality of select lines connected to a control gate of a respective select gate of the plurality of select gates for a respective subset of the plurality of select gates; and control logic configured to: open the array of memory cells for multiple read operations; bias a first select line of the plurality of select lines to connect via respective select gates of the plurality of select gates each data line of the plurality of data lines to a respective first string of series-connected memory cells of the plurality of strings of series-connected memory cells; read first page data from respective memory cells coupled to a first selected access line of the plurality of access lines for the respective first strings of series-connected memory cells; and read first page data from respective memory cells coupled to a second selected access line of the plurality of access lines for the respective first strings of series-connected memory cells without closing the array of memory cells following the reading of the first page data from the respective memory cells coupled to the first selected access line.
The claim 16 of examined application are obvious over the claims of reference because the claim 1 or 8 seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites read first page data from respective memory cells coupled to a second selected access line of the plurality of access lines for the respective first strings of series-connected memory cells without closing the array of memory cells following the reading of the first page data from the respective memory cells coupled to the first selected access line while in the reference was silence. However, a claim 14 of Zang (US Pub. 20210202011) discloses these limitation.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1- 7 and 16-20 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Zang et al. US Pub. No. 20210202011.
As per claims 1 and 3, a claim 1 and Fig. 1 of Zang are directed to a memory device comprising: an array of memory cells comprising a plurality of strings of series-connected memory cells (par. 20); a plurality of access lines (401 and 411 of Fig. 4), each access line of the plurality of access lines connected to a control gate (CG) of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; a plurality of data lines (I/Ox of Fig. 2), each data line of the plurality of data lines connected to a respective subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells via respective select gates of a plurality of select gates (claim 14); a plurality of select lines (413 and 419 of Fig. 4 or claims 4 and 5), each select line of the plurality of select lines connected to a control gate of a respective select gate of the plurality of select gates for a respective subset of the plurality of select gates (413 and 419 of Fig. 4 or claims 4 and 5); and control logic (702 of Fig. 7 or claim 14) configured to: open the array of memory cells for multiple read operations (Fig. 1); bias a first select line of the plurality of select lines to connect via respective select gates of the plurality of select gates each data line of the plurality of data lines to a respective first string (block in claim 1) of series-connected memory cells of the plurality of strings of series-connected memory cells (103); read first page data (103) from respective memory cells coupled to a first selected access line (103 by ) of the plurality of access lines for the respective first strings of series-connected memory cells; and read second page data (109) from the respective memory cells coupled to the first selected access line for the respective first strings of series-connected memory cells without closing (claim 2) the array of memory cells following the reading of the first page data (101 or 113).
As per claim 2, a claim 14 of Zang discloses wherein the control logic is configured to: read first page data from respective memory cells coupled to a second selected access line (second address in claim 14) of the plurality of access lines for the respective first strings of series-connected memory cells without closing (sequential in claim 14) the array of memory cells following the reading of the second page data from the respective memory cells coupled to the first selected access line; and read second page data from the respective memory cells coupled to the second selected access line for the respective first strings of series-connected memory cells without closing (sequential in claim 14) the array of memory cells following the reading of the first page data from the respective memory cells coupled to the second selected access line.
As per claim 16, the rejection of claim 16 is the same rejections of claims 1-2.
As per claims 4 and 17, Fig. 4 or 5 of Zang discloses wherein the control logic is configured to open the array of memory cells for multiple read operations (Fig. 1) by: ramping up each access line (401, par. 64) of the plurality of access lines from a reference voltage to a voltage sufficient to activate each respective memory cell coupled to each access line of the plurality of access lines; and ramping up each select line (417, par. 61)of the plurality of select lines from the reference voltage to a voltage sufficient to activate each respective select gate coupled to each select line of the plurality of select lines.
As per claims 5 and 18, Fig. 1 of Zang discloses wherein the control logic is configured to close (113, par. 49) the array of memory cells once all page data is read from respective memory cells coupled to each access line of the plurality of access lines for each string of series-connected memory cells of the plurality of strings of series-connected memory cells.
As per claims 6 and 19, Fig. 4 or 5 of Zang discloses wherein the control logic is configured to close (113 of Fig. 1) the array of memory cells by: ramping up each access line of the plurality of access lines to a voltage sufficient to activate each respective memory cell coupled to each access line of the plurality of access lines (before 401 ramping down to 0V) followed by ramping down each access line of the plurality of access lines to a reference voltage (0V); and ramping up each select line of the plurality of select lines (before 413 and 417 ramping down to 0V) to a voltage sufficient to activate each respective select gate coupled to each select line of the plurality of select lines followed by ramping down (ramping to 0V) each select line of the plurality of select lines down to the reference voltage.
As per claims 7 and 20, a paragraph 80 and a claim 14 of Zang discloses wherein the array of memory cells comprises a three-dimensional (3D) NAND memory array (claim 14).
10. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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