Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 09 October 2024 for application number 18/910,571. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 08 November 2023 (KR10-2023-0153994).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09 October 2024 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 13, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dellow et al. [hereafter as Dellow], US Pub. No. 2008/0271164 A1 in view of Merry et al. [hereafter as Merry], US Patent No. 7,509,441 B1.
As per claim 1, Dellow discloses a storage device comprising:
a memory [“a one-time-programmable (OTP) memory”] [Abstract]; and
a memory controller configured to control the memory [“The SoC 100 may comprise at least one memory controller (MC) 106”] [para. 0017],
wherein the memory controller includes a one-time programmable (OTP) module, the OTP module including a hardware area and being configured to store, in the hardware area, a logic bit indicating an initial operation restriction state of an instruction code [“Access to the restricted function portion or the remaining portion of the ROM may be based on at least one bit from the OTP memory.”] [para. 0016] [“The OTP 304 may comprise suitable logic, circuitry, and/or code that may enable storage of at least one bit that may be utilize to control portions of the operation of the secure multimedia SoC 300.”] [para.0030], and
wherein the memory controller is configured to output an operation restriction state of a command based on a state table [bit] corresponding to the instruction code [“The OTP 304 may comprise suitable logic, circuitry, and/or code that may enable storage of at least one bit that may be utilize to control portions of the operation of the secure multimedia SoC 300.”] [para.0030].
However, Dellow does not explicitly discloses an operation restriction state of a vendor unique command (VUC).
Merry teaches an operation restriction state of a vendor unique command (VUC) [“Dividing the NVM array 116 into different zones advantageously allows each zone to implement different vendor-specific commands including, but not limited to, commands that control access or security levels for a particular zone. Thus, vendor-specific commands such as a fast erasure of data command described in copending U.S. application Ser. No. 11/000,134, filed on Nov. 30, 2004, can be implemented on a zone-by-zone basis.”] [col. 5, lines 1-8].
Dellow and Merry are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Dellow with Merry in order to modify Dellow for “an operation restriction state of a vendor unique command (VUC)” as taught by Merry. One of ordinary skill in the art would be motivated to combine Dellow with Merry before the effective filing date of the claimed invention to improve a system by where it “would be advantageous to develop a technique and system for segmenting a storage subsystem into multiple segments (or zones) such that a separate set of security or access parameters can be associated with each zone and each zone can implement different vendor-specific commands.” [Merry, col. 1, lines 37-41].
As per claim 2, Dellow in view of Merry discloses the storage device of claim 1, Dellow discloses wherein the memory controller is further configured to set the state table based on the logic bit [“When the security processor 102 accesses the ROM 130 to fetch the appropriate code or instructions to initiate the boot up process, the programmed bit or bits in the OTP 304 may restrict which portion of the ROM 130 is accessed.”] [para. 0032] [Examiner is interpreting the programmed bit or bits as the state table].
As per claim 3, Dellow in view of Merry discloses the storage device of claim 2, Dellow discloses wherein the memory controller is further configured to read the logic bit stored in the hardware area of the OTP module [“The OTP 304 may comprise suitable logic, circuitry, and/or code that may enable storage of at least one bit that may be utilize to control portions of the operation of the secure multimedia SoC 300. In this regard, at least one bit in the OTP 304 may be utilized to determine whether the security processor 102 may access the first portion 130a or the second portion 130b of the ROM 130. For example, a single bit in the OTP 304 may be utilized to enable access to half of the storage addresses in the ROM 130 by the security processor 102 via an address bus...”] [para. 0030].
As per claim 4, Dellow in view of Merry discloses the storage device of claim 1, Merry teaches wherein the memory controller is further configured to extract the VUC from data received from a host [“a host system using the storage subsystem determines whether access to a particular area of the memory array on the storage subsystem is consistent with defined segment parameters. For example, the host system reads the segment definitions and the associated segment parameters and a controller in the host system determines whether access to the memory array is consistent with the defined segments and associated parameters.”] [col. 2, lines 15-22] [“Dividing the NVM array 116 into different zones advantageously allows each zone to implement different vendor-specific commands including, but not limited to, commands that control access or security levels for a particular zone. Thus, vendor-specific commands such as a fast erasure of data command described in copending U.S. application Ser. No. 11/000,134, filed on Nov. 30, 2004, can be implemented on a zone-by-zone basis.”] [col. 5, lines 1-8].
Claim 13 is rejected with like reasoning as claims 1 – 4 above.
Claim 14 is rejected with like reasoning as claim 3 above.
Claim 19 is rejected with like reasoning as claim 13 above.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dellow et al. [hereafter as Dellow], US Pub. No. 2008/0271164 A1 in view of Merry et al. [hereafter as Merry], US Patent No. 7,509,441 B1 as applied to claim 4 above, and further in view of Moore et al. [hereafter as Moore], US Pub. No. 2013/007324 A1.
As per claim 5, Dellow in view of Merry discloses the storage device of claim 4, however Dellow and Merry do not explicitly disclose wherein the memory controller is configured to not perform an operation according to the VUC based on the operation restriction state of the VUC being a lock state.
Moore teaches wherein the memory controller is configured to not perform an operation according to the VUC based on the operation restriction state of the VUC being a lock state [“if no data or requests are pending, the host signals to the function endpoints or sends over the control endpoint 0 a class specific or vendor specific command that includes addresses for the function interface or endpoints. The power management module changes the state of the function to locked if data or requests are pending at the time of the receipt of a suspend request and no Activity Indications have been received since the last resume.”] [para. 0038].
Dellow, Merry, and Moore are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Dellow and Merry with Moore in order to modify Dellow and Merry “wherein the memory controller is configured to not perform an operation according to the VUC based on the operation restriction state of the VUC being a lock state” as taught by Moore. One of ordinary skill in the art would be motivated to combine Dellow and Merry with Moore before the effective filing date of the claimed invention to improve a system for the “inclusion of the locked and indefinite states in the state machines is for efficiency.” [Moore, para. 0047].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 4, 13, 14, and 19 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 6, 15, and 20 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to include all of the limitations of the base claim and any intervening claims in independent form. Claims 7 – 12 and 16 – 18 depend from claims 6 and 15 and are subsequently objected to as considered containing allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 6 and 15 the prior art of record, neither anticipates, nor renders obvious controlling whether the state table is changeable. Claims 7 – 12 and 16 – 18 depend from claims 6 and 15 and would be allowable based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 20 the prior art of record, neither anticipates, nor renders obvious the storage device is configured to set the state table as changeable based on a result of determining whether the host device is a legitimate device.
The prior art made of record and not relied upon considered pertinent to applicant's disclosure.
Matthew et al., US Pub. No. 2020/0341775 A1 – teaches “The memory command may be a read command that causes the control circuitry of the memory module 100 to read contents of vendor-specific register and/or a write command that causes the control circuitry of the memory module 100 to configure a vendor-specific register to enable and/or disable a vendor-specific functionality on the memory module 100.” [para. 0054]
Strong et al., US Patent No. 10,523,444 B2 – teaches “A memory device comprising a controller and a storage memory, wherein the controller includes a processor and a controller memory operably coupled to the processor, and wherein: the controller is configured to receive a command and control (C.sup.2) packet from a remote computer, the C.sup.2 packet including— a command for the controller to change a permission status of a restricted command, and a vendor signature, wherein the restricted command is a command to access a restricted memory region, a command to modify firmware of the memory device, a command to overclock the memory device, a command to enable a test mode of the memory device, a command to format the storage memory, and/or a command to disable an enabled command; and the controller memory stores instructions executable by the processor to— determine if the vendor signature is valid, and direct the controller to execute the command to change the permission status of the restricted command if the vendor signature is determined to be valid.” [claim 1]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EW/Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135