Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–4, 6, 10, 11, 13–15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE(US11359973B2) in view of COLE(US6097031A).
Regarding claim 1, Lee discloses A sensing substrate(MEMS device 100 including a sensor substrate 102; Lee ¶ [0036]), comprising:
a first substrate(lower substrate 110; Lee ¶ [0048]);
a circuit layer disposed on the first substrate(a readout integrated circuit (ROIC) formed at the lower substrate 110, together with metal pad 113 electrically connected to the ROIC; Lee ¶¶ [0048], [0052]–[0053]);
a planarization layer disposed on the circuit layer(insulating layer 111 disposed on the lower substrate 110 on which the ROIC is formed; Lee ¶ [0048]),
wherein the planarization layer comprises an opening(a contact through insulating layer 111 by which the metal pad 113 is electrically connected to the ROIC; Lee ¶¶ [0048], [0053]);
a sensing unit disposed on the planarization layer(infrared sensor 103, including absorption plate 115 supported over insulating layer 111 by anchor 118; Lee ¶¶ [0038], [0052]),
wherein the sensing unit is electrically connected to the circuit layer through the opening(the anchor 118 electrically connects the absorption plate 115 to metal pad 113, which is connected to the ROIC through the opening in insulating layer 111; Lee ¶¶ [0052]–[0053], [0063]); and
a first bonding layer disposed on the planarization layer(lower bonding pad 116 disposed on insulating layer 111; Lee ¶ [0050]).
Lee does not explicitly disclose that its insulating layer 111 is a planarization layer, or that the electrical connection of the sensing unit to the circuit layer passes through an opening in that planarization layer.
However, Cole teaches a planarization layer 13 formed over the substrate electronics, the planarization layer having a via 14 formed therein through which a contact 15 electrically connects the overlying infrared detecting pixel to the substrate electronics (Cole, FIG. 1a; "A via 14 is formed in planarization layer 13 for a contact 15 into substrate 11").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Lee's insulating layer 111 as a planarization layer having an opening through which the sensing unit is electrically connected to the underlying circuit, as taught by Cole, in order to provide a substantially flat surface over the underlying circuitry on which to build the suspended infrared sensor and the bonding layer while defining a vertical electrical interconnect between the sensor and the substrate readout electronics.
Regarding claim 2/1, Lee in view of Cole teaches the sensing substrate as claimed in claim 1.
Lee further discloses wherein the sensing unit and the first bonding layer are located on the same side of the planarization layer(both the infrared sensor 103 and the lower bonding pad 116 are formed on the upper side of the lower substrate 110 / insulating layer 111; Lee ¶¶ [0050], [0052]).
Regarding claim 3/1, Lee in view of Cole teaches the sensing substrate as claimed in claim 1.
Lee discloses wherein the sensing unit comprises: an absorbing layer(absorbing layer 115b; Lee ¶ [0058]);
a first insulating layer and a second insulating layer disposed on the absorbing layer(first insulating layer 115a and second insulating layer 115d disposed on either side of the absorbing layer 115b; Lee ¶¶ [0058], [0128]); and
a sensing layer disposed between the first insulating layer and the second insulating layer(resistive layer 115c, disposed between insulating layers 115a and 115d; Lee ¶¶ [0058], [0061]).
Regarding claim 4/3, Lee in view of Cole teaches the sensing substrate as claimed in claim 3.
Lee discloses wherein the sensing unit further comprises a supporting element disposed between the planarization layer and the absorbing layer(anchor 118, formed of titanium nitride (TiN) or Ti/TiN/W, disposed between insulating layer 111 and the absorption plate 115 and supporting the absorption plate; Lee ¶¶ [0063]–[0064]).
Regarding claim 6/1, Lee in view of Cole teaches the sensing substrate as claimed in claim 1.
Lee discloses wherein the first bonding layer surrounds the sensing unit(lower bonding pad 116 disposed to surround the infrared sensor 103; Lee ¶¶ [0038], [0050]).
Regarding claim 10, Lee discloses A sensing device(MEMS device 100; Lee ¶ [0036]), comprising:
a sensing substrate, comprising:
a first substrate(lower substrate 110; Lee ¶ [0048]);
a circuit layer disposed on the first substrate(a readout integrated circuit (ROIC) formed at the lower substrate 110, together with metal pad 113 electrically connected to the ROIC; Lee ¶¶ [0048], [0052]–[0053]);
a planarization layer disposed on the circuit layer, wherein the planarization layer comprises an opening(insulating layer 111 disposed on the lower substrate 110 on which the ROIC is formed, having a contact through which metal pad 113 is electrically connected to the ROIC; Lee ¶¶ [0048], [0053]);
a sensing unit disposed on the planarization layer, wherein the sensing unit is electrically connected to the circuit layer through the opening(infrared sensor 103, including absorption plate 115 supported over insulating layer 111 by anchor 118, the anchor electrically connecting the absorption plate 115 to metal pad 113 and thus to the ROIC; Lee ¶¶ [0038], [0052]–[0053], [0063]); and
a first bonding layer disposed on the planarization layer(lower bonding pad 116 disposed on insulating layer 111; Lee ¶ [0050]); and
an optical substrate comprising a second substrate and a second bonding layer disposed on the second substrate(cap substrate 101, including upper substrate 120 and upper bonding pad 182 disposed on partition wall 180 of the upper substrate; Lee ¶¶ [0037], [0044]);
wherein the optical substrate and the sensing substrate are bonded to each other through the first bonding layer and the second bonding layer(lower bonding pad 116 and upper bonding pad 182 are eutectic-bonded to each other to seal cavity 104; Lee ¶¶ [0044], [0050]).
Lee does not explicitly disclose that its insulating layer 111 is a planarization layer, or that the electrical connection of the sensing unit to the circuit layer passes through an opening in that planarization layer.
However, Cole teaches a planarization layer 13 formed over the substrate electronics, the planarization layer having a via 14 formed therein through which a contact 15 electrically connects the overlying infrared detecting pixel to the substrate electronics (Cole, FIG. 1a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Lee's insulating layer 111 as a planarization layer having an opening through which the sensing unit is electrically connected to the underlying circuit, as taught by Cole, in order to provide a substantially flat surface over the underlying circuitry on which to build the suspended infrared sensor and the bonding layer while defining a vertical electrical interconnect between the sensor and the substrate readout electronics.
Regarding claim 11/10, Lee in view of Cole teaches the sensing device as claimed in claim 10.
Lee discloses wherein the first bonding layer and the second bonding layer undergo a melting reaction to form a bonding structure, and the bonding structure comprises Cu3Sn, Au5Sn or gold(the lower and upper bonding pads 116/182 are each an alloy of gold (Au), indium (In), copper (Cu), and tin (Sn) that perform eutectic bonding; Lee ¶¶ [0044], [0050]).
Regarding claim 13/10, Lee in view of Cole teaches the sensing device as claimed in claim 10.
Lee discloses wherein the optical substrate comprises a recess and the recess overlaps the sensing unit(cavity region 150 depressed in the lower surface of upper substrate 120, with the infrared sensor 103 disposed to face the cavity region 150; Lee ¶¶ [0038], [0041]).
Regarding claim 14/10, Lee in view of Cole teaches the sensing device as claimed in claim 10.
Lee discloses wherein the first bonding layer and the second bonding layer are bonded to each other to form a cavity in the sensing device(the bonding pads 116/182 are bonded to seal cavity 104, maintained in a vacuum state; Lee ¶¶ [0039], [0050]).
Regarding claim 15, Lee discloses A method of manufacturing a sensing device(method of manufacturing MEMS device 100/300; Lee ¶¶ [0068], [0113]), comprising:
providing a sensing substrate, comprising: providing a first substrate(providing lower substrate 110; Lee ¶¶ [0069], [0071]);
forming a circuit layer on the first substrate(forming the ROIC and metal pad 113 at/on the lower substrate 110; Lee ¶¶ [0071]–[0072]);
forming a planarization layer on the circuit layer, wherein the planarization layer comprises a first opening(forming insulating layer 111 on the lower substrate 110 on which the ROIC is formed, the insulating layer having a contact through which metal pad 113 is connected to the ROIC; Lee ¶¶ [0071], [0118]);
forming a sensing unit on the planarization layer, wherein the sensing unit is electrically connected to the circuit layer through the first opening(forming infrared sensor 103 including anchor 118 electrically connecting absorption plate 115 to metal pad 113 and thus to the ROIC; Lee ¶¶ [0063], [0068]); and
forming a first bonding layer on the planarization layer(forming lower bonding pad 116 on insulating layer 111; Lee ¶ [0050]).
Lee does not explicitly disclose that its insulating layer 111 is a planarization layer, or that the sensing unit is electrically connected to the circuit layer through a first opening in that planarization layer.
However, Cole teaches a planarization layer 13 formed over the substrate electronics, the planarization layer having a via 14 formed therein through which a contact 15 electrically connects the overlying infrared detecting pixel to the substrate electronics (Cole, FIG. 1a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Lee's insulating layer 111 as a planarization layer having a first opening through which the sensing unit is electrically connected to the underlying circuit, as taught by Cole, in order to provide a substantially flat surface over the underlying circuitry on which to form the suspended infrared sensor and the bonding layer while defining a vertical electrical interconnect between the sensor and the substrate readout electronics.
Regarding claim 19/15, Lee in view of Cole teaches the method of manufacturing a sensing device as claimed in claim 15.
Lee discloses further comprising: providing an optical substrate, comprising: providing a second substrate; and forming a second bonding layer on the second substrate(providing upper substrate 120 and forming upper bonding pad 182 thereon; Lee ¶¶ [0037], [0044]).
Regarding claim 20/19, , Lee in view of Cole teaches the method of manufacturing a sensing device as claimed in claim 15.
Lee discloses further comprising melting the first bonding layer and the second bonding layer through a bonding process to bond the sensing substrate to the optical substrate(eutectic bonding, by heating, of the lower and upper bonding pads 116/182 to bond sensor substrate 102 to cap substrate 101; Lee ¶¶ [0044], [0050]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over LEE(US11359973B2) in view of COLE(US6097031A), and further in view of GOOCH(US9227839B2).
Regarding claim 12, Lee discloses A sensing device(MEMS device 100; Lee ¶ [0036]) comprising:
a sensing substrate, comprising a first substrate(lower substrate 110; Lee ¶ [0048]),
a circuit layer(ROIC and metal pad 113 at the lower substrate 110; Lee ¶¶ [0048], [0052]–[0053]),
a planarization layer comprising an opening(insulating layer 111 having a contact through which metal pad 113 is connected to the ROIC; Lee ¶¶ [0048], [0053]),
a sensing unit electrically connected to the circuit layer through the opening (infrared sensor 103, with anchor 118 connecting absorption plate 115 to metal pad 113; Lee ¶¶ [0052]–[0053], [0063]),
and a first bonding layer(lower bonding pad 116 on insulating layer 111; Lee ¶ [0050]);
and an optical substrate comprising a second substrate and a second bonding layer disposed on the second substrate(cap substrate 101, including upper substrate 120 and upper bonding pad 182 on partition wall 180; Lee ¶¶ [0037], [0044]), the optical substrate and the sensing substrate being bonded to each other through the lower bonding pad 116 and the upper bonding pad 182 to seal cavity 104 (Lee ¶¶ [0044], [0050]).
Lee does not explicitly disclose that its insulating layer 111 is a planarization layer, or that the electrical connection of the sensing unit to the circuit layer passes through an opening in that planarization layer.
However, Cole teaches a planarization layer 13 formed over the substrate electronics, the planarization layer having a via 14 formed therein through which a contact 15 electrically connects the overlying infrared detecting pixel to the substrate electronics (Cole, FIG. 1a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Lee's insulating layer 111 as a planarization layer having an opening through which the sensing unit is electrically connected to the underlying circuit, as taught by Cole, in order to provide a substantially flat surface over the underlying circuitry on which to build the suspended infrared sensor and the bonding layer while defining a vertical electrical interconnect between the sensor and the substrate readout electronics
Lee in view of Cole does not disclose wherein the optical substrate further comprises an anti-reflective layer, and the anti-reflective layer is disposed on a surface of the second substrate.
However, Gooch teaches an anti-reflective coating (ARC) layer 50 disposed on a surface of the cover wafer 16, wherein such coatings are provided to reduce the reflective properties and increase the infrared transmission properties of the lid (Gooch ¶¶ [0009], [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an anti-reflective layer on a surface of Lee's upper substrate 120, as taught by Gooch, in order to reduce reflectivity and increase infrared transmission through the optical window, thereby increasing the infrared radiation reaching the sensor and improving the sensitivity of the sensing device.
Allowable Subject Matter
Claims 5, 7, 8, 9, 16, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5/4/3/1, the prior art of record does not teach the limitation, “wherein the sensing unit further comprises a fixing element disposed in an opening of the supporting element”, in combination of the limitations of the base claim and the intervening claims.
Regarding claim 7/1, the prior art of record does not teach the limitation, “wherein the first bonding layer comprises a first seed layer and a first metal layer disposed on the first seed layer”, in combination of the limitations of the base claim and the intervening claims.
Claims 8 and 9 are objected to for being dependent on claim 7.
Regarding claim 16/15, the prior art of record does not teach the limitation, “wherein the step of forming the sensing unit on the planarization layer comprises: forming a first sacrificial layer on the planarization layer; forming a supporting element on the first sacrificial layer; forming a second sacrificial layer on the supporting element; forming an absorbing layer on the second sacrificial layer; forming a first insulating layer on the absorbing layer; forming a sensing layer on the first insulating layer; and forming a second insulating layer on the sensing layer”, in combination of the limitations of the base claim and the intervening claims.
Claim 17 is objected to for being dependent on claim 16.
Regarding claim 18/15, the prior art of record does not teach the limitation, “wherein the step of forming the first bonding layer on the planarization layer comprises: forming a first seed layer on the planarization layer; forming a protective layer on the first seed layer; removing a portion of the protective layer to form a second opening, wherein the second opening exposes the first seed layer; forming a first metal layer in the second opening; and removing the protective layer”, in combination of the limitations of the base claim and the intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure.
Schweikert(US9741591B2) — teaches wafer-level packaging of microbolometer vacuum package assemblies, disclosing solder-ring reflow bonding, an anti-reflective coating on the lid windows, and a getter.
Lida(US20010028035A1) — teaches uncooled infrared sensor pixel structure disclosing a leg-like support member supporting the infrared detector in a cavity and a sacrificial-film support-formation process.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED QURESHI whose telephone number is (571)-272-8310. The examiner can normally be reached on 8:30 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tulsidas Patel can be reached on 571-272-2098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect. uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/MOHAMMED AHMED QURESHI/Examiner, Art Unit 2834
/TULSIDAS C PATEL/Supervisory Patent Examiner, Art Unit 2834
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