Prosecution Insights
Last updated: July 17, 2026
Application No. 18/910,731

GENERATION OF A MATRIX

Non-Final OA §101§102
Filed
Oct 09, 2024
Priority
Oct 20, 2023 — FR 2311368
Examiner
AHSAN, SYED M
Art Unit
2491
Tech Center
2400 — Computer Networks
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
1y 7m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
212 granted / 288 resolved
+15.6% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
21 currently pending
Career history
323
Total Applications
across all art units

Statute-Specific Performance

§101
4.1%
-35.9% vs TC avg
§103
82.3%
+42.3% vs TC avg
§102
9.2%
-30.8% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 288 resolved cases

Office Action

§101 §102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority This application claims the priority benefit of French patent application number FR2311368, filed on Oct. 20, 2023, entitled “Génération d'une matrice”, which is hereby incorporated by reference. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/09/2024 was filed along with the mailing date of the Non-Provisional Patent Application on 10/09/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. DETAILED ACTION This Office Action is in response to a Requirement for Restriction/Election sent on 03/19/2026. In response Applicant has amended claims 3, 12-14, and 17-20 to recite subject matter which removes the Restriction requirement. The amended claims recite subject matter which aligns to same concept. Claims 1-2, 4-11, and 15-16 remain original. In the response received on 05/19/2026, claims 1-20 have been received for consideration and have been examined. Specification Applicant’s submitted specification has been reviewed and found to be in compliance. Drawings Applicant’s submitted drawings have been reviewed and found to be in compliance. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more analyzed according to MPEP 2106. Step 1: The independent claims 1, 12, and 17 do fall into one of the four statutory categories of “a method” claims, however, they still recite an abstract idea without significantly more. Step 2A: Prong 1: The limitations of the independent claims 1, 12, and 17 recite the abstract idea which falls into the category of Mental Processes comprising concepts performed in the human mind (including an observation, evaluation, judgment, opinion) and Mathematical Concept (including mathematical relationships, mathematical formulas or equations, mathematical calculations). The limitations recite Abstract Idea as follows: Claim 1: A method, comprising: generating, in an electronic device, a matrix used for the implementation of a data cipher algorithm, the generating the matrix including: providing a seed data element; generating, with a first function, a first pseudo-random data element using the seed data element; and generating, with a second function, a plurality of polynomials of a known degree based on the first pseudo-random data element; and verifying, with a verification function using a final portion of output data of the first function, that the matrix is conformable. Examiner notes that claim 1 recite limitations focus almost entirely on manipulating data using mathematical functions, generating pseudo-random elements, and calculating polynomials. The limitations recite Step-by-Step Logic: Providing a seed, running a function, and verifying an output are mental or logical steps that describe disembodied mental processes. Claim 12: A method, comprising: generating a matrix for a data cipher algorithm, the generating the matrix including: providing a seed data element; generating, with a first function, a first pseudo-random data element using the seed data element; generating, with a second function, a plurality of polynomials of a known degree based on the first pseudo-random data element; forming an element of the matrix with each of the plurality of polynomials; and verifying, with a verification function using a final portion of output data of the first, sponge-type function, that the matrix is conformable. Examiner notes that claim 12 recite Mathematical Concepts: Generating pseudo-random data, computing polynomials, populating a matrix, and running a verification function are mathematical concepts and calculations. And Mental Processes: The steps describe a logical algorithm or calculation that could theoretically be performed entirely by a human using a pen and paper. Claim 17: A method, comprising: generating a matrix for a data cipher algorithm, the generating the matrix including: providing a seed data element; generating, with a first function, a first pseudo-random data element using the seed data element; generating, with a second function, a plurality of polynomials of a known degree based on the first pseudo-random data element; forming an element of the matrix with each of the plurality of polynomials; and verifying, with a verification function using a final portion of output data of the first, sponge-type function, that the matrix is conformable. Examiner notes that claim 17 recite limitations recite the steps of providing a seed, generating pseudo-random numbers, polynomials, and matrices fall under "mathematical concepts" and "mental processes". The claim generically recites the concept of execution actions which can be performed in the human mind. If claim limitations, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the category of Mental Processes - concepts performed in the human mind (including an observation, evaluation, judgment, opinion) and Mathematical Concepts (including mathematical relationships, mathematical formulas or equations, mathematical calculations) grouping of abstract ideas. The claim as a whole recites methods of organizing human activity using mathematical concept of manipulating data using mathematical functions, generating pseudo-random elements, and calculating polynomials. Therefore, the claim limitations, fall within the Mental Processes: concepts performed in the human mind (including an observation, evaluation, judgment, opinion) grouping of abstract ideas and Mathematical Operations. Step 2A: Prong 2: The claims fail to recite any judicial exceptions because claims do not recite any specific machine. The claims do not recite a specific physical architecture, hardware, or customized electronic circuitry. Generating a matrix "for a data cipher algorithm" is often considered claiming the algorithm itself. In particular, the claim recites additional element (i.e., an electronic device) at a high-level of generality such that they amount no more than mere instructions to apply the exception using generic computer components. Generic Computer Implementation: The phrase "generating, in an electronic device" simply uses a computer as a generic tool to perform pure math, which courts consistently find does not make an idea less abstract. Accordingly, these elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea. Further, the claimed additional element merely describes how to generally “apply” the concept of specifies an order in a computer environment (MPEP: 2106.05(f)(2), “(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to distribute, contain, identify, or create blocks) or simply adding a general-purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.”) which is Mere Instructions To Apply An Exception. The claimed computer components are recited at a high level of generality and are merely invoked as tools to perform an existing storage object update process. Simply implementing the abstract idea on a generic computer is not a practical application of the abstract idea. Step 2B: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the claims do not reflect improvement in the technology. Further, mere automated instructions to apply an exception using a generic computer component cannot provide an inventive concept. Thus, the claims are not patent eligible. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements (i.e., an electronic device) amount to no more than mere instructions to apply the exception using general purpose computer. The additional element recited at a high-level of generality (i.e., as generic terms performing generic computer functions (instant spec. [0031], [0043], [0059]) such that it amounts no more than mere instructions to apply the exception using generic computer components. Accordingly, the additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Recitation of these element does not improve the functioning of the computer or to any other technology or technical field instead recite elements which are considered an improvement to the Abstract Idea itself. Therefore, the use of these elements individually or in combination, does no more than employ the computer as a tool to automate and/or implement the abstract idea. The use of a computer or processor to merely automate and/or implement the abstract idea cannot provide significantly more than the abstract idea itself (MPEP 2106.05(I)(A)(f) & (h)). Dependent claims 2-11, 13-16, and 18-20 are also rejected under the same analysis as cited in the rejection of claims 1, 12, and 17. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Ghosh et al., (US20250007693A1). Regarding claim 1, Ghosh discloses: A method, comprising: generating, in an electronic device ([0005] FIG. 2 illustrates a block diagram of an example processor and/or System on a Chip (SoC) that may have one or more cores, an integrated memory controller and a Kyber hardware accelerator), a matrix used for the implementation of a data cipher algorithm ([0035] Kyber.CPAPKE is an INDCPA-secure public-key encryption (PKE) scheme encrypting messages of a fixed length of 32 bytes. Kyber.CPAPKE.KeyGen( ) performs key generation for Kyber public-key encryption. The Kyber hardware accelerator 220 is used to perform Kyber.CPAPKE.KeyGen( ). Kyber.CPAPKE.KeyGen( ) performs key generation and has three independent operations, 1) generate Matrix Â, 2) generate secret vector a, and 3) generate secret vector e. Kyber.CPAPKE.KeyGen( ) uses the Matrix Â, secret vector a and secret vector e to generate a secret key (sk) and a public key (pk). The independent operations allow Keccak calls to be parallelized), the generating the matrix including: providing a seed data element ([0036] In the embodiment shown in FIG. 3 there are four SHA-3 engines 304-0, 304-1, 304-2, 304-3. The input (message) to each of the SHA-3 engines 304-0, 304-1, 304-2, 304-3 is a 32 byte seed (ρ). The 32 byte seed (ρ) is a randomly generated value to be used as the initial message. The same seed (32 byte seed (ρ)) that is stored in memory 302 a is input in parallel to each of the four SHA-3 engines 304-0, 304-1, 304-2, 304-3); generating, with a first function (i.e., generate unique pseudorandom stream for different polynomials of Matrix Â), a first pseudo-random data element using the seed data element ([0037] Each of the four SHA-3 engines 304-0, 304-1, 304-2, 304-3 has a respective counter in memory 302 a. The respective counter value 316-0, 316-1, 316-2, 316-4 stored in the counters in memory 302 a is read by the respective SHA-3 engine 304-0, 304-1, 304-2, 304-3 and concatenated with the 32 byte seed (ρ) in the SHA-3 engine 304-0, 304-1, 304-2, 304-3 to generate unique pseudorandom stream for different polynomials of Matrix Â; [0043] FIG. 4 is an execution flow chart of the Kyber hardware accelerator 220 shown in FIG. 3 configured to generate Matrix  for Kyber.CPAPKE.KeyGen( ); [0044] At block 402, the 32 byte seed (ρ) is loaded from memory. The 32 byte seed (ρ) is shared among the 4 SHA-3 engines 304-0, 304-1, 304-2, 304-3; [0045] At blocks 404 a, 404 b, 404 c, 404 d, each respective SHA-3 engine performs an XOF( ) function to process a different element of matrix  in parallel); and generating, with a second function (i.e., outputs of the Parse functions), a plurality of polynomials of a known degree based on the first pseudo-random data element ([0041] Each SHA-3 engine 304-0, 304-1, 304-2, 304-3 outputs a respective digest stream (byte stream) 314-0, 314-1 314-2, 314-3. The byte stream is processed by a Parse function (Parse ( ) which receives the byte stream and computes the NTT-representation. The coefficient outputs of the Parse functions are written to memory 302 b; [0046] At blocks 406 a, 406 b, 406 c, 406 d, each respective digest stream (byte stream) output by the respective SHA-3 engine is processed by a Parse function (Parse( )) in parallel); and verifying, with a verification function using a final portion of output data of the first function, that the matrix is conformable ([0042] The output is processed serially to derive the respective polynomial coefficients. Each of these polynomials are formed as degree 256 where coefficients of the polynomials have 12 bits and follow mod q (=3329) arithmetic. In each cycle for matrix A generation, two coefficients are computed from the output (digest stream) of each of the SHA3 engines; [0047] At block 408, the coefficient outputs of the Parse functions are written to the same memory location 312 in memory). Regarding claim 12, it is a method claim and recite similar subject matter as claim 1 and therefore rejected under similar ground of rejection. Regarding claim 17, it is a method claim and recite similar subject matter as claim 1 and therefore rejected under similar ground of rejection. Regarding claim 2, Ghosh discloses: The method according to claim 1, wherein the first function is a sponge-type function ([0034] The SHA-3 Standard (FIPS PUB 202) specifies the Secure Hash Algorithm-3 (SHA-3) family of functions on binary data. Each of the SHA-3 functions is based on an instance of the KECCAK algorithm. Examiner notes that Keccak uses a sponge construction, an innovative design where input data is "absorbed" into an internal state and then "squeezed" to produce the output hash). Regarding claim 3, Ghosh discloses: The method according to claim 2, wherein the first function comprises a third cryptographic hash function ([0040] Each SHA-3 engine processes a different element of matrix A in parallel. Each of the SHA-3 engines 304-0, 304-1, 304-2, 304-3 includes padding 306, Keccak-f 308 and buffer 310. Padding 306 takes any arbitrary length less than a SHA3 block-size as input data and transforms it to data with length equal to the SHA-3 block-size. Keccak-f 308 computes the 24 rounds Keccak operations on the input data received from padding 306. Buffer 310 stores the output from Keccak-f block locally. Examiner notes that Keccak function is considered as a third hash function). Regarding claim 4, Ghosh discloses: The method according to claim 3, wherein the third cryptographic hash function is a Keccak function ([0040] Each SHA-3 engine processes a different element of matrix A in parallel. Each of the SHA-3 engines 304-0, 304-1, 304-2, 304-3 includes padding 306, Keccak-f 308 and buffer 310. Padding 306 takes any arbitrary length less than a SHA3 block-size as input data and transforms it to data with length equal to the SHA-3 block-size. Keccak-f 308 computes the 24 rounds Keccak operations on the input data received from padding 306. Buffer 310 stores the output from Keccak-f block locally). Regarding claim 18, it is a method claim and recite similar subject matter as claim 4 and therefore rejected under similar ground of rejection. Regarding claim 5, Ghosh discloses: The method according to claim 1, wherein the second function takes as an input a data element of a variable size and produces as an output the plurality of polynomials of the known degree ([0037] Each of the four SHA-3 engines 304-0, 304-1, 304-2, 304-3 has a respective counter in memory 302 a. The respective counter value 316-0, 316-1, 316-2, 316-4 stored in the counters in memory 302 a is read by the respective SHA-3 engine 304-0, 304-1, 304-2, 304-3 and concatenated with the 32 byte seed (ρ) in the SHA-3 engine 304-0, 304-1, 304-2, 304-3 to generate unique pseudorandom stream for different polynomials of Matrix Â. In an embodiment, the size of the counter value is 4 bytes; [0038] The SHA-3 engines 304-0, 304-1, 304-2, 304-3 generate Matrix  ( [i][j]) in the NTT domain by performing the operations shown below in parallel. The variable k defines the size of the public matrix  as k×k. The variables i and j are temporary variables used in this procedure to generate k×k polynomials of Â; [0042] The output is processed serially to derive the respective polynomial coefficients. Each of these polynomials are formed as degree 256 where coefficients of the polynomials have 12 bits and follow mod q (=3329) arithmetic). Regarding claim 6, Ghosh discloses: The method according to claim 1, wherein the data cipher algorithm is a lattice-based cryptography algorithm ([0069] As discussed, the Kyber hardware accelerator with parallel SHA-3 engines reduces latency for secure key exchange for Kyber. Additionally, enriching the PQC portfolio with the HW IP, enables the kyber scheme that is the selected standardization for the lattice based). Regarding claim 7, Ghosh discloses: The method according to claim 6, wherein the data cipher algorithm is the “Kyber” algorithm ([0035] Kyber.CPAPKE is an INDCPA-secure public-key encryption (PKE) scheme encrypting messages of a fixed length of 32 bytes. Kyber.CPAPKE.KeyGen( ) performs key generation for Kyber public-key encryption. The Kyber hardware accelerator 220 is used to perform Kyber.CPAPKE.KeyGen( )). Regarding claim 8, Ghosh discloses: The method according to claim 7, wherein the matrix is the matrix A of the “Kyber” algorithm ([0035] Kyber.CPAPKE is an INDCPA-secure public-key encryption (PKE) scheme encrypting messages of a fixed length of 32 bytes. Kyber.CPAPKE.KeyGen( ) performs key generation for Kyber public-key encryption. The Kyber hardware accelerator 220 is used to perform Kyber.CPAPKE.KeyGen( )). Regarding claim 9, Ghosh discloses: The method according to claim 7, wherein the matrix is a context vector of the “Kyber” algorithm ([0035] Kyber.CPAPKE.KeyGen( ) performs key generation and has three independent operations, 1) generate Matrix Â, 2) generate secret vector a, and 3) generate secret vector e. Kyber.CPAPKE.KeyGen( ) uses the Matrix Â, secret vector a and secret vector e to generate a secret key (sk) and a public key (pk). The independent operations allow Keccak calls to be parallelized). Regarding claim 10, Ghosh discloses: The method according to claim 6, wherein the data cipher algorithm is the “CRYSTALS-Dilithium” algorithm ([0069] Also, the multiple instances of the SHA3 engines described for use with Kyber design modules proposed in this invention are generic and can be easily ported across other lattice based PQC primitives, for example, Dilithium). Regarding claim 11, Ghosh discloses: The method according to claim 1, wherein the final portion of the output data of the first function includes a second pseudo-random data element that is not used by the second function ([0042] The output is processed serially to derive the respective polynomial coefficients. Each of these polynomials are formed as degree 256 where coefficients of the polynomials have 12 bits and follow mod q (=3329) arithmetic. In each cycle for matrix A generation, two coefficients are computed from the output (digest stream) of each of the SHA3 engines; [0047] At block 408, the coefficient outputs of the Parse functions are written to the same memory location 312 in memory). Regarding claim 13, Ghosh discloses: The method according to claim 12, wherein the seed data element is a 32-byte data element comprising 256 bits ([0034] The SHA-3 Standard (FIPS PUB 202) specifies the Secure Hash Algorithm-3 (SHA-3) family of functions on binary data. Each of the SHA-3 functions is based on an instance of the KECCAK algorithm. The SHA-3 family consists of four cryptographic hash functions, called SHA3-224, SHA3-256, SHA3-384, and SHA3-512, and two extendable-output functions (XOFs), called SHAKE128 and SHAKE256. Hash functions are components for information security applications, including 1) the generation and verification of digital signatures, 2) key derivation, and 3) pseudorandom bit generation. For hash functions, the input is called the message, and the output is called the (message) digest or the hash value. The length of the message can vary; the length of the digest is fixed; [0035] Kyber.CPAPKE is an INDCPA-secure public-key encryption (PKE) scheme encrypting messages of a fixed length of 32 bytes). Regarding claim 15, Ghosh discloses: The method according to claim 12, wherein the second function takes as an input a data element of a variable size and produces as an output the plurality of polynomials of the known degree ([0037] Each of the four SHA-3 engines 304-0, 304-1, 304-2, 304-3 has a respective counter in memory 302 a. The respective counter value 316-0, 316-1, 316-2, 316-4 stored in the counters in memory 302 a is read by the respective SHA-3 engine 304-0, 304-1, 304-2, 304-3 and concatenated with the 32 byte seed (ρ) in the SHA-3 engine 304-0, 304-1, 304-2, 304-3 to generate unique pseudorandom stream for different polynomials of Matrix Â. In an embodiment, the size of the counter value is 4 bytes; [0038] The SHA-3 engines 304-0, 304-1, 304-2, 304-3 generate Matrix  ( [i][j]) in the NTT domain by performing the operations shown below in parallel. The variable k defines the size of the public matrix  as k×k. The variables i and j are temporary variables used in this procedure to generate k×k polynomials of Â; [0042] The output is processed serially to derive the respective polynomial coefficients. Each of these polynomials are formed as degree 256 where coefficients of the polynomials have 12 bits and follow mod q (=3329) arithmetic). Regarding claim 16, Ghosh discloses: The method according to claim 12, wherein the second function is a selection by injection type function ([0046] At blocks 406 a, 406 b, 406 c, 406 d, each respective digest stream (byte stream) output by the respective SHA-3 engine is processed by a Parse function (Parse( )) in parallel; [0047] At block 408, the coefficient outputs of the Parse functions are written to the same memory location 312 in memory). Regarding claim 19, Ghosh discloses: The method according to claim 17, wherein the cryptographic hash function is applied four times during the squeeze-out phase ([0046] At blocks 406 a, 406 b, 406 c, 406 d, each respective digest stream (byte stream) output by the respective SHA-3 engine is processed by a Parse function (Parse( )) in parallel; [0047] At block 408, the coefficient outputs of the Parse functions are written to the same memory location 312 in memory). Regarding claim 20, Ghosh discloses: The method according to claim 17, further comprising: forming the data element to be hashed from a first data element and a second data element, the first data element having a same size as the output data element and being generated by a seed function; and incorporating, with an XOR function, the seed data element and the plurality of indices to the first data element before the applying the cryptographic hash function (Fig. 3 & Fig. 4; [0034-0047]). Allowable Subject Matter Claim 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. However, claim 14 along with other claims will continue to be rejected under 35 USC § 101 Abstract Idea as described in above rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED M AHSAN whose telephone number is (571)272-5018. The examiner can normally be reached 8:30 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Korzuch can be reached at 571-272-7589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SYED M AHSAN/Primary Examiner, Art Unit 2491
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Prosecution Timeline

Oct 09, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §101, §102 (current)

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