DETAILED ACTION
This action is responsive to the communication filed on 12/18/2025. Claims 1 and 3-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tzafrir (US 20190050022 A1) in view of Yang (US 20250006252 A1).
As per claim 1,
1. A storage device comprising: a storage controller that comprises training circuitry and that transmits a data signal comprising a command and user data, the training circuitry performing a read training operation based on at least a part of the user data; [Tzafrir teaches a system with a controller comprising components (training circuitry) (e.g. timing adjustment engine) which may perform a second adjustment process (read training) for adjusting interface timing signals, the second adjustment process involving sending write command and user data to a non-volatile memory device, reading the data as written, and then performing a comparison using the read data in association with adjusting timing signal (para. 41, 44, 59, 61-63, 73-76, 78-79, 81, 27; fig. 3A and associated paragraphs), wherein the controller or components thereof (such as the timing adjustment engine or processor of the controller) may correspond to the training circuitry] and a non-volatile memory device that comprises a memory cell array and a register, the non-volatile memory device being configured to receive the data signal from the storage controller, to store the at least a part of the user data used for the read training operation in the register during a runtime of the storage device, and [Tzafrir teaches that the data for the second adjustment process may be written to a memory array or one or more latches (register) in the memory device and re-read (para. 61, 63, 68, 41, 73-76), where the runtime may correspond to the controller, and, therefore, the system (storage device) being active for executing instructions such as issuing of the write command.]
While Trafrir does not explicitly disclose storing the user data in both the latches and the memory array, Yang discloses:
to store the user data in the memory cell array. [Tzafrir as shown above teaches storing data to one or more latches, reading the data again, and checking for errors (see above; para. 68, 73-76); Tzafrir’s disclosure is not explicit with respect to storing the data in both the memory cell array and the latches (register), but Yang teaches storing data into a page buffer for error checking while also providing for storing the data from the page buffer into a non-volatile memory element before or after error checking the data in the page buffer (para. 4-5, 27-28; figs. 2-5 and associated paragraphs; see para 18, 21 providing the memory element comprising flash and the page buffer comprising SRAM)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
As per claim 13, Tzafrir in view of Yang teaches claim 1 as shown above and further teaches:
13. The storage device according to claim 1, wherein the training circuitry performs the read training operation, based on receiving a read training request from a host. [Tzafrir teaches a message received from a host causing the controller to perform the second adjustment process (para. 56, 59)]
As per claim 14, Tzafrir in view of Yang teaches claim 13 as shown above and further teaches:
14. The storage device according to claim 13, wherein, after receiving the read training request, the storage controller determines a time point during the runtime to perform the read training operation. [Tzafrir as shown above teaches the controller initiating the second adjustment process, responsive to host message, comprising writing data and re-reading the data to adjust timing associated with read or write operations (read training operation) (para. 59, 61, 63, 68, 73-76, 79, 81), where performing of the operations by the controller necessarily corresponds to the controller having determined a timepoint for performing the operations while active (runtime)]
As per claim 15, Tzafrir in view of Yang teaches claim 1 as shown above and further teaches:
15. The storage device according to claim 1, wherein the command comprises a program data-in command. [Tzarir teaches the controller initiating a second adjustment process comprising writing data and re-reading data (61, 63, 68, 73-76, 79, 81; see para. 61 providing write command)]
As per claim 20,
20. A method for operating a storage device, the method comprising: transmitting, by a storage controller, a data signal comprising a command and user data to a non-volatile memory device, the user data including a training pattern comprising at least a part of the user data; receiving, by the non-volatile memory device, the data signal from the storage controller; [Tzafrir teaches a system with a controller comprising components (e.g. timing adjustment engine) which may perform a second adjustment process (read training) for adjusting interface timing signals, the second adjustment process involving sending write command and user data to a non-volatile memory device, reading the data as written, and then performing a comparison using the read data in association with adjusting timing signal (para. 41, 44, 59, 61-63, 73-76, 78-79, 81, 27; fig. 3A and associated paragraphs), wherein the user data may correspond to the claim’s user data and the training pattern] storing, by the non-volatile memory device, the user data into a memory cell array of the non-volatile memory device and the at least a part of the user data comprising the training pattern in a register of the non-volatile memory device; receiving, by the storage controller, the at least a part of the user data comprising the training pattern from the register of the non-volatile memory device; and performing, by a training circuitry of the storage controller, a training operation based on the at least the part of the user data. [Tzafrir teaches that the data for the second adjustment process may be written to a memory array or one or more latches (register) in the memory device and re-read to check for errors, where timing signal of read/write operations may be adjusted based on presence of errors (para. 61, 63, 68, 41, 73-76, 79), wherein the controller or components thereof (such as the timing adjustment engine or processor of the controller) may correspond to the training circuitry]
While Trafrir does not explicitly disclose storing the user data in both the latches and the memory array, Yang discloses:
the user data into a memory cell array of the non-volatile memory device [Tzafrir as shown above teaches storing data to one or more latches, reading the data again, and checking for errors (see above; para. 68, 73-76); Tzafrir’s disclosure is not explicit with respect to storing the data in both the memory cell array and the latches (register), but Yang teaches storing data into a page buffer for error checking while also providing for storing the data from the page buffer into a non-volatile memory element before or after error checking the data in the page buffer (para. 4-5, 27-28; figs. 2-5 and associated paragraphs; see para 18, 21 providing the memory element comprising flash and the page buffer comprising SRAM)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
Claims 3-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tzafrir (US 20190050022 A1) in view of Yang (US 20250006252 A1) in view of Reusswig et al. (US 11398288 B1).
As per claim 3, Tzafrir in view of Yang teaches claim 1 as shown above. It does not explicitly disclose, but Reusswig discloses:
3. The storage device according to claim 1, wherein: the training circuitry comprises a pattern buffer, and the storage controller stores in the pattern buffer, as a training pattern, the at least the part of the user data. [Tzafrir in view of Yang as shown above teaches that the controller may retain a copy of the data (training pattern, the at least part of the user data) to be used during the second adjustment process by being compared to the data that was programmed to the latches and re-read (Tzafrir: para. 76, 73-75, 81; Yang: para. 4-5, 27-28); Tzafrir in view of Yang does not explicitly disclose a buffer for storing the data on the controller, but Reusswig discloses, in association with adjusting interface transfer parameters, loading test data pattern into a buffer of a storage controller to be compared against data transferred between the storage controller and storage medium (col. 12, lines 22-54, col. 14, lines 23-57)]
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
As per claim 4, Tzafrir in view of Yang in view of Reusswig teaches claim 3 as shown above and further teaches:
4. The storage device according to claim 3, wherein: the training circuitry further comprises a comparator, [Tzafrir in view of Yang as shown above teaches the controller comparing the copy of data retained against data programmed to the memory device and re-read (para. 76, 73-75, 81), where the controller or the components comprising the controller may correspond to the comparator] the non-volatile memory device stores, in the register, the user data received from the storage controller, [Tzafrir in view of Yang in view of Reusswig as shown above teaches latches (register) of the memory device may be used to program and read the data (see claim 1 above; Tzafrir: para. 68; Yang: para. 4-5, 27-28)] the non-volatile memory device transmits to the comparator, the at least a part of the user data that is used for the read training operation and that is stored in the register, and the comparator compares the training pattern stored in the pattern buffer with the at least the part of the user data received from the register. [Tzafrir teaches that the controller may retain a copy of the data (training pattern, the at least part of the user data) to be used during the second adjustment process by being compared to the data that was programmed to the latches and re-read (para. 76, 73-75, 81; see claim 3 above providing for pattern buffer by Reusswig (Reusswig: col. 12, lines 22-54, col. 14, lines 23-57))]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
As per claim 5, Tzafrir in view of Yang in view of Reusswig teaches claim 4 as shown above and further teaches:
5. The storage device according to claim 4, wherein, based on receiving a read training command from the storage controller, the non-volatile memory device transmits to the comparator the at least the part of the user data stored in the register. [Tzafrir teaches the controller transmitting a read command (read training command) to the non-volatile memory device for sensing the stored data (para. 63, 73-76, 81)]
As per claim 6, Tzafrir in view of Yang in view of Reusswig teaches claim 4 as shown above and further teaches:
6. The storage device according to claim 4, wherein a size of the at least the part of the user data transmitted from the register to the comparator is the same as a size of the training pattern stored in the pattern buffer. [Where Tzafrir in view Yang in view of Reusswig as shown above teaches writing data to the latches of a memory device and rereading the data for comparison to a copy held in the controller’s buffer (see claims 3-4 above), Reusswig further discloses loading test data pattern into a buffer of a storage controller to be compared against data transferred between the storage controller and storage medium (col. 12, lines 22-37); Reusswig teaches the controller transfers the test data pattern to the storage medium, reads the test data pattern from the storage medium, and compares the test data pattern as read to the test data pattern in the controller buffer (col. 15, line 34 – col. 16, line 65), where Reusswig as shown above describes the test data pattern being stored/transferred/read without specifying segmenting or storing/transferring/reading the test data in parts, the test data pattern stored in the controller buffer would necessarily be the same (i.e. same size) as the test data pattern read from the storage medium]
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
As per claim 7 Tzafrir in view of Yang in view of Reusswig teaches claim 4 as shown above and further teaches:
7. The storage device according to claim 4, wherein: the non-volatile memory device stores, in the memory cell array, the user data stored in the register, based on a result from the comparator. [Tzafrir in view of Yang in view of Reusswig as shown above teaches storing user data in latches and also in a memory array (see claim 1 above); Yang teaches write data stored into a page buffer, where, only after completion of verification indicating no errors, the data is written from the page buffer to a nonvolatile memory element (para. 4, 28; fig. 4-5 and associated paragraphs)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
As per claim 8, Tzafrir in view of Yang in view of Reusswig teaches claim 7 as shown above and further teaches:
8. The storage device according to claim 7, wherein: based on the comparator determining that the training pattern stored in the pattern buffer matches the at least the part of the user data received from the register, [Tzafrir in view of Yang in view of Reusswig as shown above teaches a memory controller storing user data into a latch in a memory device and re-reading the data for comparison to a copy in the controller (Tzafrir: 76, 73-75, 81; Reusswig: col. 12, lines 22-54, col. 14, lines 38-45)] the storage controller transmits a program confirmation command to the non-volatile memory device, and based on receiving the program confirm command from the storage controller, the non-volatile memory device stores in the memory cell array the user data that is stored in the register. [Yang teaches a program command may be issued by a controller, responsive to the data having no error, to store the data buffered in the page buffer to the nonvolatile memory (Yang: para. 4, 28; Tzafrir: para. 68)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
As per claim 9, Tzafrir in view of Yang in view of Reusswig teaches claim 4 as shown above and further teaches:
9. The storage device according to claim 4, wherein: after the non-volatile memory device stores the user data stored in the register in the memory cell array, the comparator determines whether the training pattern and the at least the part of the user data received from the register correspond to each other. [Tzafrir in view of Yang in view of Reusswig as shown above teaches a memory controller storing user data into latches in a memory device and re-reading the data for comparison to a copy in the controller to check for errors (see claim 3-4; Tzafrir: 76, 73-75, 81; Reusswig: col. 12, lines 22-54, col. 14, lines 38-45), where the data in the latches may be programmed into a memory array and then read from the latches to check for errors (Yang: para. 5, 27; fig. 2-3 and associated paragraphs)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
As per claim 10, Tzafrir in view of Yang in view of Reusswig teaches claim 4 as shown above and further teaches:
10. The storage device according to claim 4, wherein, based on the comparator determining that the training pattern and the at least the part of the user data received from the register do not correspond to each other, the storage controller adjusts a delay of the data signal. [Tzafrir teaches adjusting timing signal of read/write operations responsive to determining that a number of errors (i.e. mismatches) exceeds a threshold (para. 79); Reusswig similarly teaches adjusting interface transfer parameters such as timing for controlling the transfer of data while errors (mismatches) are detected (col. 14, lines 23-57; fig. 6 and associated paragraphs)]
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
As per claim 19,
19. A storage controller comprising: a pattern generator that generates a training pattern comprising a part of user data; a controller interface that transmits, to a non-volatile memory device, a data signal comprising a command and user data that includes the part of the user data that comprises the training pattern; and a comparator that receives the part of the user data that comprises the training pattern and that has been stored in a register of the non-volatile memory device from the non-volatile memory device and determines whether the training pattern stored in the pattern buffer and the part of the user data received from the non-volatile memory device correspond to each other, [Tzafrir teaches a system with a controller comprising components (e.g. timing adjustment engine) which may perform a second adjustment process (read training) for adjusting interface timing signals, the second adjustment process involving sending write command and user data to a non-volatile memory device to be written into the latches or a memory array of the memory device, re-reading the data as written, and then performing a comparison using the read data and a copy held in the controller, in association with adjusting timing signal (para. 41, 44, 59, 61-63, 68, 73-76, 78-79, 81, 27; fig. 3A and associated paragraphs; see para. 61, 63, fig. 3A providing interface of the controller to the memory device), wherein the controller or components thereof (such as the processor of the controller) may correspond to pattern generator and comparator; while the claim recites a part of the user data to comprise a training pattern, where the claim does not positively recite and exclude other part(s) of the user data from comprising the training pattern, the user data as a whole may be considered as training pattern under the broadest reasonable interpretation.] and based on the comparator determining that the training pattern and the part of the user data received from the register do not correspond to each other, the storage controller adjusts a delay of the data signal. [Tzafrir teaches, based on the comparison, adjusting timing signal of read/write operations responsive to determining that a number of errors (i.e. mismatches) exceeds a threshold (para. 79, 76)]
Tzafrir does not explicitly disclose, but Yang discloses:
wherein: based on the comparator determining that the training pattern stored in the pattern buffer matches the part of the user data received from the non-volatile memory device, the controller interface transmits a program confirmation command to the non-volatile memory device, the program confirm command instructing the non-volatile memory device to store in a memory cell array the user data that is stored in the register, [Where Tzafrir as shown above teaches determining the number of errors (i.e. mismatches) in data written to latches of a memory device (see the rejection above; para. 79, 76), it does not explicitly disclose storing the data from the latches to a memory array; however, Yang teaches write data stored into a page buffer, where, only after completion of verification indicating no errors, a program command is issued to store the data buffered in the page buffer to nonvolatile memory (para. 4, 28; fig. 4-5 and associated paragraphs; see para 18, 21 providing the memory element comprising flash and the page buffer comprising SRAM)]
Tzafrir and Yang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir and Yang, to modify the disclosures by Tzafrir to include disclosures by Yang since they both teach data storage and verification, wherein Yang is directed towards enhance data integrity and reliability of data storage devices (para. 3). Therefore, it would be applying a known technique (storing data in a page buffer for error checking and also storing the data from the page buffer to a nonvolatile memory element) to a known device (memory controller writing user data to a latch or a memory array of a nonvolatile memory device and reading the data to test for errors) ready for improvement to yield predictable results (memory controller writing user data to a latch of a memory device to check for errors, where the user data is also written from the latch to a memory array of the memory device to provide reduced latency in error checking and permanently storing user data). MPEP 2143
Tzafrir in view of Yang does not explicitly disclose, but Reusswig discloses:
a pattern buffer that stores the training pattern;; stored in the pattern buffer [Tzafrir in view of Yang as shown above teaches that the controller may retain a copy of the data to be used during the second adjustment process by being compared to the data that was programmed to the latches and re-read (Tzafrir: para. 76, 73-75, 81; Yang: para. 4-5, 27-28); Tzafrir in view of Yang does not explicitly disclose a buffer for storing the data on the controller, but Reusswig discloses, in association with adjusting interface transfer parameters, loading test data pattern into a buffer of a storage controller to be compared against data transferred between the storage controller and storage medium (col. 12, lines 22-54, col. 14, lines 23-57)]
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tzafrir (US 20190050022 A1) in view of Yang (US 20250006252 A1) in view of Reusswig et al. (US 11398288 B1) in view of Cha (US 20190318797 A1) in view of Liu et al. (US 20230280928 A1).
As per claim 11, Tzafrir in view of Yang in view of Reusswig does not explicitly disclose, but Cha discloses:
11. The storage device according to claim 4, wherein, based on receiving a request to adjust a length of the training pattern, a size of the at least the part of the user data stored in the pattern buffer and a size of the at least the part of the user data transmitted from the register to the comparator are adjusted. [Tzafrir in view of Yang in view of Reusswig as shown above teaches writing data to latches of a memory device and rereading the data to be compared to a copy held in the controller’s buffer (see claims 3-4 above), where Reusswig further teaches a test data pattern may be stored to the controller and written/read from the storage device buffer without specifying modifications or segmenting (i.e. test data pattern stored to the controller and test data patter read from the storage device buffer being the same data necessarily having the same size) (Reusswig: col. 12, lines 22-37, col. 15, line 34 – col. 16, line 65); Cha teaches test data generated for testing a memory device (para. 47-50; fig. 3 and associated paragraphs), wherein the test data is generated and output to the memory device by a master device (host) (para. 56-59); Cha teaches that the test data may be variously changed or modified to include data suitable for testing the memory device (para. 48), where it would have been obvious for one of ordinary skill in the arts, provided with Cha’s disclosures directed to a host generating test data and test data being modifiable, to provide for host providing modifications to test data]
[Where Cha does not explicitly disclose modifying such test data to be of a different length, Liu teaches test data used in writing to or reading from a memory chip, where the test data may be set to a fixed length or, alternatively, simply set to any length (para. 26)]
Tzafrir, Yang, and Reusswig are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Reusswig, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Reusswig since they both teach data storage and testing, wherein Reusswig is directed towards improved storage performs such as quicker reads and writes (col. 1, lines 13-25). Therefore, it would be applying a known technique (controller comprising a buffer for holding test data used for comparison in adjusting interface transfer parameters) to a known device (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in the controller in association with determining interface timing signal adjustments) ready for improvement to yield predictable results (memory controller writing user data to a latch and reading the data, where the data read is compared against a copy of the data held in a buffer of the controller in association with determining interface timing signal adjustments; doing so would provide for improved administration of the comparison operations by providing a dedicated location for accessing the data against which the data read from the nonvolatile memory or latches is to be compared). MPEP 2143
Tzafrir, Yang, Reusswig, and Cha are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang in view of Reusswig and Cha, to modify the disclosures by Tzafrir in view of Yang in view of Reusswig to include disclosures by Cha since they both teach data storage and testing, wherein Cha is directed towards improved device test procedures (para. 6). Therefore, it would be applying a known technique (host providing test data to a memory device and modifications to the test data) to a known device (memory controller for performing adjustment to interface timing signals by storing and rereading user data) ready for improvement to yield predictable results (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data to provide for improved testing by adjusting the user data pattern being tested). MPEP 2143
Tzafrir, Yang, Reusswig, Cha, and Liu are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang in view of Reusswig in view of Cha and Liu, to modify the disclosures by Tzafrir in view of Yang in view of Reusswig in view of Cha to include disclosures by Liu since they both teach data storage and testing, wherein Liu is directed towards improved memory testing (para. 2-3). Therefore, it would be applying a known technique (test data used in memory testing, the length of the test data configurable to any length) to a known device (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data) ready for improvement to yield predictable results (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data, where said modification may include setting an alternative length to the test data in order to provide for a more robust test involving different data parameters including length). MPEP 2143
As per claim 12, Tzafrir in view of Yang in view of Reusswig in view of Cha in view of Liu teaches claim 11 as shown above and further teaches:
12. The storage device according to claim 11, wherein the request to adjust the length of the training pattern is received from a host. [Tzafrir in view of Yang in view of Reusswig in view of Cha in view of Liu as shown above teaches host generating and modifying length of test data provided to a memory device (see claim 11 above; Cha: para. 47-59; Liu: para. 26)]
Tzafrir, Yang, Reusswig, and Cha are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang in view of Reusswig and Cha, to modify the disclosures by Tzafrir in view of Yang in view of Reusswig to include disclosures by Cha since they both teach data storage and testing, wherein Cha is directed towards improved device test procedures (para. 6). Therefore, it would be applying a known technique (host providing test data to a memory device and modifications to the test data) to a known device (memory controller for performing adjustment to interface timing signals by storing and rereading user data) ready for improvement to yield predictable results (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data to provide for improved testing by adjusting the user data pattern being tested). MPEP 2143
Tzafrir, Yang, Reusswig, Cha, and Liu are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang in view of Reusswig in view of Cha and Liu, to modify the disclosures by Tzafrir in view of Yang in view of Reusswig in view of Cha to include disclosures by Liu since they both teach data storage and testing, wherein Liu is directed towards improved memory testing (para. 2-3). Therefore, it would be applying a known technique (test data used in memory testing, the length of the test data configurable to any length) to a known device (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data) ready for improvement to yield predictable results (memory controller for performing adjustment to interface timing signals by storing and rereading user data, wherein the host may further provide modifications to the user data, where said modification may include setting an alternative length to the test data in order to provide for a more robust test involving different data parameters including length). MPEP 2143
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tzafrir (US 20190050022 A1) in view of Yang (US 20250006252 A1) in view of Johnson et al. (US 6971046 B1).
As per claim 16, Tzafrir in view of Yang teaches claim 15 as shown above. It does not explicitly disclose, but Johnson discloses:
16. The storage device according to claim 15, wherein the command further comprises a read training command. [Tzafrir as shown above teaches controller issuing write and read requests in association with the second adjustment process and comparing the data original written with the data re-read (61, 63, 68, 73-76, 79, 81); it does not explicitly disclose, but Johnson discloses a write, read, verify command that similarly causes writing of data to a disk, reading the data, and comparing the first written data to the data read back (col. 14, lines 23-34]
The disclosures by Tzafrir in view of Yang and Johnson are analogous because they are in the same field of endeavor of data storage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tzafrir in view of Yang and Johnson, to modify the teachings of Tzafrir in view of Yang to include the teaching of Johnson since they both teach data storage and verification, wherein Johnson is directed towards improved testing and data verification (col. 2, lines 9-15). Therefore, it would have been a simple substitution of first types of operations (separately submitting commands for writing and reading data for verification) for another type of operation (a write, read, verify command for performing writing, reading, and comparison of data read back) ready for improvement to provide predictable results (faster processing of the write, read, and verify process by the memory device by not requiring the device to wait for a separately command from the controller before carrying out each step). MPEP 2143
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tzafrir (US 20190050022 A1) in view of Yang (US 20250006252 A1) in view of Meiri et al. (US 20190244675 A1).
As per claim 17, Tzafrir in view of Yang teaches claim 1 as shown above. It does not explicitly disclose, but Meiri discloses:
17. The storage device according to claim 1, wherein: the training circuitry comprises a pattern generator, and the pattern generator generates a plurality of training patterns based on the user data. [Meiri teaches a data storage system performing tests by writing host data, reading the host data, and comparing the host data as written and read, where, in addition to the host data, certain host specific information may also be stored, read, and compared along with the host data (together, training pattern) (para. 48, 44; fig. 2, 4, and associated paragraphs; see para. 41, 43 on data storage system comprising storage processors), where the host specific information may comprise one or more of a various categories of information including disk ID, LBA, write length, among others (para. 49)]
Tzafrir, Yang, and Meiri are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Meiri, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Meiri since they both teach data storage and validation, wherein Meiri is directed towards improved storage performs such as quicker reads and writes (para. 2, 8). Therefore, it would be applying a known technique (generating test data comprising host data and one or more of a plurality of host specific information) to a known device (memory controller storing copy of user data, writing the user data to memory latches, and rereading the user data) ready for improvement to yield predictable results (memory controller storing copy of test data, writing the test data to memory latches, and rereading the test data, wherein the test data may also include, in addition to a user data, one or more of a plurality of host specific information to provide for a method of generating different data patterns to be tested). MPEP 2143
As per claim 18, Tzafrir in view of Yang in view of Meiri teaches claim 17 as shown above and further teaches:
18. The storage device according to claim 17, wherein at least some of the plurality of training patterns have different lengths from each other. [Meiri as shown above teaches a data storage system performing tests by writing host data, reading the host data, and comparing the host data as written and read, where, in addition to the host data, certain host specific information may also be stored, read, and compared along with the host data (together, training pattern) (para. 48, 44; fig. 2, 4, and associated paragraphs; see para. 41, 43 on data storage system comprising storage processors), where the host specific information may comprise one or more of a various categories of information including disk ID, LBA, write length, among others (para. 49); where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures of Meiri providing for a plurality of types of host specific information that may be stored, read, and tested along with host data as a test pattern, that the different types of host specific information may comprise different sizes resulting in the test pattern similarly resulting in differing sizes]
Tzafrir, Yang, and Meiri are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Tzafrir in view of Yang and Meiri, to modify the disclosures by Tzafrir in view of Yang to include disclosures by Meiri since they both teach data storage and validation, wherein Meiri is directed towards improved storage performs such as quicker reads and writes (para. 2, 8). Therefore, it would be applying a known technique (generating test data comprising host data and one or more of a plurality of host specific information) to a known device (memory controller storing copy of user data, writing the user data to memory latches, and rereading the user data) ready for improvement to yield predictable results (memory controller storing copy of test data, writing the test data to memory latches, and rereading the test data, wherein the test data may also include, in addition to a user data, one or more of a plurality of host specific information to provide for a method of generating different data patterns to be tested). MPEP 2143
Response to Arguments
The rejection of claims 1 and 20 on the ground of non-statutory double patenting has been withdrawn in view of the amendments by the applicant.
Applicant’s arguments with respect to the rejection of claims 1, 20, and claims depending therefrom under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of amendments to the claims and newly found prior arts.
Claim 19’s rejection under 35 USC 103 is similarly withdrawn in view of the amendments and a new ground of rejection is made upon further consideration in view of amendments to the claims and newly found prior arts. However, with respect to the remark(s) on page 11 of the remarks distinguishing the recitation in claim 19, of a part of user data comprising a training pattern used for training, from using the whole of the user data for training, the examiner respectfully disagrees and submits, where the claim recites a part of the user data to comprise a training pattern but does not positively recite other part(s) of the user data which are excluded from comprising the training pattern, that, under the broadest reasonable interpretation of the claim language, the user data as a whole may be considered as training pattern as well.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Ehrlich et al. (US 20160351270 A1) teaches storing and reading user data to detect for read retention errors, where a portion of the user data comprises a test pattern.
Mozak et al. (US 20150066819 A1) teaches writing a training signal to a register, reading the training signal from the register, checking the read training signal for errors, and causing adjustments to at least one of an input/output parameter of memory device based on the number of errors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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