Prosecution Insights
Last updated: October 04, 2026
Application No. 18/911,234

Multicore Processor Clock Distribution Using Asynchronous Wavefront

Final Rejection §103
Filed
Oct 09, 2024
Priority
Mar 30, 2024 — provisional 63/572,257
Examiner
BIRKHIMER, CHRISTOPHER D
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Tenstorrent Usa Inc.
OA Round
2 (Final)
75%
Grant Probability
Favorable
3-4
OA Rounds
1y 1m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
384 granted / 515 resolved
+19.6% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
15 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
19.6%
-20.4% vs TC avg
§112
26.9%
-13.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 515 resolved cases

Office Action

§103
DETAILED ACTION The current Office Action is in response to the papers submitted 05/20/2026. Claims 1 - 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 – 9 and 11 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carson et al. (WO 2024/040108) referred to as Carson in view of Miller et al. (Pat 9,372,503) referred to as Miller. Regarding claim 1, Carson teaches a method for wave clock distribution [Paragraph 0041; The clock signal is propagated through the node array] to a network of computational nodes [102, Fig 1], comprising: providing, from a clock source [106, Fig 1; Paragraph 0035; Item 106 is a clock generator that provides a clock signal to the node array], a clock signal to a plurality of nodes [202, Fig 3; Paragraphs 0038 and 0047; The clock signal is provided to the nodes in the array horizontally along 206 and vertically along 204] of the network of computational nodes [102, Fig 1]; distributing, from each node of the plurality of nodes [202, Fig 3], the clock signal to a respective adjacent node [Figs 2 - 3; Paragraphs 0039 – 0041 and 0047; The clock signal is distributed diagonally or in rows and columns from a root node along the rows and columns to adjacent nodes]; and propagating, via the adjacent nodes, the clock signal to any additional nodes of the network of computational nodes [102, Fig 1] that are not among the plurality of nodes or the adjacent nodes [Figs 2 - 3; Paragraphs 0040 - 0041 and 0047; The clock signal is propagated from the root node to other nodes in the array that are not root nodes in a diagonal, vertical, or horizontal manner]. However, Carson may not specifically disclose the limitation(s) of providing, from a clock source via a clock distribution tree, a clock signal to a plurality of nodes wherein each node of the plurality of node receives the clock signal synchronously via the clock distribution tree. Miller teaches providing, from a clock source via a clock distribution tree, a clock signal to a plurality of nodes wherein each node of the plurality of node receives the clock signal synchronously via the clock distribution tree [Column 4, Lines 27 – 46; The elements are nodes and the clock signal is sent to the elements/nodes synchronously using a clock trees]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Miller in Carson, because the use of a clock tree distribution minimizes signal delay and keeps clock signals uniform across all parts of a circuit since each recipient of the clock receives a copy of the clock signal synchronously with other recipients of the clock. Regarding claim 2, Carson teaches wherein the network of computational nodes [102, Fig 1] comprises a plurality of rows and a plurality of columns arranged in a rectangular pattern [Paragraph 0040; The nodes are organized in a rectangular design], wherein the plurality of nodes [202, Fig 3] is arranged in one or more of the plurality of rows [Fig 1; Paragraph 0040; Root node labeled “1” is in row 1 and column 1], and wherein the distributing and propagating occur along each row via the plurality of columns [Figs 2 - 3; Paragraphs 0040 - 0041 and 0047; The clock signal is propagated from the root node to other nodes in the array that are not root nodes in a diagonal, vertical, or horizontal manner along the rows and columns]. Regarding claim 3, Carson teaches the plurality of nodes [202, Fig 3] spans two adjacent rows, and wherein the distributing and propagating occur upward along the plurality of columns from a first row of the two adjacent rows and wherein the distributing and propagating also occur downward along the plurality of columns from a second row of the two adjacent rows [Figs 2 – 3; Paragraphs 0042 and 0047; The nodes make up multiple rows of nodes and a clock signal is sent to each node through a root node. The clock signal is provided upward and downward along the rows and columns of nodes]. Miller discloses distributing the clock signal to the plurality of nodes synchronously [Column 4, Lines 27 – 46]. Regarding claim 4, Carson teaches the distributing and propagating [Figs 2 - 3; Paragraphs 0039 – 0041 and 0047; The clock signal is distributed in diagonally or in rows and columns from a root node along the rows and columns to adjacent nodes] occur along the plurality of columns such that each node within each row of nodes receives the clock signal synchronously [Fig 2; Paragraphs 0035 and 0039 – 0041; The node propagate a clock signal through each row in a column and the nodes communicate synchronously. Each node within each node receives the clock signal synchronously with another diagonally aligned node]. Regarding claim 5, Carson teaches the network of computational nodes [102, Fig 1] is arranged in a non-rectangular pattern [Figs 2 - 3; Paragraphs 0039 – 0041 and 0047; Distributing the clock signal along diagonals shows a non-rectangular pattern of the nodes], wherein the respective adjacent nodes receive the clock signal synchronously [Fig 2; Paragraphs 0035 and 0039 – 0041; The node propagate a clock signal through each row in a column and the nodes communicate synchronously. Column 13 shows nodes in rows 2 – 15 of column 15 receive the same clock signal at the same time since they have the same delay], and wherein, during the propagating [Figs 2 - 3; Paragraphs 0040 - 0041 and 0047; The clock signal is propagated from the root node to other nodes in the array that are not root nodes in a diagonal, vertical, or horizontal manner], each of the additional nodes receives the clock signal synchronously with other of the additional nodes based on a number of nodes the clock signal propagates through from one of the respective adjacent nodes [Fig 2; Paragraphs 0035 and 0039 – 0041; The node propagate a clock signal through each row in a column and the nodes communicate synchronously. Column 13 shows nodes in rows 2 – 15 of column 15 receive the same clock signal at the same time since they have the same delay]. Regarding claim 6, Carson teaches the non-rectangular pattern comprises a circular pattern, an oval pattern, a polygon pattern, or an irregular pattern [Figs 2 - 3; The clock delay is not linear going vertically, horizontally, or diagonally showing the pattern is irregular]. Regarding claim 7, Carson teaches receiving a data signal at a receiving node of the network of computational nodes [102, Fig 1; Figs 2 – 5B; Signals are received in nodes of the node array along the lines shown]; and modifying a timing of the data signal based on whether the data signal is sent in a direction of the distributing and propagating [Paragraphs 0052 – 0054; The timing if a signal can be changed based on if the signal is sent along the same direction as the clock or not]. Regarding claim 8, Carson teaches when the data signal is sent in a same direction as the distributing and propagating, the data signal is delayed [Fig 4A; Paragraph 0053 - 0055; Signals in the same direction as the clock will have a delay]. Regarding claim 9, Carson teaches when the data signal is sent in an opposite direction as the distributing and propagating, the data signal is not delayed [Fig 4A; Paragraph 0053 - 0055; Signals in the opposite direction as the clock will have less of a delay or no delay]. Regarding claim 11, Carson teaches selecting an operating mode of each of the nodes of the network of computational nodes [102, Fig 1] based on a location of the node relative to the distributing and propagating [Paragraphs 0052 – 0054; The modes of the nodes, which are the delay times, are based on where the node is, what direction the communication is going, and the direction of the clock signal]. Regarding claim 12, Carson teaches selecting the operating mode of each of the nodes comprises selecting the operating mode based on whether data reception for each node is in a direction of the distributing and propagating [Paragraphs 0052 – 0054; The mode of a node is based on the direction of the distributing and propagation of the clock signal and communication signal]. Regarding claim 13, Carson teaches the operating mode is selected from a set of operating modes comprising a first mode when the data reception for the node is in the direction of the distributing and propagating, a second mode when the data reception for the node is in an opposite direction as the distributing and propagating, and a third mode when adjacent nodes have a clock signal with zero skew [Paragraphs 0044 and 0052 – 0054; The communication signal in the direction of the clock signal is one mode, the communication signal in the opposite direction of the clock signal is another mode, and the third mode if when the skew is eliminated as shown in column 13 in figure 2 where the skew is 14 for multiple nodes]. Regarding claim 14, Carson teaches the clock source [106, Fig 1] comprises a phase locked loop [Paragraph 0035]. Claims 15 – 20 are system claims corresponding to claims 1 – 3 and are rejected using the same prior art and reasoning as claim 1 – 3 above. Carson discloses the system [Fig 1; Paragraph 0035; The node array is part of the system on a wafer]. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carson et al. (WO 2024/040108) referred to as Carson in view of Miller et al. (Pat 9,372,503) referred to as Miller as applied to claim 9 above, and further in view of Belk et al. (Pub. No.: US 2007/0019686) referred to as Belk. Regarding claim 10, Carson teaches providing, from a clock source [106, Fig 1; Paragraph 0035; Item 106 is a clock generator that provides a clock signal to the node array], a clock signal to a subset of nodes [Paragraph 0038; The root nodes in the corners are a subset of nodes in the array] of the network of computational nodes [102, Fig 1]. Miller discloses using a clock tree distribution to distribute a clock signal to nodes synchronously [Column 4, Lines 27 – 46]. However, Carson in view of Miller may not specifically disclose the limitation(s) of when the clock signal at the receiving node is a same clock signal as at a sending node, the data signal is buffered. Belk discloses when the clock signal at the receiving node is a same clock signal as at a sending node, the data signal is buffered [Paragraph 0048; The average buffer fill level being constant shows data is being buffered when the clock signal is the same at the source and destination]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Belk in Carson in view of Miller, because it allows the system to take into account “cell jitter” by looking at the fill level of a buffer overtime before changing any settings in the system due to delays [Paragraphs 0048]. Response to Arguments Applicant's arguments filed 05/02/2026 have been fully considered but they are not persuasive. The applicant argues on pages 10 – 13, with regard to claims 1, 15, and 18, that Carson fails to teach providing a clock signal from a clock source via a clock distribution tree to a plurality of nodes that each receive the clock signal synchronously. The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The combination teaches propagating clock signals among a group of nodes as taught in Carson while also providing the advantages of clock tree distribution of one or more clock signals among groups of nodes as disclosed by Miller. The combination uses aspects of Carson and Miller without completely discarding an entire reference’s teachings. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution. The applicant argues on pages 13 – 14, with regard to claim 4, there is an error in figure 2 of Carson and therefor Carson fails to the teach the limitations of claim 4. After careful consideration of the applicant's arguments the examiner respectfully disagrees. Even if there is an error in figure 2, Carson still teaches the limitations of claim 4. Claim 4 requires each node within each row of the nodes receives the clock signal synchronously. There is no specific identification as to what synchronous limitation is relating to exactly. Carson teaches each node in a row in a column of nodes and receives a clock signal that is synchronous with relation to a diagonal node. For example, The node in row 3 in column 2 receives the clock signal synchronously with the nodes in row 4 column 1, row 2 column 3, and row 1 column 4. The applicant argues on pages 14 – 15, with regard to claims 3, 17, and 20, that Carson fails to teach the using two adjacent rows of nodes as an initial seed line or propagating the clock signal in two different opposing directions away from such a seed line. After careful consideration of the applicant's arguments the examiner respectfully disagrees. The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution. Carson teaches distributing a clock signal to multiple nodes through a root node. The multiple nodes are arranged in columns and rows. Miller discloses distributing a clock signal to multiple nodes or elements using a clock tree where multiple nodes/elements receive the clock signal synchronously. The combination shows nodes, whether they are adjacent or not, can receive the clock signal synchronously. Carson teaches the clock signal propagates to two neighboring nodes. In the example described in paragraphs 0038 and 0039 that root node can be located at a corner of the node array. This does not require the root node to be at the corner of the node array though. The corner of the node array is just one example of where the root node can be. Any node of the node array can be a root node. Paragraph 0039 discloses any signal can propagate south and east or north and west. This shows a root node being somewhere not in the corner would result in the clock signal being propagated both northward and southward diagonally from the root node. The applicant argues on pages 15 – 16 that the rejections of the remaining dependent claims be withdrawn since they are dependent from base claims argued not being taught by Carson. After careful consideration of the applicant's arguments the examiner respectfully disagrees. The examiner has responded to the base claims showing how the prior art teaches the amended limitations. The rejections of the dependent claims are maintained based in part on the rejections of the base claims. The applicant argues on pages 16 – 17, with regard to claim 10, that Belk fails to remedy the deficiencies of Carson and withdraw the rejection of claim 10. After careful consideration of the applicant's arguments the examiner respectfully disagrees The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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Prosecution Timeline

Oct 09, 2024
Application Filed
Feb 20, 2026
Non-Final Rejection mailed — §103
May 20, 2026
Response Filed
Sep 02, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
75%
Grant Probability
82%
With Interview (+7.6%)
3y 1m (~1y 1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 515 resolved cases by this examiner. Grant probability derived from career allowance rate.

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