Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claims 1-21 have been submitted for examination.
Claims 1 16 2 3 4 5 6 7 17 20 21 have been rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 16 2 3 4 5 6 7 17 20 21 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Fujiwara WO 2021/138125 A1 hereinafter 125.
In regard to claims 1 16
125 discloses
A memory comprising: a first error correction code (ECC) decoder circuit configured to correct errors of first data having multiple bits and second data having one or more bits by using the first data, the second data, and a first parity, and generate first error correction results; (Figure 3 Block 1) “The plurality of bits of information may include a plurality of data bits and a plurality of parity bits. The first ECC circuit may receive a first portion of the plurality of data bits and a first portion of the plurality of parity bits, and the second ECC circuit may receive a second portion of the plurality of data bits and a second portion of the plurality of parity bits. The first ECC circuit may locate and correct errors in the first portion of the plurality of data bits based on the first portion of the plurality of parity bits, and the second ECC circuit may locate and correct errors in the second portion of the plurality of data hits based on the second portion of the plurality of parity bits. ” a second ECC decoder circuit configured to correct errors of the first data and third data having one or more bits by using the first data, the third data, and the first parity, (Figure 3 Block 2)” and the second ECC circuit may receive a second portion of the plurality of data bits and a second portion of the plurality of parity bits. The first ECC circuit may locate and correct errors in the first portion of the plurality of data bits based on the first portion of the plurality of parity bits, and the second ECC circuit may locate and correct errors in the second portion of the plurality of data hits based on the second portion of the plurality of parity bits.” and generate second error correction results; and a first selection circuit configured to select one of the first error correction results and the second error correction results.
“The read bits, including the two corrected hits, are then provided to the I/O circuit
322, which reassembles the bits into a sequence including the corrected bits (e.g., ABCDE’F’GH) and
provides it to the DQ pads. In this manner, when the string of bits in the memory array 318 which includes
two adjacent error bits is read, a string of bits with both errors corrected is provided to the DQ pads.”
In regard to claim 2
125 discloses
2. The memory of claim 1, wherein the second data and the third data are read from different memory cells and have an identical value with each other. The apparatus may include a third memory cell disposed along the word line. The third memory cell may be adjacent the second memory cell but not adjacent to the first memory cell. The third memory cell may be coupled to the first ECC circuit. The apparatus may include a fourth memory cell disposed along the word line. The fourth memory cell may be adjacent the third memory cell but not adjacent to the second memory cell, and the fourth memory cell may be coupled to the second ECC circuit.
In regard to claim 3
125 discloses
3. The memory of claim 2, wherein: each of the bits of the second data is more important than each of the bits of the first data, and each of the bits of the third data is more important than each of the bits of the first data. data may be organized based on a number of data bits and parity bits which can correct up to a single error in the data hits. For example, if a group of data, such as the data saved along a row', includes 128 data bits and 8 parity bits, the 8 parity bits may be used to identify and correct up to one error among the 128 data bits. Accordingly, if the 128 data bits include two or more errors then the error correction circuit may not be able to correct the errors in the 128 data bits. One way in which multiple bits can fail is if there is a defect in the chip which affects two memory cells which are adjacent to each other (e.g., two memory cells along the same row, but coupled to adjacent digit lines)
In regard to claim 4
125 discloses
4. The memory of claim 1, wherein the first selection circuit performs a selection operation on the first error correction results and the second error correction results based on a value of a syndrome that is generated by the first ECC decoder circuit. , a row may include i data bits and k parity bits, which may be used to correct up to j of the data hits. During a write operation the parity bits may be generated by an error correction circuit based on the data written to the memory cells of the row. During a read operation the error correction circuit may use the parity bits to determine if the read data bits are correct, and may correct any errors which are found.
In regard to claim 5
125 discloses
5. The memory of claim 4, wherein the first selection circuit selects the second error correction results when the first ECC decoder circuit corrects the second data, and selects the first error correction results when the first ECC decoder circuit does not correct the second data. If a pair of adjacent bits fail, then one of the failed bits will end up read out to the first error correction circuit, while the other of the failed bits will end up read out. to the second error correction circuit. In this manner, both bits may be corrected, since each error correction circuit receives one of the two adjacent failed bits
In regard to claim 6
125 discloses
6. The memory of claim 1, further comprising a first ECC encoder circuit configured to generate the first parity. as part of a write operation an ECC control circuit 120 may receive 128 bits of data from the IO circuit and may generate 8 parity bits based on those 128 data bits. The 128 data bits and the 8 parity bits (e.g., 136 total bits) may be written to the memory array 118
In regard to claim 7
125 discloses
7. The memory of claim 6, wherein the first ECC decoder circuit, the second ECC decoder circuit, and the first ECC encoder circuit use an identical H matrix. the first ECC circuit 646 may receive a total of 128 data bits and 8 parity bits from memory cells which are not adjacent to each other. The first ECC circuit 646 may correct the 128 bits of data based on the 8 parity bits and provide the 128 corrected bits. In a similar manner, the second ECC circuit 645 may receive 128 data bits and 8 parity bits from non-adjacent memory cells in the two row sections of the second portion 643 and provide 128 corrected bit
In regard to claim 17
125 discloses
17. The operating method of claim 16, further comprising: prior to the reading of the first to third data and the reading of the parity, generating a write parity by using write data; writing some bits of the write data in the multiple first memory cells; redundantly writing remaining bits of the write data in the one or more second memory cells and the one or more third memory cells; and writing the write parity in the multiple fourth memory cells.
a plurality of memory cells arranged along the word line, a first error correction code (ECC) circuit which manages information in odd numbered ones of the plurality of memory cells, and a second ECC circuit which manages information in even numbered ones of the plurality of memory cells.
In regard to claim 20
125 discloses
20. The operating method of claim 17, wherein each of the remaining bits of the write data is more important than each of the some bits of the write data. The ECC control circuit 120 may use the 8 parity bits to determine if there are any errors in the 128 read data bits, and may correct them if any are found
In regard to claim 21
125 discloses
21. The operating method of claim 16, wherein the selecting one of the first error correction results and the second error correction results includes selecting the second error correction results when the second data are corrected in the first error correction operation, and selecting the first error correction results when the second data are not corrected in the first error correction operation. If a pair of adjacent bits fail, then one of the failed bits will end up read out to the first error correction circuit, while the other of the failed bits will end up read out. to the second error correction circuit. In this manner, both bits may be corrected, since each error correction circuit receives one of the two adjacent failed bits. In some embodiments, information may be read serially from groups including non-adjacent memory cells (e.g., data may be read first from even digit lines then from odd word lines) to reduce the number of error correction circuits which are required.
Allowable Subject Matter
Claims 8-15, 18, 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure See PTO 892.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMINE RIAD whose telephone number is (571)272-8185.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bonzo Bryce can be reached 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.R./
/Amine Riad/
Primary Examiner