Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to application filed 01/30/25. Claims 1 – 20 have been examined and are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1 – 16 of U.S. Patent No. US 20240220228 A1. Although the claims at issue are not identical, they are not patentably distinct from each other because recite significantly as the parent application and are no more than and obvious variation thereof.
18/911312
US 20240220228 A1
Claim 1.
[AltContent: arrow][AltContent: arrow]a first processor and a second processor, both to access a multi-layer memory comprising multiple layers arranged in a hierarchy, the layers comprising at least (i) one or more first layers and (ii) one or more second layers that are higher in the hierarchy than the one or more first layers and serve as a cache for the one or more first layers, wherein the first processor is to execute software code from the one or more first layers of the multi-layer memory, and wherein the second processor is to update the software code from an existing version to an updated version, by:
[AltContent: arrow]loading the updated version to the one or more second layers of the multi-layer memory; and invalidating the existing version in the one or more first layers, thereby causing a subsequent attempt to read the existing version from the one or more first layers to result in a cache-miss event and thus forcing the second processor to fetch the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.
Claim 1.
a first processor, to manage communication over the peripheral bus by executing bus-maintenance software code, the bus-maintenance software code being executed from one or more first layers of a multi-layer memory; and a second processor, to update the bus-maintenance software code from an existing version to an updated version, by: loading the updated version to one or more second layers of the multi-layer memory, higher in hierarchy than the one or more first layers; and invalidating the existing version in the one or more first layers, thereby forcing fetching of the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.
Claim 8.
8. The peripheral device according to claim 1, wherein the second processor is to define the bus-maintenance software code as non-cacheable for the one or more first layers, thereby causing the first processor to execute the updated version directly from the one or more second layers while the second processor is fetching the updated version is being fetched to the one or more first layers.
Regarding the inclusion of claim 8 for the mapping, while the language “ cache miss” used in the instant claimed invention may be different, the parent case mentions the term “non-cacheable” and are equivalent in meaning and functionality and hence is also being taught by the parent claims in a later dependent claim.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chuck Kendall whose telephone number is 571-272-3698. The examiner can normally be reached on 10:00 am - 6:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung Sough can be reached on 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUCK O KENDALL/
Primary Examiner, Art Unit 2192
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