DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/5/2026 have been fully considered but they are not persuasive. Applicant argues that Kong does not teach or suggest “the driving circuit is configured to sense an LX node voltage of the output circuit to determine whether at least one of a first body diode included in the first switch or a second diode included in the second switch is turned on or not, and based thereon, control a dead time corresponding to one of the first switch or the second switch”. The examiner does not find this argument to be persuasive. The Kong reference in paragraphs 0057 and 0059 discloses a dead time controller and zero current detector, specifically Kong states these components and a gate driver are components included in the buck converter of the related art and the functions thereof are the same as the related art so that a specific description will be omitted. Looking at relevant prior art such as Ruan et al. (US 2020/0389090) which shows a similar buck converter in figure 1A, the voltage between the two switches SW is provided to a feedback circuit FB CKT element 120. Later in Ruan, figure 6, one can see that the SW signal is provided to a comparator 602 and the result is then used to control the switches HS and LS. Therefore, it is well known in the art how a buck converter is used and that the circuit of Kong is a buck converter and would provide the functionality of “the driving circuit is configured to sense an LX node voltage of the output circuit to determine whether at least one of a first body diode included in the first switch or a second diode included in the second switch is turned on or not, and based thereon, control a dead time corresponding to one of the first switch or the second switch”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kong et al. (US 2020/0266707 A1 hereinafter Kong).
In regards to claim 9, Kong discloses a power supply (see figure 1, buck converter) comprising:
an output circuit including a first switch and a second switch configured to charge or discharge power input through an input terminal thereof to output a power output through an output terminal thereof (see figure 1, output circuit with first switch 111 and second switch 113); and
an output controller including a driving circuit configured to control charging or discharging of the output circuit (see figure 1, dead time control 173 connected to node Vx),
wherein the driving circuit is configured to sense an LX node voltage of the output circuit to determine whether at least one of a first body diode included in the first switch or a second body diode included in the second switch is turned on or not, and based thereon, control a dead time corresponding to one of the first switch or the second switch, the LX node between the first switch and the second switch. (see figure 1, dead time control 173 connected to node Vx and controls switches 111 and 113).
In regards to claim 10, as recited in claim 9, Kong further discloses wherein the driving circuit comprises a dead time controller configured to control the dead time corresponding to one of the first switch or the second switch, based on the LX node voltage sensed from the output circuit, a reference voltage, and a switch control reference signal output from a control circuit of the driving circuit (see figure 1, dead time control 173 is controlled by node Vx and controls switches 111 and 113).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2022/0284855 A1 hereinafter Kang) in view of Kong.
In regards to claim 1, Kang discloses a display apparatus comprising:
a display panel configured to display an image (see figure 1, display panel 14);
a panel driver configured to drive the display panel (see figure 1, data driver 12); and
a power supply circuit for supplying power to the display panel (see figure 1, power source 16).
However, Kang fails to disclose a power supply circuit including an output circuit and an output controller, the output circuit including a first switch and a second switch configured to charge or discharge power input through an input terminal thereof to output a power output through an output terminal thereof, and the output controller including a driving circuit configured to control charging or discharging of the output circuit, wherein the driving circuit is configured to sense an LX node voltage of the output circuit to determine whether at least one of a first body diode included in the first switch or a second body diode included in the second switch is turned on or not, and based thereon, control a dead time corresponding to one of the first switch or the second switch, the LX node between the first switch and the second switch.
Kong teaches a power supply circuit including an output circuit and an output controller (see figure 1), the output circuit including a first switch and a second switch configured to charge or discharge power input through an input terminal thereof to output a power output through an output terminal thereof (see figure 1, switch 111 and switch 113), and the output controller including a driving circuit configured to control charging or discharging of the output circuit (see figure 1 and paragraph 0042, output voltage controller 170),
wherein the driving circuit is configured to sense an LX node voltage of the output circuit to determine whether at least one of a first body diode included in the first switch or a second body diode included in the second switch is turned on or not, and based thereon, control a dead time corresponding to one of the first switch or the second switch, the LX node between the first switch and the second switch. (see figure 1, dead time control 173 is connected to node Vx).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kang and include the buck converter as taught by Kong, thereby using known techniques to yield predictable results.
In regards to claim 2, as recited in claim 1, Kong further discloses wherein the driving circuit comprises a dead time controller configured to control the dead time corresponding to one of the first switch or the second switch, based on the LX node voltage sensed from the output circuit, a reference voltage, and a switch control reference signal output from a control circuit of the driving circuit (see figure 1, dead time control 173 is controlled by node Vx and controls switches 111 and 113).
In regards to claim 13, Kang discloses a display apparatus comprising:
a display panel configured to display an image (see figure 1, display panel 14).
However, Kang fails to disclose a power supply circuit for supplying power to the display panel, the power supply circuit including an output circuit and an output controller, the output circuit including a first switch and a second switch connected in series between an input terminal and a ground terminal, a node between the first switch and the second switch being connected to an output terminal through an inductor, and the output controller configured to sense a voltage at the node and control a dead time state of one of the first switch or the second switch based on the inductor voltage sensed.
Kong teaches a power supply circuit (see figure 1, buck converter) for supplying power to the display panel, the power supply circuit including an output circuit and an output controller, the output circuit including a first switch and a second switch connected in series between an input terminal and a ground terminal (see figure 1, output circuit with first switch 111 and second switch 113, between Vin and ground), a node between the first switch and the second switch being connected to an output terminal through an inductor (see figure 1, node Vx connected to inductor 123), and the output controller configured to sense a voltage at the node and control a dead time state of one of the first switch or the second switch based on the inductor voltage sensed (see figure 1, dead time control, connected to node Vx).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kang and include the buck converter as taught by Kong, thereby using known techniques to yield predictable results.
In regards to claim 14, as recited in claim 13, Kong further teaches wherein the output controller is configured to: determine whether at least one of a first body diode included in the first switch or a second body diode included in the second switch is turned on based on the voltage at the node sensed (see figure 1, switch 111 and switch 113); and
control the dead time state of the one of the first switch or the second switch based on a result of determining whether at least one of the first body diode included in the first switch or the second body diode included in the second switch is turned on (see figure 1, dead time control 173 is connected to node Vx).
In regards to claim 15, as recited in claim 14, Kong further teaches wherein in a case that the power supply circuit operates in a first mode, and in response to determining that the second body diode included in the second switch is on a turn-on state, the output controller is configured to turn on the first switch or the second switch to end a dead time state of the first switch or the second switch (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
In regards to claim 16, as recited in claim 14, Kong further teaches wherein in a case the power supply circuit operates in a second mode, and in response to determining that the first body diode included in the first switch is on a turn-on state, the output controller is configured to turn on the first switch to end a dead time state of the first switch (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
In regards to claim 17, as recited in claim 14, Kong further teaches wherein in a case the power supply circuit operates in a second mode, and in response to determining that the second body diode included in the second switch is on a turn-on state, the output controller is configured to turn on the second switch to end a dead time state of the second switch (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
In regards to claim 18, as recited in claim 14, Kong further teaches wherein in a case the power supply circuit operates in a second mode and the first switch is turned off, in response to determining that the second body diode included in the second switch is in a turn-off state, the output controller is configured to turn on the second switch after a fixed dead time (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
In regards to claim 19, as recited in claim 13, Kong further teaches wherein the output controller includes a first output control circuit and a second output control circuit, the first output control circuit configured to control an operation state of the second output control circuit based on a current and a voltage at the output terminal of the output circuit, and the second output control circuit configured to generate a first switch control signal and a second switch control signal for controlling switching timing of each of the first switch and the second switch, based on a signal output from the first output control circuit (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
In regards to claim 20, as recited in claim 19, Kong further teaches wherein the second output control circuit is configured to forcibly end a dead time state of each of the first switch or the second switch based on a current and a voltage at the input terminal and the voltage at the node sensed (see paragraph 0046, when a PWM signal is a high signal, the switching unit 115 turns on the PMOS power transistor 111 and turns off the NMOS power transistor 113 by a driving signal. Further, for example, when the PWM signal is a low signal, the switching unit 115 turns off the PMOS power transistor 111 and turns on the NMOS power transistor 113).
Allowable Subject Matter
Claims 3-8, 11, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628