DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10-11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2013/0141316) in view of Chun (US 2021/0134215).
Regarding claims 1, Lee teaches A display device comprising:
a display panel on which a data line intersects a gate line, and a plurality of subpixels are arranged (Figs. 1-2);
a data driver configured to supply a data signal to the data line (Fig. 2 data driver 120);
a gate driver configured to supply a scanning signal and an emission control signal to the gate line ( Fig. 2 driver 130 [0048-0049]),
wherein each of the plurality of subpixels comprises a subpixel circuit, the subpixel circuit comprising (Figs. 2-5):
a driving transistor configured to drive a light-emitting element (Fig. 3 transistorTdr);
a first transistor controlled by the scanning signal, the first transistor electrically connected to a gate node and a drain node of the driving transistor (Fig. 3 transistor T2);
a second transistor controlled by the scanning signal, the second transistor electrically connected to a source node of the driving transistor and the data line (Fig. 3 transistor Tsw);
a third transistor controlled by the emission control signal, the third transistor electrically connected to a high potential voltage supply line (Fig. 3 Vdd) and the source node of the driving transistor (Fig. 3 transistor T1);
a fourth transistor controlled by the emission control signal, the fourth transistor electrically connected to the drain node of the driving transistor and the light- emitting element (Fig. 3 transistor Tem); and
a fifth transistor controlled by the scanning signal, the fifth transistor electrically connected to an initializing voltage supply line and the light-emitting element (Fig. 3 transistor T3). Although Lee teaches the limitations as discussed above, he fails to teach wherein, in a driving time of subpixels driven through different gate lines, an emission period has a same time interval, and a holding period has a different time interval depending on a gate-line position.
However in the field of driving a display device, Chun teaches light-emitting display where , in a driving time of subpixels driven through different gate lines, an emission period has a same time interval, and a holding period has a different time interval depending on a gate-line position (In Figs. 9,13,18 and 20 Chun shows two holding periods. Holding period 1 which takes place after a sampling period and Holding period 2 which takes place after a data write DW period. This Figures show Holding period 1 and Holding period 2 being different based on the scan line number while the emission period starts at the same time after holding period 2.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with the driving method as taught by Chun. This combination improve a display experience by preventing luminance non-uniformity due to block driving as taught by Chun [0007].
Regarding claim 2, Lee teaches a storage capacitor electrically connected to the high potential voltage supply line and the gate node of the driving transistor (Fig. 3 capacitor C1).
Regarding claim 3, Lee teaches herein gate nodes of the first transistor, the second transistor, and the fifth transistor are connected to a single scanning signal line that supplies the scanning signal (Fig. 3 Transistor Tsw and T2-T3), and gate nodes of the third transistor and the fourth transistor are connected to a single emission control signal line that supplies the emission control signal (Fig. 3 transistors Tem and T1).
Regarding claim 4, Lee teaches wherein an emission period ([0096-0098]), and during the initializing period, an initializing voltage is applied to the gate node of the driving transistor ([0085-0088]), and a high potential voltage is applied to the source node of the driving transistor ([0092] teaches node VN2 is high-potential voltage Vdd).
Regarding claim 5, Lee teaches wherein during the initializing period, the initializing voltage is applied to the gate node of the driving transistor through the fifth transistor, the fourth transistor, and the first transistor ([0085-0088]).
Regarding claim 6, Lee teaches wherein during a sampling period, the first transistor, the second transistor, and the fifth transistor are turned on by the scanning signal having a turn-on level voltage ([0092]), and the third transistor and the fourth transistor are turned off by the emission control signal having a turn-off level voltage ([0096]).
Regarding claim 7, Lee teaches wherein during the sampling period, a data voltage is applied to the source node of the driving transistor([0092] node VN2 may be Vdata), and a voltage on the gate node of the driving transistor changes from the initializing voltage applied to the gate node of the driving transistor during the initializing period into a tracking voltage ([0094] voltage at VN1 may be Vdata -Vth).
Regarding claim 10 Lee teaches wherein during the holding period, a voltage on the drain node of the driving transistor is increased by a conduction current of the driving transistor ([0101-0102]).
Regarding claim 11, Lee teaches wherein during the emission period, the first transistor, the second transistor and the fifth transistor are turned off by the scanning signal having the turn-off level voltage, and the third transistor and the fourth transistor are turned on by the emission control signal having the turn-on level voltage([0098-0099]).
Regarding claim 14, Lee teaches wherein at least one of the data line, the gate line, the initializing voltage supply line, and the high potential voltage supply line has a zigzag shape comprising a plurality of bent portions (Figs. 3 and 5).
Regarding claim 15, Chun teaches wherein in the driving time of the plurality of subpixels driven through different gate lines, the emission period has a same time interval (In Figs. 9,13,18 and 20 emission period have the same time period for each scan line).
Regarding claim 16, Chun teaches wherein in the driving time of the plurality of subpixels driven through different gate lines, the initializing period, the sampling period, have a same time interval, (In Figs. 9,13,18 and 20 initializing period and sampling period have the same time period for each scan line).
Claims 8-9, 12-13, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2013/0141316) in view of Chun (US 2021/0134215) and Chang (US 20190130832).
Regarding claims 8, Lee in view of Chun teaches wherein during the sampling period, the tracking voltage corresponds to a difference between the data voltage and an a threshold voltage of the driving transistor([0094] voltage at VN1 may be Vdata -Vth), and a gate-source potential difference of the driving transistor corresponds to a magnitude of the threshold voltage of the driving transistor ([0056-0057]). Although Lee teaches the limitations as discussed above, he fails to explicitly teach the tracking voltage is an absolute voltage of a threshold voltage.
However in the field of driving a display pixel, Chang teaches a method where a tracking voltage is an absolute voltage of a threshold voltage ([0126] teaches when the driving transistor is diode connected the gate to drain potential is a difference between the data voltage and the absolute value of the threshold voltage.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device and method as taught by Lee with the driving method as taught by Chun and the threshold voltage method as taught by Chang. This combination would provide a display with an improved image quality as expressed by Chang [0002].
Regarding claim 9, Lee in view of Chun teach the limitations as discussed above but fails to teach wherein during the holding period, the first transistor, the second transistor, and the fifth transistor are turned off by the scanning signal having the turn-off level voltage , and during the holding period, the third transistor and the fourth transistor are turned off by the emission control signal having the turn-off level voltage.
However in the field of driving a display pixel, Chang teaches a the holding period, the first transistor(Fig. 6 T2), the second transistor (Fig. 6 T6), and the fifth transistor (Fig. 6 T1) are turned off by the scanning signal having the turn-off level voltage ([0129]) , and during the holding period, the third transistor (Fig. 6 T4) and the fourth transistor (Fig. 6 T3) are turned off by the emission control signal having the turn-off level voltage ([0129]).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device and method as taught by Lee the driving method as taught by Chun and the threshold voltage method as taught by Chang. This combination would provide a display with an improved image quality as expressed by Chang [0002].
Regarding claim 12, Lee and view of Chun teach wherein during the emission period, a high potential voltage is applied to the source node of the driving transistor through the third transistor that is turned on, the voltage on the gate node of the driving transistor corresponds to a voltage difference between the data voltage and a threshold voltage of the driving transistor, and a current flows to the light-emitting element through the driving transistor ([0098-0102]). Although Lee teaches the limitations as discussed above, he fails to explicitly teach the tracking voltage is an absolute voltage of a threshold voltage.
However in the field of driving a display pixel, Chang teaches a method where a tracking voltage is an absolute voltage of a threshold voltage ([0126] teaches when the driving transistor is diode connected the gate to drain potential is a difference between the data voltage and the absolute value of the threshold voltage.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device and method as taught by Lee the driving method as taught by Chun and the threshold voltage method as taught by Chang. This combination would provide a display with an improved image quality as expressed by Chang [0002].
Regarding claim 13, Lee teaches wherein during the emission period, a magnitude of the current flowing to the light-emitting element is determined irrespective of the threshold voltage of the driving transistor([0056-0057]).
Regarding claim 22, Lee teaches a method of driving a display device comprising subpixels each comprising a light-emitting element and a driving transistor, the method comprising: an initialization period of applying a high potential voltage to a source node of the driving transistor and applying an initializing voltage to a gate node of the driving transistor([0085-0090] and [0092] teaches node VN2 is high-potential voltage Vdd); and a sampling period of applying a data voltage to the source node of the driving transistor, ([0092] node VN2 may be Vdata)
wherein in the sampling period of applying the data voltage, the gate node of the driving transistor has a voltage at which a threshold voltage of the driving transistor is subtracted from the data voltage([0094] voltage at VN1 may be Vdata -Vth), and a gate-source potential difference of the driving transistor corresponds to a magnitude of the threshold voltage([0056-0057]). Although Lee in view of Chun teach the limitations as discussed above, he fails to teach wherein, in a driving time of subpixels driven through different gate lines, an emission period has a same time interval, and a holding period has a different time interval depending on a gate-line position.
However in the field of driving a display device, Chun teaches light-emitting display where comprising a holding period and an emission period, wherein a driving time of subpixels driven through different gate lines, an emission period has a same time interval, and a holding period has a different time interval depending on a gate-line position (In Figs. 9,13,18 and 20 Chun shows two holding periods. Holding period 1 which takes place after a sampling period and Holding period 2 which takes place after a data write DW period. This Figures show Holding period 1 and Holding period 2 being different based on the scan line number while the emission period starts at the same time after holding period 2.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with the driving method as taught by Chun. This combination improve a display experience by preventing luminance non-uniformity due to block driving as taught by Chun [0007]. Although Lee in view of Chun teach the limitations as discussed above, he fails to explicitly teach the tracking voltage is an absolute voltage of a threshold voltage.
However in the field of driving a display pixel, Chang teaches a method where a tracking voltage is an absolute voltage of a threshold voltage ([0126] teaches when the driving transistor is diode connected the gate to drain potential is a difference between the data voltage and the absolute value of the threshold voltage.).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device and method as taught by Lee with the driving method as taught by Chun and the threshold voltage method as taught by Chang. This combination would provide a display with an improved image quality as expressed by Chang [0002].
Regarding claim 23, Lee teaches wherein in the sampling of applying the data voltage, a first transistor connected to a drain node and the gate node of the driving transistor is turned on ([0158]).
Regarding claim 24, Lee teaches wherein in the initialization period of applying the high potential voltage and the initializing voltage, the initializing voltage is applied to the gate node of the driving transistor through the first transistor(Fig. 3-5 transistor T2 is used during initializing period, sampling period, and holding period).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00.
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/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
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