DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reissue Applications
This application seeks to reissue US Patent No. 11,470,233 (“the ‘233 patent”). By preliminary amendment, claim 1 has been amended. Claims 1-26 are pending. This is a broadening reissue application.
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 11,470,233 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Objection, 37 CFR 1.173 – No Description of Support
The application is objected to for failing to conform to the requirements of 37 CFR 1.173(c), which requires that claim amendments be “accompanied by an explanation of the support in the disclosure of the patent for the amendment (i.e., support for all changes made in the claim(s), whether insertions or deletions).” MPEP 1453 II. The applicant has not provided an explanation of support for the broader invention that is recited in amended claim 1. Correction is required.
Objection, 37 CFR 1.173 – Improper Amendment
The application is objected to for failing to conform to the requirements of 37 CFR 1.173(d), which requires that when a claim in a reissue application is amended, “matter to be omitted by reissue must be enclosed in brackets.” Amended claim 1 shows omissions with strikethrough. Correction is required. Please refer to MPEP 1453.
Claim Objections
Claim 8 is objected to because of the following informalities: claim 8 recites “a third second input” on line 4 of the claim. Claim 8 of the patent simply recited “a third input” in this line. Correction is required.
Claim Rejections - Res Judicata
Claims 1-26 are rejected on the grounds of res judicata. A rejection under res judicata is appropriate for a claim that “is not patentably distinct from a claim that was previously rejected if the rejection was affirmed on appeal and the decision on appeal became final.” MPEP 2190 II.
The instant application is for the reissue of the ‘233 patent, which issued from US Application 17/145,740. This application was a continuation of US Application 15/910,567 (“the ‘567 application”). During prosecution of the ‘567 application, the examiner’s rejections in the 06/02/2020 final Office action were affirmed on appeal. See the 09/29/2022 Patent Board Decision (the “PTAB Decision”) in the ‘567 application, which affirmed “the Examiner’s rejection of independent claims 1, 11, and 19 under 35 U.S.C. § 103 as being unpatentable over Mizosoe in view of Shimizu, likewise with the rejection of dependent claims 2-5, 7-9, 12-14, 17, and 20.” PTAB Decision at 6-7. The rejections of claims 10 and 18 were also upheld. Id. at 7-8.
The ‘567 application was subsequently abandoned on 12/15/2022, and no civil action or appeal to the U.S. Court of Appeals for the Federal Circuit was filed. This decision on appeal in the ‘567 application is therefore final. See MPEP 1209.
The claims of the instant application are not patentably distinct from claims in the ‘567 application. Claim 1 of the instant application is compared below with claims 1 and 19 of the ‘567 application:
18/911,885
15/810,567 (02/19/2020 claims)
1. A hub interface circuit comprising:
Claim 19: [A system comprising] a hub interface circuit
a clock generator circuit having an output;
Claim 19: a hub interface circuit including: a clock generator
a frame sync generation circuit having an output;
Claim 19: the hub interface circuit including frame sync generation circuitry
transceivers having a first input coupled to the output of the clock generator circuit, a second input coupled to the output of the frame sync generation circuit
Claim 19: a plurality of transceivers, each of the transceivers configured to: encode the clock signal and a frame sync signal in control information
wherein the hub interface circuit is configured to: receive transmissions from a first serial interface circuit and a second serial interface circuit;
Claim 19: a plurality of serial interface circuits, each of the serial interface circuits configured to bidirectionally communicate with the hub interface circuit
transmit control information to the first serial interface circuit and the second serial interface circuit; and
Claim 19:each serial interface circuit receives control information transmitted by the hub interface circuit
encode a clock signal from the output of the clock generator circuit and a frame sync signal from the second output of the frame sync generation circuit into the control information, the frame sync signal indicative of (a) a timing of video data capture by a first camera and a second camera and (b) a time to receive the transmissions from the first serial interface circuit and the second serial interface circuit.
Claims 1 and 19: encode a clock signal [from the clock generator] and a frame sync signal [from the frame sync generation circuitry] in the control information, the frame sync signal indicative of (a) a timing of video data capture by the first camera and the second camera and (b) a time to receive the transmissions from the first serial interface circuit and the second serial interface circuit.
The invention that is recited in claim 1 differs from the claims of the ‘567 application only in the following language: “an image processor interface circuit having an input and an output” and that the transceivers have “a third input coupled to the output of the image processor interface circuit, and an output coupled to the input of the image processor interface circuit.” This difference amounts to only an obvious variant of the claims of the ‘567 application, and thus claim 1 is not patentably distinct from claims 1 and 19 of the ‘567 application.
The same Mizosoe reference that was relied upon in the rejections in the ‘567 application discloses “an image processor interface circuit having an input and an output.” See Mizosoe Fig. 7: 504 and ¶¶ 47-50. Mizosoe also discloses transceiver that have “a third input coupled to the output of the image processor interface circuit, and an output coupled to the input of the image processor interface circuit.” This claim limitation requires transceivers that have bi-directional communications with the image processor circuit. This is disclosed by Mizosoze. See Fig. 7: 5021-5031, 5022-5032, and 5023-5033, and ¶¶ 47-49. The decoder-expansion circuits are transceivers because they transmit and receive information. See id. As is shown in Fig. 7, these transceivers have an input coupled to the image processing circuit 504, and an output coupled to the same image processor. Accordingly, this disclosure in Mizosoe meets the requirements of this claim language.
It would have been obvious to a skilled artisan before the effective filing date of the claimed invention to modify the claims of the ‘567 application to include these teachings in Mizosoe, the rationale being to enable proper decoding of the image that is received from the cameras. The POSITA would recognize that providing separate, dedicated decoding hardware, such as that depicted in Mizosoe Fig. 7, would result in a system with improved performance.
Independent claims 8, 14, and 20 recite similar features and are rejected under res judicata as described above. The dependent claims of this application all correlate to claims that were upheld on appeal in the ‘567 application, and are likewise rejected.
Because claims 1-26 are only an obvious variant of (that is, are not patentably distinct from) claims that were affirmed in an appeal decision that is final, the claims are rejected under res judicata. See MPEP 2190 II.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the term “the second output of the frame sync generation circuit.” This term lacks antecedent basis in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-26 are rejected under 35 U.S.C. 103 as being unpatentable over Mizosoe, US 20130287144 in view of Shimizu, JP2001282714 (see translation that was provided in the 06/02/2020 final Office action in the ‘567 application).
Claim 1: The Mizosoe-Shimizu combination that was described in the 06/02/2020 final Office action in the ‘567 application renders claim 1 obvious. See ‘567 final action at 4-21. As described under the res judicata rejection above, this rejection was affirmed on appeal, and the decision affirming this rejection has become final.
The Mizosoe-Shimizu combination discloses a hub interface circuit (Mizosoe Fig. 7 and ¶¶ 47-51 show that control 5 is a hub interface circuit )
comprising: a clock generator circuit having an output (Mizosoe ¶132 and Fig. 26: reference clock generating part 51 is a clock generator circuit with an output);
a frame sync generation circuit having an output (Mizosoe ¶132 and Fig. 26: time control packet generation part 53 generates frame sync information, therefore this is a frame sync generation circuit);
an image processor interface circuit having an input and an output (Mizosoe Fig. 26: 504)
transceivers having a first input coupled to the output of the clock generator circuit, a second input coupled to the output of the frame sync generation circuit, a third input coupled to the output of the image processor interface circuit, and an output coupled to the input of the image processor interface circuit (Misozoe Fig. 26 – the decoder/expansion circuitry 5021-5023 and 5031-5033 are transceivers in that they transmit and receive data. These circuits are coupled, via the bus that is depicted in Fig. 25, do each circuit in the manner required by this claim limitation);
wherein the hub interface circuit is configured to:
receive transmissions from a first serial interface circuit and a second serial interface circuit (Transmissions are received from LAN interface circuits. Mizosoe ¶¶ 132-134. Shimizu discloses receiving transmission from cameras that are connected to a hub via serial interface circuits. Shimizu ¶¶12-13 and 39-41.);
transmit control information to the first serial interface circuit and the second serial interface circuit; and encode a clock signal from the output of the clock generator circuit and a frame sync signal from the second output of the frame sync generation circuit into the control information, the frame sync signal indicative of (a) a timing of video data capture by a first camera and a second camera and (b) a time to receive the transmissions from the first serial interface circuit and the second serial interface circuit (A Synch packet and DelayResp packets together form control information that is generated to synchronize transmission between the server and client. Mizosoe ¶110. The DelayResp packet acts to indicate a time to receive transmission from the interface circuits. Id. ¶¶ 91 and 110, and Figures 13 and 15. Likewise, the control information encodes the clock signal from the generation part 51. Id. ¶¶ 62-65. As such, Mizosoe teaches this claim limitation. See also the 09/29/2022 Decision on appeal in the ‘567 application at 4-6, in which it was found that the Mizosoe-Shimizu combination taught a substantially similar claim limitation.).
Motivation to combine Mizosoe and Shimizu was given by in the 06/02/2020 final Office action in the ‘567 application. In particular, the skilled artisan would have found it obvious to include the teachings of Shimizu in the system of Mizosoe in order to ensure that images are simultaneously captured and transmitted. See 06/02/2020 final Office action in the ‘567 application pg. 6.
Claim 2: The Mizosoe-Shimizu combination discloses that the first serial interface circuit and the second serial interface circuit each include: a clock recovery circuit configured to extract the clock signal from the control information received from the hub interface circuit (Mizosoe ¶¶91-95, Shimizu Fig. 1 and 7, and ¶¶12-13 and 39-41. See the 06/02/2020 final Office action in the ‘567 application at 6-7 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 3: The Mizosoe-Shimizu combination discloses that the first serial interface circuit and the second serial interface circuit include clock generation circuitry configured to generate a clock signal based on the clock signal extracted from the control information (Mizosoe ¶¶85 and 91-95. See the 06/02/2020 final Office action in the ‘567 application at 6-7 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 4: Mizosoe-Shimizu discloses that the first serial interface circuit and the second serial interface circuit are configured to provide a clock signal to the first camera and the second camera (Mizosoe ¶99. See the 06/02/2020 final Office action in the ‘567 application at 8 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 5: Mizosoe-Shimizu discloses that the first serial interface circuit and the second serial interface circuit are configured to extract the frame sync signal from the control information (Mizosoe ¶¶ 110 and 132-133. See the 06/02/2020 final Office action in the ‘567 application at 9 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 6: Mizosoe-Shimizu discloses that the first serial interface circuit and the second serial interface circuit are configured to provide the frame sync signal extracted from the control information to the first camera and the second camera (Mizosoe ¶¶ 90-91, 9697, and 136. See the 06/02/2020 final Office action in the ‘567 application at 9 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 7: Mizosoe-Shimizu discloses that the first serial interface circuit and the second serial interface circuit are configured to transmit video data to the hub interface circuit, the video data comprising video frames synchronized to the frame sync signal extracted from the control information (Mizosoe ¶¶ 53-55, 119, and 132-135. See the 06/02/2020 final Office action in the ‘567 application at 10 (the position of which is adopted in this rejection), as well as the PTAB Decision affirming this rejection at 6-7).
Claim 8: see rejection of claim 1 above. Claim 8 closely corresponds to claims 11 and 19 of the ‘567 application, and is likewise rejected under res judicata for reasons given above.
The “receiver” that is recited in claim 8 corresponds to the “transceivers” that are recited in claim 1, and the limitations of claim 8 are addressed in the rejection of claim 1. The receiver in Mizosoe-Shimizu therefore includes a receiver having the claimed first, second, and third inputs (Mizosoe Fig. 7, with input from the serial interfaces 5011-5013), and configured to transmit control information as required in claim 8. See above. Mizosoe-Shimizu also includes an input for receiving transmissions from a serial interface circuit. See Mizosoe Fig. 7.
Claims 9-13 see rejection of claims 1-6, respectively.
Claim 14: see rejection of claims 1 and 8 above. Claim 14 closely corresponds to claims 11 and 19 of the ‘567 application, and is likewise rejected under res judicata as described above.
As with the “receiver” in claim 8, the “transmitter” in claim 14 corresponds to the transceiver in claim 1. The grounds described in the rejection of claim 1 meet the requirements of claim 14, as Mizosoe-Shimizu teaches a transmitter having the claimed first and second output (Mizosoe Fig. 7 and Fig. 26) and configured to transmit the control information as recited in claim 14.
Claims 15-19: see rejection of claims 1-6, respectively.
Claim 20 see rejection of claim 1. Claim 20 closely correlates to claim 11 of the ‘567 application, and is likewise rejected under res judicata as described above. Mizosoe-Shimizu discloses a transceiver comprising:
a first input for receiving a clock signal (Mizosoe Fig. 26: the transceiver receive a clock signal from the generation part 51);
a second input for receiving a frame synch signal (Mizosoe Fig. 26: time control packet generating part 53 transmits the frame synch signal to the transceiver);
a third input for receiving transmissions from a serial interface circuit (Mizosoe Fig. 7);
a first output for transmitting control information (see rejection of claim 1 showing that the hub circuit, via the transceiver, includes this first output);
a second output coupled to an image processor interface circuit (Mizosoe Fig. 7);
wherein the transceiver is configured to: receive transmissions from the serial interface circuit; transmit control information to the serial interface circuit; and encode the clock signal and the frame sync signal into the control information, the frame sync signal indicative of (a) a timing of video data capture by a camera and (b) a time to receive the transmissions from the serial interface circuit (A Synch packet and DelayResp packets together form control information that is generated to synchronize transmission between the server and client. Mizosoe ¶110. The DelayResp packet acts to indicate a time to receive transmission from the interface circuits. Id. ¶¶ 91 and 110, and Figures 13 and 15. Likewise, the control information encodes the clock signal from the generation part 51. Id. ¶¶ 62-65. As such, Mizosoe teaches this claim limitation. See also the 09/29/2022 Decision on appeal in the ‘567 application at 4-6, in which it was found that the Mizosoe-Shimizu combination taught a substantially similar claim limitation.).
Claims 21-26: see rejection of claims 2-7, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J HANCE whose telephone number is (571)270-5319. The examiner can normally be reached M-F 11:00am-7:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Fuelling can be reached at (571) 270-1367. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT J HANCE/ Primary Examiner, Art Unit 3992
Conferees: /JOSEPH R POKRZYWA/ Primary Examiner, Art Unit 3992
/M.F/ Supervisory Patent Examiner, Art Unit 3992