DETAILED ACTION
Claim Rejections - 35 USC § 112
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the second through via" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim as well as in the preceding parent claims 1 and 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 14, 15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu US 2017/0125347 A1 in view of Hwang et al. US 2019/0057949 A1.
Regarding claims 1-6 and 8, Hu discloses:
A semiconductor package (Fig. 1) comprising:
a silicon substrate comprising (110 core silicon substrate) a through-silicon via (171 conductive through silicon vias);
a first build-up layer (111 top RDL) on a first surface of the silicon substrate;
a second build-up layer (bottom RDL) on a second surface of the silicon substrate; and
Hu does not disclose:
at least one capacitor included in at least one of the silicon substrate, the first build-up
layer, and the second build-up layer.
Hwang discloses a publication from a similar field of endeavor in which:
at least one capacitor (500) included in at least one of the silicon substrate, the first build-up layer, and the second build-up layer (included in redistribution layer 100) (Figs. 1 and 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor of Hwang within the similar RDL layer layers of Hu to provide various functions, such as decoupling, filtering and/or resonance damping (Hwang; para 0036).
(claim 2) Hu: Fig. 1; 111 and 112 unnumbered wiring/via region levels shown inherent within insulating layers.
(claim 3) Hwang: Figs. 1 and 2; capacitor (500) shown at top surface of RDL (100) where in combination with Hu’s top or bottom RDL (100) would meet the claimed language.
(claim 4) Hwang: Figs. 1 and 2; capacitor (500) shown included in RDL (100) connected to first and second wiring patterns (510, 530) where in combination with Hu’s top or bottom RDL (100) would meet the claimed language.
(claim 5) Hwang: Figs. 1 and 2; capacitor (500) shown included in RDL (100) on surfaces of two adjacent wiring patterns (510, 530) where in combination with Hu’s bottom RDL (100) would meet the claimed language.
(claim 6) Hwang: Figs. 1 and 2; capacitor (500) shown at top surface of RDL (100) where in combination with Hu’s bottom RDL (100) would meet the claimed language.
(claim 8) Hwang Figs. 1 and 2; a semiconductor chip (200) on a first surface of RDL (100); connection member (210) therebetween; capacitor (500) in contact with connection member where in combination with similar structure of Hu would meet the claim language.
Regarding claim 14, although Hu/Hwang do not specifically disclose “wherein a thickness of each of the at least one capacitor in a vertical direction is less than equal to 2um”, Hwang does provide evidence that a thin thickness may be formed where a desired capacitance may be installed in the semiconductor package (para 0036). As a result, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed thickness of Hwang’s capacitor to be less than or equal to 2 um
since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re
Aller, 105 USPQ 233.
Regarding claims 15 and 17-19, Hu discloses:
A method of manufacturing a semiconductor package (Fig. 1) the method comprising:
providing a silicon substrate comprising (110 core silicon substrate) a through-silicon via (171 conductive through silicon vias);
providing a first build-up layer (111 top RDL) on a first surface of the silicon substrate;
providing a second build-up layer (bottom RDL) on a second surface of the silicon substrate; and providing a semiconductor chip (101, 102).
Hu does not disclose:
providing a capacitor in at least one of the silicon substrate, the first build-up
layer, and the second build-up layer.
Hwang discloses a publication from a similar field of endeavor in which:
providing a capacitor (500) in at least one of the silicon substrate, the first build-up layer, and the second build-up layer (included in redistribution layer 100) (Figs. 1 and 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor of Hwang within the similar RDL layer layers of Hu to provide various functions, such as decoupling, filtering and/or resonance damping (Hwang; para 0036).
(claim 17) Hwang: Figs. 1 and 2; capacitor (500) shown included in RDL (100) on surfaces of two adjacent wiring patterns (510, 530) and second through via (121) where in combination with Hu’s bottom RDL (100) would meet the claimed language.
(claim 18) Hwang: Figs. 1 and 2; capacitor (500) shown included in RDL (100) on surfaces of two adjacent wiring patterns (510, 530) and second through via (121) at the upper surface of the RDL where in combination with Hu’s bottom RDL (100) would meet the claimed language.
(claim 19) Hwang: Figs. 1 and 2; capacitor (500) shown included in RDL (100) under the overlying semiconductor chip (200) where in combination with Hu’s bottom RDL (100) would meet the claimed language.
Regarding claim 20, Hu discloses:
An electronic system (Fig. 1) comprising:
a silicon substrate comprising (110 core silicon substrate) a through-silicon via (171 conductive through silicon vias);
a first build-up layer (111 top RDL) on a first surface of the silicon substrate;
a second build-up layer (bottom RDL) on a second surface of the silicon substrate; and
Hu does not disclose:
at least one memory configured to store computer-readable instructions and a plurality of
data; and at least one processor configured to execute the computer-readable instructions and implement a plurality of computing operations using the plurality of data, and
at least one capacitor included in at least one of the silicon substrate, the first build-up
layer, and the second build-up layer.
Hwang discloses a publication from a similar field of endeavor in which:
at least one memory configured to store computer-readable instructions and a plurality of
data; and at least one processor configured to execute the computer-readable instructions and implement a plurality of computing operations using the plurality of data (para 0126), and
at least one capacitor (500) included in at least one of the silicon substrate, the first build-up layer, and the second build-up layer (included in redistribution layer 100) (Figs. 1 and 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor of Hwang within the similar RDL layer layers of Hu to provide various functions, such as decoupling, filtering and/or resonance damping (Hwang; para 0036). Although Hu/Hwang do not specifically disclose “the at least one processor comprises [the above details of] the semiconductor package”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to derive such an instance from the disclosure of Hwang for the same reasons above.
Claims 7, 13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Hwang, as applied claim 1, in view of Chen et al. US 2022/0352123 A1.
Regarding claims 7, 13 and 16, Hu/Hwang do not disclose:
(claim 7) wherein the silicon substrate comprises a groove on at least one of the first surface of the silicon substrate and the second surface of the silicon substrate, and wherein a capacitor among the at least one capacitor is provided in the groove; and (claim 13) wherein a capacitor among the at least one capacitor is included in the silicon substrate, and wherein a thickness of the capacitor is less than or equal to a thickness of the silicon substrate in a vertical direction; and (claim 16) forming a groove on at least one of the second surface of the silicon substrate and the first surface of the silicon substrate, wherein the providing the capacitor comprises providing the capacitor in the groove.
Chen discloses a publication from a similar field of endeavor in which:
(claim 7) wherein the silicon substrate (101; para 0029) comprises a groove (para 0033; deep trench capacitor) on at least one of the first surface of the silicon substrate and the second surface of the silicon substrate, and wherein a capacitor (103; para 0033) among the at least one capacitor is provided in the groove; and (claim 13) wherein a capacitor (103; para 0033) among the at least one capacitor is included in the silicon substrate (101; para 0029), and wherein a thickness of the capacitor is less than or equal to a thickness of the silicon substrate in a vertical direction; and (claim 16) forming a groove (para 0033; deep trench capacitor) on at least one of the second surface of the silicon substrate and the first surface of the silicon substrate (101; para 0029), wherein the providing the capacitor comprises providing the capacitor in the groove (para 0033; deep trench capacitor) (Figs. 1-8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor of Chen at one of the surfaces of the silicon substrate of Hu/Hwang to help enable the system-on-chip's large voltage applications (Chen: para 0028).
Claims 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu/Hwang, as applied claims 1 and 8, in view of Salama US 2023/0298964 A1.
Regarding claims 9-11, Hu/Hwang do not disclose:
(claim 9) further comprising: a second semiconductor chip included in the silicon substrate, wherein another capacitor among the at least one capacitor is included in the silicon substrate adjacent to the second semiconductor chip; and (claim 10) further comprising: a second silicon substrate comprising a through via, wherein a fourth semiconductor chip is included in the second silicon substrate, and wherein another capacitor among the at least one capacitor is included in the second silicon substrate; and (claim 11) further comprising: a third semiconductor chip included in the silicon substrate, wherein a capacitor among the at least one capacitor is included in the silicon substrate adjacent to the third semiconductor chip;.
Salama discloses a publication from a similar field of endeavor in which:
(claim 9) further comprising: a second semiconductor chip (bridge die shown similar to 364 of Fig. 5A; paras 0112 and 0114) included in the silicon substrate (400), wherein another capacitor (402 decap) among the at least one capacitor is included in the silicon substrate (400) adjacent to the second semiconductor chip; and (claim 10) further comprising: a second silicon substrate (400) comprising a through via (unnumbered via in 400), wherein a fourth semiconductor chip (bridge die shown similar to 364 of Fig. 5A; paras 0112 and 0114) is included in the second silicon substrate, and wherein another capacitor (402 decap) among the at least one capacitor is included in the second silicon substrate; and (claim 11) further comprising: a third semiconductor chip (bridge die shown similar to 364 of Fig. 5A; paras 0112 and 0114) included in the silicon substrate (400), wherein a capacitor (402 decap) among the at least one capacitor is included in the silicon substrate adjacent to the third semiconductor chip; (Fig. 5A2; para 0114).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor among a second chip as shown by Salama within the silicon substrate of Hu/Hwang to provide further functionality to the overall semiconductor package allowing voltage regulation, decoupling and connection bridging.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893
