DETAILED ACTION
This action is in response to the Application filed on 10/10/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/14/2025 and 06/09/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 9 is/are objected to because of the following informalities:
Claim(s) 9 recite(s) “minimising” in British form. It appears that it should be “minimizing” in the American English spelling form.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 18 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the term “preferably”. Said term is indefinite because “preferably” seems to be optional, and therefore the scope of the claim is unclear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 4, 9 – 10, 14 – 16 and 18 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over US Pub. No. 2026/0051885; (hereinafter Zhang) in view of US Pub. No. 2013/0278229; (hereinafter Chai).
Regarding claim 1, Zhang [e.g. Fig. 8] discloses a method of balancing junction temperatures between at least two power switches of a converter, the method comprising: receiving a junction temperature of each of the at least two power switches [e.g. switches SiC and IGBT, see step 812 receiving Tjsic and Tjigbt by step 810 from Fig. 7]; determining a difference in junction temperature between the at least two power switches [e.g. Fig. 8; 812 (Tjsic – Tjigbt)]; defining a ratio of operating time [e.g. Fig. 8; step 852] for which the converter operates using a first pulse width modulation [e.g. Fig. 8; step 846], PWM, mode of a plurality of PWM modes [e.g. Fig. 8; mode 1 (840) with 846, mode 2 (842) with 848, 852, 846 and mode 3 (844) with 850, 852, 846] based on closed loop control [e.g. Fig. 8] in order to reduce the difference in junction temperature of the at least two power switches [e.g. paragraph 090 recites “If the temperature difference between the SiC MOSFET and Si IGBT of hybrid semiconductor device is less than a maximum allowable difference, then the junction temperature difference is proper”]; and generating a control signal [e.g. Fig. 8; 846] to operate the converter using the first PWM mode for the ratio of operating time [e.g. Fig. 8; 852, 846].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 2, Zhang [e.g. Fig. 8] discloses further comprising: generating a control signal [e.g. Fig. 8; 846] to operate the converter using a remainder of the plurality of PWM modes for a remainder of the time [e.g. Mode 2 (842) and Mode 3 (844)].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 3, Zhang [e.g. Fig. 8] discloses further comprising: defining a ratio of operating time [e.g. 852] for at least one other PWM mode [e.g. Mode 3] based on closed loop control in order to reduce the difference in junction temperature of the at least two power switches [e.g. paragraph 087 recites “Step 850 determines if the temperature differences is greater than allowable temperatures difference. If the temperature difference is greater than an allowable temperature difference, the multi-layer method 800 proceeds to step 852. Step 852 adjusts the first time difference and/or the second time difference according to third operation mode 844”]; and generating a control signal to operate the converter using the ratios of operating time for at least one other PWM mode [e.g. paragraph 087 recites “After adjusting the first time difference and/or the second time difference at step 852 or determining that temperature difference is below a temperature difference threshold, method 800 proceeds to step 846. Step 846 generates PWM signal according to third operation mode 844”].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 4, Zhang [e.g. Fig. 8] discloses further comprising: adjusting a ratio(s) of operating time dynamically [e.g. 852] based on real time junction temperature information of the at least two power switches [e.g. Tjsic and Tjigbt at 848, 850 ].
Regarding claim 9, Zhang [e.g. Fig. 8] discloses wherein the reducing the difference in junction temperature of the at least two power switches comprises minimising the difference in junction temperature of the at least two power switches [e.g. paragraphs 08 – 09 recite “a hybrid semiconductor device may result in an unbalanced junction temperature because the SiC MOSFET devices and Si IGBT devices are different semiconductor devices. Therefore, it would be desirable in the field of integrated circuits to provide gate sequence control for hybrid SiC MOSFET and Si IGBT devices to maintain an allowable temperature difference between the SiC MOSFET and the Si IGBT to achieve an allowable switch loss. The gate sequence control may maintain a temperature difference within a desired temperature range”. Examiner note: It is implied that Zhang is balancing (minimizing) the junction temperatures].
Regarding claim 10, Zhang [e.g. Fig. 8] discloses further comprising: selecting the at least two power switches of the converter that have different thermal losses and/or different thermal loss profiles [e.g. SiC and IGBT transistors have different thermal profiles].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 14, Zhang [e.g. Fig. 8] discloses wherein the ratio of operating time in one or more of the PWM modes is selected for one phase of the converter [e.g. step 852 in any of Mode 2 and Mode 3].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 15, Zhang [e.g. Fig. 8] discloses wherein the ratio of operating time in one or more of the PWM modes is selected for each phase of the converter [e.g. step 852 and 846].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 16, Zhang [e.g. Fig. 8] discloses a system for balancing junction temperatures between at least two power switches of a converter, the system comprising: a closed loop controller [e.g. Fig. 8] configured to: receive a junction temperature of each of the at least two power switches [e.g. switches SiC and IGBT, see step 812 receiving Tjsic and Tjigbt by step 810 from Fig. 7]; determine a difference in junction temperature between the at least two power switches [e.g. Fig. 8; 812 (Tjsic – Tjigbt)]; define a ratio of operating time [e.g. Fig. 8; step 852] for which the converter operates using a first pulse width modulation [e.g. Fig. 8; step 846], PWM, mode of a plurality of PWM modes [e.g. Fig. 8; mode 1 (840) with 846, mode 2 (842) with 848, 852, 846 and mode 3 (844) with 850, 852, 846] based on closed loop control [e.g. Fig. 8] in order to reduce the difference in junction temperature of the at least two power switches [e.g. paragraph 090 recites “If the temperature difference between the SiC MOSFET and Si IGBT of hybrid semiconductor device is less than a maximum allowable difference, then the junction temperature difference is proper”], and generate a control signal [e.g. Fig. 8; 846] to operate the converter using the first PWM mode for the ratio of operating time [e.g. Fig. 8; 852, 846].
Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Regarding claim 18, Zhang fails to disclose wherein the converter is a multilevel converter.
Chai [e.g. Fig. 3] teaches wherein the converter is a multilevel converter [e.g. paragraph 012 recites “FIG. 3 illustrates a three-level inverter IGBT switch array”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the converter is a multilevel converter as taught by Chai in order of being able to take many levels of DC input voltage and produce a desired output voltage waveform.
Claim(s) 7 – 8 and 17 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chai and further in view of US Pub. No. 2016/0377687; (hereinafter Nimura).
Regarding claim 7, Zhang fails to disclose wherein the closed loop control is implemented using linear control.
Nimura [e.g. Figs. 1 - 3] taches wherein the closed loop control is implemented using linear control [e.g. paragraph 042 recites “the control module 31 comprises a root-mean-square value computation module 311, a subtracter 312, a proportional-plus-integral control (PI) control module 313”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the closed loop control is implemented using linear control as taught by Nimura in order of being able to continuously corrects any persistent deviation.
Regarding claim 8, Zhang fails to disclose wherein the closed loop linear control is implemented using a proportional, P, controller, a proportional-integral, PI, controller, or a proportional-integral-derivative, PID, controller.
Nimura [e.g. Figs. 1 - 3] taches wherein the closed loop linear control is implemented using a proportional, P, controller, a proportional-integral, PI, controller, or a proportional-integral-derivative, PID, controller [e.g. paragraph 042 recites “the control module 31 comprises a root-mean-square value computation module 311, a subtracter 312, a proportional-plus-integral control (PI) control module 313”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the closed loop linear control is implemented using a proportional, P, controller, a proportional-integral, PI, controller, or a proportional-integral-derivative, PID, controller as taught by Nimura in order of being able to continuously corrects any persistent deviation.
Regarding claim 17, Zhang fails to disclose wherein the closed loop controller comprises a linear closed loop controller.
Nimura [e.g. Figs. 1 - 3] teaches wherein the closed loop controller comprises a linear closed loop controller [e.g. paragraph 042 recites “the control module 31 comprises a root-mean-square value computation module 311, a subtracter 312, a proportional-plus-integral control (PI) control module 313”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the closed loop controller comprises a linear closed loop controller as taught by Nimura in order of being able to continuously corrects any persistent deviation.
Claim(s) 11 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chai and further in view of US Pub. No. 2024/0171157; (hereinafter Alisar).
Regarding claim 11, Zhang fails to disclose wherein receiving the junction temperature of the at least two power switches comprises: modelling the junction temperature of the at least two power switches based on look up tables.
Alisar [e.g. Fig. 10] teaches wherein receiving the junction temperature of the at least two power switches comprises: modelling the junction temperature of the at least two power switches based on look up tables [e.g. paragraph 071 recites “If the temperature is obtained from the case or the heatsink, an RC network or look-up table 20 may be used to convert the case temperature Tc or the heatsink temperature Ths into a junction temperature Tj. After the selector 10, a low pass filter 30 may be used to eliminate or substantially dampen the sudden changes or unwanted noises in the temperature measurements or estimations”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein receiving the junction temperature of the at least two power switches comprises: modelling the junction temperature of the at least two power switches based on look up tables as taught by Alisar in order of being able to speeding up data access, and improving system performance.
Claim(s) 12 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chai and further in view of US Pub. No. 2012/0313595; (hereinafter Mao).
Regarding claim 12, Zhang fails to disclose wherein receiving the junction temperature of the at least two power switches comprises: measuring the junction temperature by direct die temperature measurement for each of the at least two power switches.
Mao teaches wherein receiving the junction temperature of the at least two power switches comprises: measuring the junction temperature by direct die temperature measurement for each of the at least two power switches [e.g. paragraph 031 recites “the high side switch SW1, the low side switch SW2 and the driver 202 may be fabricated on a single semiconductor die. The driver 202 may comprise a temperature detection circuit to detect the junction temperature of the monolithic semiconductor die and report the junction temperature through the signal terminal Tj to an external thermal management unit (not shown)”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein receiving the junction temperature of the at least two power switches comprises: measuring the junction temperature by direct die temperature measurement for each of the at least two power switches as taught by Mao in order of being able to provide reliability.
Claim(s) 19 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chai and further in view of US Pub. No. 2024/0275303; (hereinafter Xiao).
Regarding claim 19, Zhang fails to disclose wherein the multilevel converter is an inverter, preferably an active neutral point clamp, ANPC, inverter.
Xiao [e.g. Fig. 2] teaches wherein the multilevel converter is an inverter, preferably an active neutral point clamp, ANPC, inverter [e.g. paragraph 045 recites “FIG. 2 is a structural diagram of an A-NPC inverter”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the multilevel converter is an inverter, preferably an active neutral point clamp, ANPC, inverter as taught by Xiao in order of being able to improve efficiency and reduce harmonic distortion.
Claim(s) 20 is/are rejected under 35 U.S.C. 103(a) as being unpatentable over Zhang in view of Chai and further in view of US Pub. No. 2019/0140557; (hereinafter ‘557).
Regarding claim 20, Zhang fails to disclose wherein the multilevel converter comprises three pairs of power switches in a half-bridge leg, and the at least two power switches belong to different pairs of the three pairs of power switches.
‘557 [e.g. Figs. 1 - 2] teaches wherein the multilevel converter comprises three pairs of power switches in a half-bridge leg [e.g. Fig. 2; switches 218 and 220 in each phase legs 1 – 3 of Fig. 1], and the at least two power switches belong to different pairs of the three pairs of power switches [e.g. phase legs 1 - 3].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zhang by wherein the multilevel converter comprises three pairs of power switches in a half-bridge leg, and the at least two power switches belong to different pairs of the three pairs of power switches as taught by ‘557 in order of being able to improve reliability.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claim(s) 5, 6 and 13 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 5 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “applying a predefined swapping period for operating the plurality of PWM modes”.
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein measuring the junction temperature by direct die temperature measurement for each of at least two power switches comprises measuring the junction temperatures using a highly integrated SiC-Cascode power switch”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
Prosecution Insights