DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 03/31/2026. Claims 1-20 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/31/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference Park US 2024/0345771 is cited in this Office Action necessitated by the amendment.
The objection given in the previous Office Action is withdrawn in view of the amendment.
In view of the new reference, independent claims 1, 11, and 17 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lam et al. US 2022/0187999 (“Lam”) in view of O’Krafka et al. US 2017/0242790 (“O’Krafka”) and in further view of Park US 2024/0345771 (“Park”).
As per independent claim 1, Lam teaches A memory controller (“A memory sub-system controller 115 (or controller 115 for simplicity)” para 0037 and FIGS. 1 and 2), comprising
a data buffer (“single-level cell (SLC) cache 207” para 0044 and FIG. 2);
a processor coupled to the data buffer (“processor 117” para 0038 and FIG. 1) and configured to:
control a memory device to sequentially write data into a buffer area of the memory device (“Write operations can be performed sequentially in the 4 SLC blockstripes.” Para 0053);
sequentially write the data in the buffer area into a storage area of the memory device (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe. The QLC blockstripe can be selected sequentially for programming.” Paras 0053 and 0058);
wherein the first zone includes multiple first memory cells in which data is stored in a single-level mode (“Write operations can be performed sequentially in the 4 SLC blockstripes.” Para 0053. A zone is mapped to a blockstripe);
wherein the storage area includes multiple second memory cells in which data is stored in a multi-level mode (“The QLC blockstripe can be selected sequentially for programming.” Para 0053 and 0058”).
Lam discloses all of the claim limitations from above, but does not explicitly teach “wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities” and “wherein in response to an amount of the data being less than a storage capacity of the buffer area, control the memory device to sequentially write the data in the buffer area into the storage area of the memory device in response to the memory device being idle during a garbage collection operation of the memory device”.
However, in an analogous art in the same field of endeavor, O’Krafka teaches wherein the buffer area includes multiple first zones which include contiguous physical addresses (“the contiguous sequence of logical addresses for the logical stripe corresponds to one or more contiguous sequences of physical addresses in the physical address space of the storage devices.” Para 0148) and equal storage capacities (“the logical stripe is sized such that it is composed of one or more erase blocks per storage device” para 0121).
Given the teaching of O’Krafka, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Lam with “wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities”. The motivation would be that the invention improves performance by employing write serialization, para 0016 of O’Krafka.
Lam in combination with O’Krafka discloses all of the claim limitations from above, but does not explicitly teach “wherein in response to an amount of the data being less than a storage capacity of the buffer area, control the memory device to sequentially write the data in the buffer area into the storage area of the memory device in response to the memory device being idle during a garbage collection operation of the memory device”.
However, in an analogous art in the same field of endeavor, Park teaches wherein in response to an amount of the data being less than a storage capacity of the buffer area, control the memory device to sequentially write the data in the buffer area into the storage area of the memory device in response to the memory device being idle during a garbage collection operation of the memory device (“If the device information includes both information on the remaining capacity of the write booster buffer and the dirty level, an idle period may be set as the sum of the idle periods corresponding to each of information.” Para 0134. “The idle period may be set in various ways depending on whether an operation of moving data in the write booster buffer and garbage collection are performed separately or simultaneously.” Para 0135. “a remaining capacity of a write booster buffer composed of single-level cells.” Para 0080. “if the remaining capacity of the write booster buffer is 25% or less, the idle period may be set to T11.” Para 0115. Lam teaches sequentially writing from a non-volatile buffer to a non-volatile storage).
Given the teaching of Park, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Lam and O’Krafka with “wherein in response to an amount of the data being less than a storage capacity of the buffer area, control the memory device to sequentially write the data in the buffer area into the storage area of the memory device in response to the memory device being idle during a garbage collection operation of the memory device”. The motivation would be that the invention improves the operating efficiency of a storage device operating according to an external or an internal command, para 0009 of Park.
As per dependent claim 2, Lam in combination with O’Krafka and Park discloses the device of claim 1. Lam teaches wherein the processor is further configured to: configure multiple memory cells of the memory device as the buffer area (“Write operations can be performed sequentially in the 4 SLC blockstripes.” Para 0053) and the storage area (“The QLC blockstripe can be selected sequentially for programming.” Para 0053 and 0058).
As per dependent claim 3, Lam in combination with O’Krafka and Park discloses the device of claim 1. Lam teaches the storage capacity of each of the second zones is equal to the storage capacity of each of the first zones (“4 SLC blockstripes” equals 1 QLC blockstripe, para 9953);
the processor is further configured to: control the memory device to sequentially write data in the first zone into the second zone (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe. The QLC blockstripe can be selected sequentially for programming.” Para 0053 and 0058);
erase data in the first zone that has been written into the second zone (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe.” Para 0053. Migrating the data means that the SLC cache is erased).
Lam may not explicitly disclose, but O’Krafka teaches wherein the storage area includes multiple second zones which include contiguous physical addresses (“the contiguous sequence of logical addresses for the logical stripe corresponds to one or more contiguous sequences of physical addresses in the physical address space of the storage devices.” Para 0148) and equal storage capacities (“the logical stripe is sized such that it is composed of one or more erase blocks per storage device” para 0121).
The same motivation that was utilized for combining Lam and O’Krafka as set forth in claim 1 is equally applicable to claim 3.
As per dependent claim 4, Lam in combination with O’Krafka and Park discloses the device of claim 3. Lam teaches wherein the processor is further configured to: in response to an amount of data to be written to the memory device being less than or equal to the storage capacity of the buffer area, control the memory device to write data into the buffer area (4 blockstripes are written until they are full, para 0053);
control the memory device to write data in one first zone into one second zone, the written addresses in the second zone being contiguous (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe. The QLC blockstripe can be selected sequentially for programming.” Paras 0053 and 0058).
As per dependent claim 5, Lam in combination with O’Krafka and Park discloses the device of claim 3. Lam teaches wherein the processor is further configured to: in response to an amount of data to be written to the memory device being greater than the storage capacity of the buffer area, write a portion of data into the buffer area; control the memory device to sequentially write data in the first zone into the second zone, and erase the first zone; wherein one first zone corresponds to one second zone; and control the memory device to write another portion of data into the erased first zone (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe. The QLC blockstripe can be selected sequentially for programming.” Paras 0053 and 0058).
As per dependent claim 6, Lam in combination with O’Krafka and Park discloses the device of claim 3. Lam teaches wherein the processor is further configured to: generate a mapping table, the mapping table including a space number and flag information (“The replay info table can have four fields, index, QLC blockstripe number(s), SLC blockstripe number(s), and a “data in SLC” flag.” Para 0069);
wherein one second zone corresponds to one space number (“QLC blockstripe number(s),” para 0069), and the number of space numbers is equal to the number of second zones (“QLC blockstripe number(s),” para 0069), one space number corresponds to one first zone (“SLC blockstripe number(s),” para 0069);
the flag information includes first information and second information, the first information indicates that the first zone is stored with data, and the second information indicates that the second zone is stored with data (“the ‘data in SLC’ flag indicates whether the data is in the SLC blockstripe(s) or has migrated to the QLC blockstripe(s).” Para 0069).
As per dependent claim 7, Lam in combination with O’Krafka and Park discloses the device of claim 6. Lam teaches and the number of memory cells in the first subzone is equal to the number of memory cells in the second zone (4 SLC blockstripes are copied into a QLC blockstripe, para 0053), a first one of first subzones in the first zones corresponds to one space number (“SLC blockstripe number(s),” para 0069).
Lam may not explicitly disclose, but O’Krafka teaches wherein the first zone includes multiple first subzones which include equal storage capacities (“the logical stripe is sized such that it is composed of one or more erase blocks per storage device” para 0121) and contiguous physical addresses (“the contiguous sequence of logical addresses for the logical stripe corresponds to one or more contiguous sequences of physical addresses in the physical address space of the storage devices.” Para 0148).
The same motivation that was utilized for combining Lam and O’Krafka as set forth in claim 6 is equally applicable to claim 7.
As per dependent claim 8, Lam in combination with O’Krafka and Park discloses the device of claim 6. Lam teaches wherein the processor is further configured to: calculate a space number corresponding to a logical address according to the logical address corresponding to data to be read; obtain a physical address corresponding to the logical address from the mapping table according to the space number and the flag information; and control the memory device to read data corresponding to the physical address (“Because the data programmed to the QLC memory is not ready to service read operations until the data is finalized in a second pass, the data is also programmed to a single level cell (SLC) memory cache to be able to service read operations prior to the QLC memory being finalized.” Para 0021).
As per dependent claim 9, Lam in combination with O’Krafka and Park discloses the device of claim 6. Lam teaches wherein the data buffer is configured to store the mapping table (“The L2P table can be maintained by the firmware of the memory sub-system controller and can be stored on one or more non-volatile memory devices of the memory sub-system.” Para 0019).
As per dependent claim 10, Lam in combination with O’Krafka and Park discloses the device of claim 1. Lam teaches wherein the data buffer is configured to: store data which is to be written into the buffer area (“Write buffer 201 can store write commands submitted to the memory sub-system by the host system 120 and/or write commands initiated by controller 115 (e.g., garbage collection).” Para 0045 and FIG. 2);
the processor is further configured to: write the data into the buffer area (“Controller 115 can execute the write commands to SLC blockstripes in the SLC cache 207.” Para 0045 and FIG. 2).
As per independent claim 11, Lam teaches A memory system (“FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110” para 0027), comprising:
a memory controller (“A memory sub-system controller 115 (or controller 115 for simplicity)” para 0037 and FIGS. 1 and 2) configured to send a first operation command (“memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations.” Para 0037 and FIGS. 1 and 2);
a memory device coupled to the memory controller (“memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations.” Para 0037 and FIGS. 1 and 2) and comprising:
a buffer area (“single-level cell (SLC) cache 207” para 0044 and FIG. 2) and a storage area (“quad-level cell (QLC) memory device 210”, para 0044 and FIG. 2);
the first zone includes multiple first memory cells in which data is stored in a single-level mode (“Write operations can be performed sequentially in the 4 SLC blockstripes.” Para 0053);
the storage area includes multiple second memory cells in which data is stored in a multi-level mode (“The QLC blockstripe can be selected sequentially for programming.” Para 0053 and 0058”);
the memory device is configured to: in response to the first operation command, sequentially write data into the buffer area (“Write operations can be performed sequentially in the 4 SLC blockstripes.” Para 0053);
sequentially write data in the buffer area into the storage area (“When the 4 SLC blockstripes are full, the 4 SLC blockstripes are migrated to the QLC blockstripe. The QLC blockstripe can be selected sequentially for programming.” Paras 0053 and 0058).
Lam discloses all of the claim limitations from above, but does not explicitly teach “wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities” and “wherein in response to an amount of the data being less than a storage capacity of the buffer area, the memory device is configured to sequentially write the data in the buffer area into the storage area in response to the memory device being idle during a garbage collection operation of the memory device”.
However, in an analogous art in the same field of endeavor, O’Krafka teaches wherein the buffer area includes multiple first zones which include contiguous physical addresses (“the contiguous sequence of logical addresses for the logical stripe corresponds to one or more contiguous sequences of physical addresses in the physical address space of the storage devices.” Para 0148) and equal storage capacities (“the logical stripe is sized such that it is composed of one or more erase blocks per storage device” para 0121).
Given the teaching of O’Krafka, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Lam with “wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities”. The motivation would be that the invention improves performance by employing write serialization, para 0016 of O’Krafka.
Lam in combination with O’Krafka discloses all of the claim limitations from above, but does not explicitly teach “wherein in response to an amount of the data being less than a storage capacity of the buffer area, the memory device is configured to sequentially write the data in the buffer area into the storage area in response to the memory device being idle during a garbage collection operation of the memory device”.
However, in an analogous art in the same field of endeavor, Park teaches “wherein in response to an amount of the data being less than a storage capacity of the buffer area, the memory device is configured to sequentially write the data in the buffer area into the storage area in response to the memory device being idle during a garbage collection operation of the memory device” (“If the device information includes both information on the remaining capacity of the write booster buffer and the dirty level, an idle period may be set as the sum of the idle periods corresponding to each of information.” Para 0134. “The idle period may be set in various ways depending on whether an operation of moving data in the write booster buffer and garbage collection are performed separately or simultaneously.” Para 0135. “a remaining capacity of a write booster buffer composed of single-level cells.” Para 0080. “if the remaining capacity of the write booster buffer is 25% or less, the idle period may be set to T11.” Para 0115. Lam teaches sequentially writing from a non-volatile buffer to a non-volatile storage).
Given the teaching of Park, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Lam and O’Krafka with “wherein in response to an amount of the data being less than a storage capacity of the buffer area, control the memory device to sequentially write the data in the buffer area into the storage area of the memory device in response to the memory device being idle during a garbage collection operation of the memory device”. The motivation would be that the invention improves the operating efficiency of a storage device operating according to an external or an internal command, para 0009 of Park.
As per dependent claims 12-16, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2-3 and 6-8.
As per claims 17-20, these claims are respectively rejected based on arguments provided above for similar rejected claims 11, 3, and 6-7.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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