DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 01/05/2026. Claims 1-21 have been examined and are pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1-21 have been considered but are moot in view of the current rejection.
The 35 U.S.C. 101 rejection of claims 1-2, 6-9, 14-16, and 20-21 is withdrawn in view of the amendment.
Applicant argues that the double patenting rejection of instant claims 1-21 over the claims of US Patent 12,141,467 is moot (see page 7 of Applicant’s remarks). The Examiner respectfully submits that the amendment to independent claims 1, 8, and 15 do not overcome the double patenting rejection. Thus, the rejection is maintained. Applicant is hereby requested to submit a reply showing that the claims subject to the rejection are patentably distinct from the reference claims, or file a terminal disclaimer. See MPEP 804.I.B.1.
Applicant argues, page 12 of the remarks, “[instead], Boehm explicitly describes that the scrub rate is for the entire memory array.”
While the Examiner does not necessarily agree with the Applicant’s assertion about Boehm (because Boehm varies scrub rate from die to die of a memory device, for example, “Increasing the scrub rate based on the condition of the memory die 200 may increase the reliability of the memory die 200.” para 0063 of Boehm), nonetheless, for an explicit teaching of varying scrub (or refresh) rate based on memory region and temperature, a new reference Walker et al. US 2019/0121723 (“Walker”) is cited in this Office Action.
Walker teaches “the processor 110 or the memory controller 120 may use on-die thermal sensors and thermal models to individually adjust memory cell refresh across regions based on their temperature.” Para 0020 of Walker.
In view of the new reference and the foregoing remarks, independent claims 1, 8, and 15 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
As enumerated in the table below, instant claims 1-3, 8-10, and 15-17 are anticipated by claims 1-2, 11-12, and 17-18 of US Patent 12,141,467.
Status
Instant Application
US Patent 12,141,467
Anticipation
1. (Currently Amended) A method for operating a memory system, comprising: writing a set of data to a first block of a memory array of the memory system, wherein the first block is associated with a first scan rate, and wherein the set of data is written to the first block based at least in part on a first temperature of the memory system falling outside of a first threshold range; and writing the set of data to a second block of the memory array of the memory system, wherein the second block is associated with a second scan rate, wherein the set of data is written to the second block based at least in part on a second temperature of the memory system falling within the first threshold range, and wherein the second scan rate is slower than the first scan rate.
1. A method, comprising: determining a first temperature of a memory system that comprises a first block configured with a first rate for performing scan operations and a second block configured with a second rate for performing scan operations; selecting, for writing a set of data and based at least in part on the first temperature falling outside of a first threshold range, the first block based at least in part on the first block being configured with the first rate for performing scan operations to determine error information for the first block; determining a second temperature of the memory system after writing the set of data to the first block; determining to transfer the set of data from the first block based at least in part on the second temperature and the first rate for performing scan operations; and selecting, for transferring the set of data from the first block and based at least in part on the second temperature falling within a second threshold range, the second block based at least in part on the second block being configured with the second rate, for performing scan operations to determine error information for the second block, that is slower than the first rate.
Anticipation
2. The method of claim 1, further comprising: setting the first scan rate for the first block, wherein the first scan rate for the first block is based at least in part on the first temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the first block, or both, and wherein writing the set of data to the first block is based at least in part on setting the first scan rate.
Claim 1.
Anticipation
3. The method of claim 1, further comprising: obtaining an error metric associated with the set of data written to the first block based at least in part on performing a scan operation at the first block according to the first scan rate; and writing the set of data from the first block to a third block associated with a third scan rate based at least in part on the error metric satisfying a threshold error metric, wherein writing the set of data is from the third block to the second block, and wherein the third scan rate is greater than or equal to the first scan rate.
2. The method of claim 1, further comprising: determining, before determining the second temperature, an error metric for the first block based at least in part on performing a scan operation, wherein the error information comprises the error metric; and transferring, based at least in part on the error metric satisfying a threshold, the set of data from the first block to a third block that is configured with a third rate for performing scan operations for determining error information for the third block.
Obvious in view of Boehm et al. US 2020/0387323
4. The method of claim 3, further comprising: setting the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate.
Claim 1.
Obvious in view of Boehm et al. US 2020/0387323
5. The method of claim 3, wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both.
Claim 1.
Obvious in view of Boehm et al. US 2020/0387323
6. The method of claim 1, further comprising: writing the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range.
Claim 1.
Obvious in view of Boehm et al. US 2020/0387323
7. The method of claim 1, wherein the set of data is written from the first block to the second block based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range.
Claim 1.
Anticipation
8. (Currently Amended) A memory system, comprising: one or more memory devices comprising a first memory array, wherein the first memory array comprises a first block associated with a first scan rate and a second block associated with a second scan rate that is slower than the first scan rate; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: write a set of data to the first block based at least in part on a first temperature of the memory system falling outside of a first threshold range; and write the set of data to the second block based at least in part on a second temperature of the memory system falling within the first threshold range.
11. A memory system, comprising: one or more memory devices comprising a first block configured with a first rate for performing scan operations and a second block configured with a second rate for performing scan operations; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: determine a first temperature of the memory system; select, for writing a set of data, based at least in part on the first temperature falling outside of a first threshold range, the first block based at least in part on the first block being configured with the first rate for performing scan operations to determine error information for the first block; determine a second temperature of the memory system after writing the set of data to the first block; determine to transfer the set of data from the first block based at least in part on the second temperature and the first rate for performing scan operations; and select, for transferring the set of data from the first block and based at least in part on the second temperature falling within a second threshold range, the second block is based at least in part on the second block being configured with the second rate, for performing scan operations to determine error information for the second block, that is slower than the first rate.
Anticipation
9. The memory system of claim 8, further comprising: set the first scan rate for the first block, wherein the first scan rate for the first block is based at least in part on the first temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the first block, or both, and wherein writing the set of data to the first block is based at least in part on setting the first scan rate.
Claim 11.
Anticipation
10. The memory system of claim 8, further comprising: obtain an error metric associated with the set of data written to the first block based at least in part on performing a scan operation at the first block according to the first scan rate; and write the set of data from the first block to a third block associated with a third scan rate based at least in part on the error metric satisfying a threshold error metric, wherein writing the set of data is from the third block to the second block, and wherein the third scan rate is greater than or equal to the first scan rate.
12. The memory system of claim 11, wherein the one or more controllers is further configured to cause the memory system to: determine, before determining the second temperature, an error metric for the first block based at least in part on performing a scan operation, wherein the error information comprises the error metric; and transfer, based at least in part on the error metric satisfying a threshold, the set of data from the first block to a third block that is configured with a third rate for performing scan operations for determining error information for the third block.
Obvious in view of Boehm et al. US 2020/0387323
11. The memory system of claim 10, further comprising: set the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate.
Claim 11.
Obvious in view of Boehm et al. US 2020/0387323
12. The memory system of claim 10, wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both.
Claim 11.
Obvious in view of Boehm et al. US 2020/0387323
13. The memory system of claim 10, further comprising: write the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range.
Claim 11.
Obvious in view of Boehm et al. US 2020/0387323
14. The memory system of claim 8, wherein the set of data is written from the first block to the second block based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range.
Claim 11.
Anticipation
15. (Currently Amended) A non-transitory, computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to: write a set of data to a first block of a memory array of the memory system, wherein the first block is associated with a first scan rate, and wherein the set of data is written to the first block based at least in part on a first temperature of the memory system falling outside of a first threshold range; and write the set of data to a second block of the memory array of the memory system, wherein the second block is associated with a second scan rate, and wherein the set of data is written to the second block based at least in part on a second temperature of the memory system falling within the first threshold range, and wherein the second scan rate is slower than the first scan rate.
17. A non-transitory, computer-readable medium storing code comprising instructions which, when executed by a processor of a memory system, cause the memory system to: determine a first temperature of the memory system that comprises a first block configured with a first rate for performing scan operations and a second block configured with a second rate for performing scan operations; select, for writing a set of data, and based at least in part on the first temperature falling outside of a first threshold range, the first block based at least in part on the first block being configured with the first rate for performing scan operations to determine error information for the first block; determine a second temperature of the memory system after writing the set of data to the first block; determine to transfer the set of data from the first block based at least in part on the second temperature and the first rate for performing scan operations; and select, for transferring the set of data from the first block and based at least in part on the second temperature falling within a second threshold range, the second block based at least in part on the second block being configured with the second rate, for performing scan operations to determine error information for the second block, that is slower than the first rate.
Anticipation
16. The non-transitory, computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the memory system to: set the first scan rate for the first block, wherein the first scan rate for the first block is based at least in part on the first temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the first block, or both, and wherein writing the set of data to the first block is based at least in part on setting the first scan rate.
Claim 17.
Anticipation
17. The non-transitory, computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the memory system to: obtain an error metric associated with the set of data written to the first block based at least in part on performing a scan operation at the first block according to the first scan rate; and write the set of data from the first block to a third block associated with a third scan rate based at least in part on the error metric satisfying a threshold error metric, wherein writing the set of data is from the third block to the second block, and wherein the third scan rate is greater than or equal to the first scan rate.
18. The non-transitory, computer-readable medium of claim 17, wherein the instructions, when executed by the processor, further cause the memory system to: determine, before determining the second temperature, an error metric for the first block based at least in part on performing a scan operation, wherein the error information comprises the error metric; and transfer, based at least in part on the error metric satisfying a threshold, the set of data from the first block to a third block that is configured with a third rate for performing scan operations for determining error information for the third block.
Obvious in view of Boehm et al. US 2020/0387323
18. The non-transitory, computer-readable medium of claim 17, wherein the instructions, when executed by the one or more processors, further cause the memory system to: set the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system, a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate.
Claim 17.
Obvious in view of Boehm et al. US 2020/0387323
19. The non-transitory, computer-readable medium of claim 17, wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both.
Claim 17.
Obvious in view of Boehm et al. US 2020/0387323
20. The non-transitory, computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the memory system to: write the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range.
Claim 17.
Obvious in view of Boehm et al. US 2020/0387323
21. The non-transitory, computer-readable medium of claim 15, wherein the set of data is written from the first block to the second block based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range.
Claim 17.
Claims 4-7, 11-14, and 18-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 17 of U.S. Patent No. 12,141,467 in view of Boehm et al. US 2020/0387323 (“Boehm”).
As per claims 4, 11, and 18, taking claim 4 as exemplary, Boehm teaches further comprising: setting the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system (“there may be different nominal rates defined for various temperatures of the memory device 310.” Para 0081), a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate (“the scrub command component 635 may receive a second set of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate. In some cases, the second rate is based on the second condition of the memory array.” Para 0123 and FIG. 6. See para 0013 where it is described that in some cases the data is written back to the memory as part of a scrub operation).
Given the teaching of Boehm, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of the US Patent with “further comprising: setting the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system” and “a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate”.
As per claims 5, 12, and 19, taking claim 5 as exemplary, Boehm teaches wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both (“Based on an error metric determined from the quantity of errors detected during the scrub operation, the controller 360 may determine a condition of the memory array 370.” Para 0073).
Given the teaching of Boehm, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of the US Patent with “wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both”.
As per claims 6, 13, and 20, taking claim 6 as exemplary, Boehm teaches further comprising: writing the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range (“there may be different nominal rates defined for various temperatures of the memory device 310.” Para 0081).
Given the teaching of Boehm, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of the US Patent with “further comprising: writing the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range”.
As per claims 7, 14, and 21, taking claim 7 as exemplary, Boehm teaches wherein the set of data is written from the first block to the second block (“The memory device may store the data and the error correction information at the memory array as part of the write operation.” Para 0013) based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range (“in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081).
Given the teaching of Boehm, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of the US Patent with “wherein the set of data is written from the first block to the second block based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Boehm et al. US 2020/0387323 (“Boehm”) in view of Walker et al. US 2019/0121723 (“Walker”).
As per independent claim 1, Boehm teaches A method for operating a memory system (A method for scrub rate control for a memory device is described, see claim 1), comprising:
writing a set of data to a first block of a memory array of the memory system (“The memory device may store the data and the error correction information at the memory array as part of the write operation.” Para 0013),
writing the set of data to a second block of the memory array of the memory system (“The memory device may store the data and the error correction information at the memory array as part of the write operation.” Para 0013), and wherein the second scan rate is slower than the first scan rate (“in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081).
Boehm additionally teaches that scrub rate may be increased based on a condition for a memory die 200 which may increase the reliability of the memory die 200, para 0063. Further, Boehm teaches “in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081.
Boehm may not explicitly disclose, but in an analogous art in the same field of endeavor, Walker teaches wherein the first block is associated with a first scan rate (“Example embodiments may control the refresh rate of memory cells based on temperature. … the entire memory system 130 is not treated the same with respect to control of refresh rates. On the contrary, each region may be refreshed individually based on the temperature of that region and not the worst-case temperature at any given location of the device.” Para 0028. See Table 1 for various refresh rates for regions that are cold, cool, room temp, warm, hot etc.), and wherein the set of data is written to the first block based at least in part on a first temperature of the memory system falling outside of a first threshold range (“… the entire memory system 130 is not treated the same with respect to control of refresh rates. On the contrary, each region may be refreshed individually based on the temperature of that region and not the worst-case temperature at any given location of the device.” Para 0028. See Table 1 for various refresh rates for regions that are cold, cool, room temp, warm, hot etc. Walker does not explicitly teach “temperature … falling outside of a threshold range”. But Boehm teaches “in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081 of Boehm);
wherein the second block is associated with a second scan rate (“Example embodiments may control the refresh rate of memory cells based on temperature. … the entire memory system 130 is not treated the same with respect to control of refresh rates. On the contrary, each region may be refreshed individually based on the temperature of that region and not the worst-case temperature at any given location of the device.” Para 0028. See Table 1 for various refresh rates for regions that are cold, cool, room temp, warm, hot etc.), wherein the set of data is written to the second block based at least in part on a second temperature of the memory system falling within the first threshold range (“… the entire memory system 130 is not treated the same with respect to control of refresh rates. On the contrary, each region may be refreshed individually based on the temperature of that region and not the worst-case temperature at any given location of the device.” Para 0028. See Table 1 for various refresh rates for regions that are cold, cool, room temp, warm, hot etc. Walker does not explicitly teach “temperature … falling withing within the first threshold range”. But Boehm teaches “in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081 of Boehm).
Given the teaching of Walker, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Boehm with “wherein the first block is associated with a first scan rate, and wherein the set of data is written to the first block based at least in part on a first temperature of the memory system falling outside of a first threshold range” and “wherein the second block is associated with a second scan rate, wherein the set of data is written to the second block based at least in part on a second temperature of the memory system falling within the first threshold range”. The motivation would be that the example embodiments may provide methods to improve performance or power usage or to satisfy other system constraints, para 0034 of Walker.
As per dependent claim 2, Boehm in combination with Walker discloses the method of claim 1. Boehm teaches further comprising: setting the first scan rate for the first block, wherein the first scan rate for the first block is based at least in part on the first temperature of the memory system (“in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081), a quantity of program/erase cycles (PECs) performed at the first block, or both, and wherein writing the set of data to the first block is based at least in part on setting the first scan rate (“The memory device may store the data and the error correction information at the memory array as part of the write operation.” Para 0013).
As per dependent claim 3, Boehm in combination with Walker discloses the method of claim 1. Boehm teaches further comprising: obtaining an error metric associated with the set of data written to the first block based at least in part on performing a scan operation at the first block according to the first scan rate (“Based on an error metric determined from the quantity of errors detected during the scrub operation, the controller 360 may determine a condition of the memory array 370.” Para 0073); and writing the set of data from the first block to a third block associated with a third scan rate based at least in part on the error metric satisfying a threshold error metric, wherein writing the set of data is from the third block to the second block, and wherein the third scan rate is greater than or equal to the first scan rate (“the scrub command component 635 may receive a second set of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate. In some cases, the second rate is based on the second condition of the memory array.” Para 0123 and FIG. 6. See para 0013 where it is described that in some cases the data is written back to the memory as part of a scrub operation).
As per dependent claim 4, Boehm in combination with Walker discloses the method of claim 3. Boehm teaches further comprising: setting the third scan rate of the third block, wherein the third scan rate for the third block is based at least in part on a third temperature of the memory system (“there may be different nominal rates defined for various temperatures of the memory device 310.” Para 0081), a quantity of program/erase cycles (PECs) performed at the third block, or both, and wherein writing the set of data to the third block is based at least in part on setting the third scan rate (“the scrub command component 635 may receive a second set of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate. In some cases, the second rate is based on the second condition of the memory array.” Para 0123 and FIG. 6. See para 0013 where it is described that in some cases the data is written back to the memory as part of a scrub operation).
As per dependent claim 5, Boehm in combination with Walker discloses the method of claim 3. Boehm teaches wherein the error metric comprises a raw bit error rate (RBER) associated with the set of data written to the first block, a quantity of errors in the set of data written to the first block, or both (“Based on an error metric determined from the quantity of errors detected during the scrub operation, the controller 360 may determine a condition of the memory array 370.” Para 0073).
As per dependent claim 6, Boehm in combination with Walker discloses the method of claim 1. Boehm teaches further comprising: writing the set of data from the second block to the first block based at least in part on writing the set of data to the second block and on a third temperature of the memory system falling outside of the first threshold range (“there may be different nominal rates defined for various temperatures of the memory device 310.” Para 0081).
As per dependent claim 7, Boehm in combination with Walker discloses the method of claim 1. Boehm teaches wherein the set of data is written from the first block to the second block (“The memory device may store the data and the error correction information at the memory array as part of the write operation.” Para 0013) based at least in part on the first scan rate of the first block and on the second temperature of the memory system falling within the first threshold range (“in extreme operating temperatures (e.g., temperatures exceeding 95° C.), the nominal rate may be higher than in a case that the memory device is near room temperature.” Para 0081).
As per claims 8-14, these claims are respectively rejected based on arguments provided above for similar rejected claim 1-7. “a system that includes at least one memory device” para 0001 of Boehm.
As per claims 15-21, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-7. See para 0142 of Boehm for a non-transitory computer readable medium storing computer executable instructions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132