DETAILED ACTION
Response to Amendment
The Applicant’s Amendment filed 07/07/2026 has been entered. Claim 17 has been canceled. Claims 1-16 and 18-20 have been canceled.
Response to Arguments
The Applicant requests that the Double Patenting rejection be held in abeyance until the Examiner identifies allowable subject matter. Accordingly, the Double Patenting rejection is maintained.
Applicant's arguments filed 07/07/2026 with respect to the prior art rejections have been fully considered but they are not persuasive.
Regarding claims 1, 10 and 15, the Applicant argues that the cited art Atsatt et al (US 20190044519) fails to teach the newly amended limitation “wherein the first memory column comprises a first shared data path coupled to a plurality of row controller configured to communicate via the first shared data path” and “wherein the second NOC comprises the first shared data path and the plurality of row controllers”. The Examiner respectfully disagrees. Atsatt discloses a plurality of row controllers (see figure 7, routers 98) that control the routing of information in the vertical shared data path that is the second NOC (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like). Therefore, Atsatt discloses the argued limitation as claimed.
Based on the reasoning above, the rejection should be maintained. Please see below for the detailed rejections.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,164,462. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patent.
Claim 1 of the instant application is anticipated by the patent’s claims 1 and 15 in that claims 1 and 15 of the patent contain all the limitation of claim 1 of the instant application. Please see table below for the claim comparison.
Further, the limitation of the other claims 2-20 are found with minor variations in the teaching of the patent claims 1-20.
Instant Application (18/912,321)
Patent No. 12,164,462
Claim 1: An integrated circuit comprising:
a logic fabric comprising a plurality of logic blocks and a first memory column, wherein the first memory column comprises a first shared data path coupled to a plurality of row controller
Claim 1: An integrated circuit, comprising: a plurality of microsectors arranged in a row and column grid, wherein the plurality of microsectors comprises a first microsector communicatively coupled to a first row controller;
a shared data path
Claim 15: the configuration memory of a microsector
a first network-on-chip (NOC) disposed around a partial perimeter of the plurality of logic blocks; and
Claim 1: a first network-on-chip disposed around at least a partial perimeter of a plurality of microsectors
a second NOC coupled to the first NOC, wherein the second NOC comprises the first shared data path and the plurality of row controllers.
Claim 1: transmit a command and first data from a second row controller to the first row controller using a second network-on-chip via a shared data path, down a column of rows
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Atsatt et al US 20190044519.
Regarding claim 1, Atsatt teaches an integrated circuit (see figure 3 and figure 33, FPGA 40) comprising:
a logic fabric comprising a plurality of logic blocks and a first memory column, wherein the first memory column comprises a first shared data path (fabric die 22 comprises fabric sectors 80 and sector aligned memory column 92, figure 33 shows a shared data path from A to B that comprises the memory column 92, see para 0117, the sector controller (SC) 58 may transfer data to a region of the sector-aligned memory 92 aligned with sector “A” of the fabric die 22, use the NOC 100 to transfer the data to a second region of the sector-aligned memory 92 aligned with sector “B” of the fabric die 22) coupled to a plurality of row controller configured to communicate via the first shared data path (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like);
a first network-on-chip (NOC) disposed around a partial perimeter of the plurality of logic blocks (see figure 3 shows interconnection resource 46 around a partial parameter of sectors 48, see para 0055, the interconnection resources 46 may act as a network, also see figure 33, horizontal network connecting sectors 80); and
a second NOC coupled to the first NOC, wherein the second NOC comprises the first shared data path (see figure 33, vertical network connecting sector 80 and sector aligned memory 92 of the shared data path from A to B, see para 0064, the NOC 100 may provide additional horizontal and vertical routing wires or pathways to facilitate to communication between sectors 48 of the fabric die 22, between sectors 90 of the base die 24, or between sectors 48 of the fabric die 22 and sectors 90 of the base die 24) and the plurality of row controllers (see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like e.g. via the vertical network).
Regarding claim 2, Atsatt further teaches a column manager coupled to the first NOC and the second NOC, wherein the column manager is configured to translate access commands and data between the first NOC and the second NOC (see figure 3, sector controller 58, see para 0058, the sector controller (SC) 58 may initiate a transfer of data from sector “A” of the fabric die 22 to region “C” of the sector-aligned memory 92 using the NOC 100 of the base die 24, also see para 0053, the sector controller 58 and/or device controller 60 may be augmented with numerous additional capabilities. Such capabilities may include coordinating memory transactions between local in-fabric memory (e.g., local fabric memory or CRAM being used for data storage) via the NOC, transactions between sector-aligned memory associated with that particular programmable logic sector 48 via the NOC, decrypting configuration data (bitstreams) 18, and locally sequencing reads and writes to implement error detection and correction on the configuration memory 52, and sequencing test control signals to effect various test modes).
Regarding claim 3, Atsatt further teaches the plurality of row controllers are of the first memory column (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like).
Regarding claim 4, Atsatt further teaches each row controller of the plurality of row controllers is configured to access a portion of the logic fabric (see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like).
Regarding claim 5, Atsatt further teaches a first row controller of the plurality of row controllers is configured to: determine whether at least a portion of an access command matches at least a portion of an identifier; and perform one or more operations in response to a match (see para 0110, the request may include an address range specified by the FPGA fabric 50… the memory manager 120 may cause desired contents of the in-fabric memory 114 at the specified address range to be transferred to the NOC 100).
Regarding claim 6, Atsatt further teaches a second memory column comprising a second shared data path; and a third NOC coupled to the first NOC, wherein the third NOC comprises the second shared data path (see figure 34, second sector aligned memory column 92 of the shared data path from A to C, also a vertical network at C is connected to the first network at A which comprises the data path A to C).
Regarding claim 7, Atsatt further teaches the logic fabric comprises an on-chip routing fabric configured to provide routing paths between the plurality of logic blocks (see figure 3, interconnection resource 46).
Regarding claim 8, Atsatt further teaches the first memory column comprise random-access-memory (RAM) cells (see para 0003, a programmable logic device may include programmable logic elements programmed by a form of memory known as configuration random access memory).
Regarding claim 9, Atsatt further teaches the plurality of logic blocks are arranged in a row and column grid (see figure 3, row and column grid of sectors 48).
Regarding claim 10, Atsatt teaches a programmable logic device (see figure 3 and figure 33, FPGA 40) comprising:
a logic fabric comprising a plurality of logic blocks and a first memory column having a first shared data path (fabric die 22 comprises fabric sectors 80 and sector aligned memory column 92, figure 33 shows a shared data path from A to B that comprises the memory column 92, see para 0117, the sector controller (SC) 58 may transfer data to a region of the sector-aligned memory 92 aligned with sector “A” of the fabric die 22, use the NOC 100 to transfer the data to a second region of the sector-aligned memory 92 aligned with sector “B” of the fabric die 22) coupled to a plurality of row controller configured to communicate via the first shared data path (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like);
a first network-on-chip (NOC) disposed around a partial perimeter of the plurality of logic blocks (see figure 3 shows interconnection resource 46 around a partial parameter of sectors 48, see para 0055, the interconnection resources 46 may act as a network, also see figure 33, horizontal network connecting sectors 80); and
a second NOC coupled to the first NOC, wherein the second NOC comprises the first shared data path and the plurality of row controllers (see figure 33, vertical network connecting sector 80 and sector aligned memory 92 of the shared data path from A to B, see para 0064, the NOC 100 may provide additional horizontal and vertical routing wires or pathways to facilitate to communication between sectors 48 of the fabric die 22, between sectors 90 of the base die 24, or between sectors 48 of the fabric die 22 and sectors 90 of the base die 24) and the plurality of row controllers (see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like e.g. via the vertical network or second NOC).
Regarding claim 11, Atsatt further teaches a column manager coupled to the first NOC and the second NOC, wherein the column manager is configured to translate access commands and data between the first NOC and the second NOC (see figure 3, sector controller 58, see para 0058, the sector controller (SC) 58 may initiate a transfer of data from sector “A” of the fabric die 22 to region “C” of the sector-aligned memory 92 using the NOC 100 of the base die 24, also see para 0053, the sector controller 58 and/or device controller 60 may be augmented with numerous additional capabilities. Such capabilities may include coordinating memory transactions between local in-fabric memory (e.g., local fabric memory or CRAM being used for data storage) via the NOC, transactions between sector-aligned memory associated with that particular programmable logic sector 48 via the NOC, decrypting configuration data (bitstreams) 18, and locally sequencing reads and writes to implement error detection and correction on the configuration memory 52, and sequencing test control signals to effect various test modes).
Regarding claim 12, Atsatt further teaches the second NOC comprises a plurality of row controllers of the first memory column (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like. In certain embodiments, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like), wherein each row controller of the plurality of row controllers is configured to access a portion of the logic fabric (see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like).
Regarding claim 13, Atsatt further teaches a second memory column comprising a second shared data path; and a third NOC coupled to the first NOC, wherein the third NOC comprises the second shared data path (see figure 34, second sector aligned memory column 92 of the shared data path from A to C, also a vertical network at C is connected to the first network at A which comprises the data path A to C).
Regarding claim 14, Atsatt further teaches the logic fabric comprises an on-chip routing fabric configured to provide routing paths between the plurality of logic blocks (see figure 3, interconnection resource 46), wherein the first memory column comprise random-access-memory (RAM) cells (see para 0003, a programmable logic device may include programmable logic elements programmed by a form of memory known as configuration random access memory) storing data indicative of routing paths of the on-chip routing fabric (see para 0054, a separate routine in a memory containing a control program. This control program memory may be fixed in a read-only memory (ROM) or stored in a writable memory, such as random-access memory (RAM)).
Regarding claim 15, Atsatt teaches a logic fabric (see figure 3 and figure 33, FPGA 40) comprising:
a plurality of logic blocks ((fabric die 22 comprises fabric sectors 80);
a first memory column comprising programmable memory and a first shared data path (sector aligned memory column 92, figure 33 shows a shared data path from A to B that comprises the memory column 92, see para 0117, the sector controller (SC) 58 may transfer data to a region of the sector-aligned memory 92 aligned with sector “A” of the fabric die 22, use the NOC 100 to transfer the data to a second region of the sector-aligned memory 92 aligned with sector “B” of the fabric die 22) coupled to a plurality of row controller configured to communicate via the first shared data path (see para 0062, the NOC system 100 may provide communication paths between each sector 90 via routers 98 or the like), wherein the first memory column is configured to couple to a first network-on-chip (NOC) disposed around a partial perimeter of the plurality of logic blocks (see figure 3 shows interconnection resource 46 around a partial parameter of sectors 48, see para 0055, the interconnection resources 46 may act as a network, also see figure 33, horizontal network connecting sectors 80); and
a second NOC disposed at least partially within one or more logic blocks of the plurality of logic blocks, wherein the second NOC comprises the first shared data path and the plurality of row controllers, wherein the second NOC is configured to provide direct access to the first memory column and at least a portion of the one or more logic blocks of the plurality of logic blocks (see figure 33, vertical network connecting sector 80 and sector aligned memory 92 of the shared data path from A to B, see para 0064, the NOC 100 may provide additional horizontal and vertical routing wires or pathways to facilitate to communication between sectors 48 of the fabric die 22, between sectors 90 of the base die 24, or between sectors 48 of the fabric die 22 and sectors 90 of the base die 24, also see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like e.g. via the vertical network or second NOC).
Regarding claim 16, Atsatt further teaches the second NOC is configured to provide access to the first memory column and at least the portion of the one or more logic blocks to the first NOC (see para 0064, the NOC 100 may provide additional horizontal and vertical routing wires or pathways to facilitate to communication between sectors 48 of the fabric die 22, between sectors 90 of the base die 24, or between sectors 48 of the fabric die 22 and sectors 90 of the base die 24).
Regarding claim 18, Atsatt further teaches the second NOC comprises a plurality of row controllers of the first memory column (see para 0062, the routers 98 may route user data between sectors 90 of the base die 24, to sectors 48 of the fabric die 22, and the like), wherein a first row controller of the plurality of row controllers is configured to: determine whether at least a portion of an access command matches at least a portion of an identifier; and perform one or more operations in response to a match (see para 0110, the request may include an address range specified by the FPGA fabric 50… the memory manager 120 may cause desired contents of the in-fabric memory 114 at the specified address range to be transferred to the NOC 100).
Regarding claim 19, Atsatt further teaches a second memory column comprising a second shared data path; and a third NOC comprising the second shared data path, wherein the third NOC is configured to provide direct access to the second memory column and at least a portion of the plurality of logic blocks (see figure 34, second sector aligned memory column 92 of the shared data path from A to C, also a vertical network at C is connected to the first network at A which comprises the data path A to C).
Regarding claim 20, Atsatt further teaches an on-chip routing fabric configured to provide routing paths between the plurality of logic blocks (see figure 3, interconnection resource 46), wherein the first memory column comprises random-access-memory (RAM) cells (see para 0003, a programmable logic device may include programmable logic elements programmed by a form of memory known as configuration random access memory) storing data indicative of routing paths of the on-chip routing fabric (see para 0054, a separate routine in a memory containing a control program. This control program memory may be fixed in a read-only memory (ROM) or stored in a writable memory, such as random-access memory (RAM)).
Regarding claim 21, Asatt further teaches the plurality of row controllers are disposed between portions of the plurality of logic blocks (see figure 7 showings the routers 98 disposed between the sectors).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee US 20070147154 discloses a row controller in a semiconductor device
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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/PHONG H DANG/Primary Examiner, Art Unit 2184
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