DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS."
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/10/2024 was filed after the mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. US Patent No. 12,147,262 in view of Liu US Pub. No. 2004/0257856.
Regarding claim 1 of current Application No. 18/912326, claim 1 of US Patent ‘262 recites “A first-in first-out buffer (FIFO) comprising: a memory that stores data in a plurality of memory entries of the memory using a first clock signal and outputs the stored data using a second clock signal in response to receiving a read enable signal”; and lookahead circuitry coupled to the memory configured to generate the read-enable signal. ‘262, in claim 5, further teaches “ the data stored in the threshold number of memory entries is associated with a portion of a packet.”
‘262 does not expressly claim that “the lookahead circuity is configured to generate the read-enable signal in response to the memory inputting an end of packet (EOP) indication of the data packet.”
Liu teaches “the end of a packet is indicated by a data word encoded as an end-of-packet (EOP) indicator.” Liu further teaches that “FIFO memory is ready to be read when an end-of-packet (EOP) indicator has been stored in SRAM array 45 for a packet, or when a sufficient amount of data for a give packet has been stored” [0070]. Liu explains that the FIFO asserts an active RD_RDY output-control signal when either sufficient packet data or a complete packet has been stored “This function is effected in FIFO memory 40 by its asserting of an active signal on control line RD_RDY when the packet conditions (sufficient data, or complete packet) indicate that a read of the packet stream data in FIFO memory 40 may be made” [0068]. Liu claim 11 expressly recites “packet management logic, for controlling the operation of the memory circuit, the packet management logic for enabling the outputting of output data words corresponding to a packet, responsive to detecting the writing of a start-of-packet indicator and an end-of-packet indicator.” Liu method claim 23 similarly recites “responsive to detecting the writing of input data words including a start-of-packet indicator and of an end-of-packet indicator, enabling the output of data words corresponding to the packet.” Accordingly, Liu teaches detecting the writing or storage of EOP and, in response to that detection, enabling output of the packet.
It would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the lookahead circuitry claimed by Foo to generate the read-enable signal in response to the memory inputting the EOP indication, as taught by Liu. The motivation would have been to permit a completed packet—particularly a short packet that does not reach ‘262’s threshold number of memory entries—to be promptly released from the FIFO without waiting for additional data or an unnecessary buffer interval. The modification would have predictably used Liu’s known complete-packet detection condition in ‘262’s existing lookahead circuitry, while retaining ‘262’s existing function of generating the read-enable signal. Thus, the combination teaches the entire limitation “lookahead circuitry coupled to the memory, wherein the lookahead circuitry is configured to generate the read enable signal in response to the memory inputting an end of packet (EOP) indication of the data packet.”
Therefore, claim 1 is not patentably distinct from US Patent No. ‘262 claim 1 in view of Liu.
Regarding claim 2, Foo claim 15 teaches that transmission of the packet EOP occurs: “one or more clock cycles after storing the end of the packet.” Liu teaches that asserting read enable initiates reading, with output data appearing after an access time, “e.g., one cycle of clock CLK.” A period of one or more clock cycles encompasses output in fewer than six cycles, particularly one through five cycles. Alternatively, selecting fewer than six cycles would have been an obvious optimization of the response time taught by Foo and Liu, motivated by their common objective of reducing delay in releasing available packet data. Therefore, claim 2 is not patentably distinct.
Regarding claim 3, Liu teaches that the FIFO becomes ready to be read when the EOP indication has been stored and asserts RD_RDY when a “complete packet” indicates that reading may begin. It would have been obvious to generate Foo’s read-enable signal upon that condition without adding an unnecessary post-EOP buffer interval, thereby producing the predictable latency reduction sought by both references. Therefore, the limitation that the memory outputs at least a portion of the data “without a buffer time in response to inputting the EOP indication” does not patentably distinguish claim 3.
Regarding claim 4, ‘262 claim 6 recites “the FIFO is configured to allow reading the stored portion of the data while storing a remaining portion of the data associated with a packet in response to the read enable signal.” ‘262 therefore teaches outputting data in response to the read-enable signal while inputting additional data. The claim does not require the additional data to belong to a different packet. Therefore, claim 4 is not patentably distinct.
Regarding claim 5, ‘262 claim 1 expressly recites “a plurality of memory entries” that store the data. Therefore, claim 5 is not patentably distinct.
Regarding claim 6, ‘262 claim 4 recites “at least one memory entry of the number of memory entries stores a plurality of data bytes.” Thus, ‘262 teaches memory entries configured to store a number of data bytes. Therefore, claim 6 is not patentably distinct.
Regarding claim 7, ‘262 claim 1 expressly teaches that the lookahead circuitry generates the read-enable signal “based on the threshold number of memory entries storing the portion of the data,” where the threshold number is less than the plurality of memory entries. Liu teaches using completion of the packet, indicated by written EOP, as an alternative read-enabling condition when a sufficient data threshold has not otherwise been reached. It would have been obvious to configure ‘262’s lookahead circuitry to generate read enable based on either the threshold condition claimed by ‘262 or the EOP condition taught by Liu so that both long and short packets could be promptly released. Therefore, claim 7 is not patentably distinct.
Regarding claim 8, ‘262 claim 5 expressly teaches “the data stored in the threshold number of memory entries is associated with a portion of a packet.” Therefore, claim 8 is not patentably distinct.
Regarding claim 9, ‘262 claims 19–21 teach a read-enable threshold selected between a specified value and a programmed value and expressly state that the specified value is determined before runtime. A threshold selected or determined before runtime is a predetermined threshold. Liu additionally describes packet cut-through based on a “configurable threshold.” It would have been obvious to predetermine or program the threshold before operation so that the FIFO begins operation with an established packet-release criterion. Therefore, claim 9 is not patentably distinct.
Regarding claim 10, ‘262 claim 8 recites: “a first integrated circuit transmitting a data packet using a first clock frequency”; “a second integrated circuit receiving the data packet using a second clock frequency”; A FIFO memory storing the packet data using the first clock and outputting it using the second clock in response to a read-enable signal; and Lookahead circuitry configured to generate the read-enable signal.
‘262 does not expressly claim that the data packet comprises an EOP indication and that the lookahead circuitry generates the read-enable signal in response to the memory inputting EOP.
Liu teaches that packet data includes an EOP indicator, that the EOP indicator is written into the FIFO memory, and that packet-management logic enables output in response to detecting the writing of SOP and EOP. Liu claim 37, for example, recites a network node containing transmit and receive FIFO buffers and “packet management logic…for enabling the outputting of output data words corresponding to a packet, responsive to detecting the writing of a start-of-packet indicator and an end-of-packet indicator.”
It would have been obvious to modify the lookahead circuitry claimed by ‘262 to generate its existing read-enable signal in response to Liu’s EOP-storage condition so that a completed packet may be promptly read even when the packet does not reach the threshold number of memory entries. The modification would produce the predictable result of reducing delay for short packets. Therefore, claim 10 is not patentably distinct from ‘262 claim 8 in view of Liu.
Regarding claim 11, ‘262 claim 15 teaches transmission of EOP one or more clock cycles after storing EOP, while Liu teaches data output after an access time of, for example, one clock cycle following read enable. Output in one clock cycle is output in fewer than six clock cycles. Alternatively, the recited upper limit represents an obvious optimization of known FIFO-response time. Therefore, claim 11 is not patentably distinct.
Regarding claim 12, ‘262 claim 11 recites “the FIFO is configured to allow reading the stored portion of the data while storing a remaining portion of the data associated with the data packet in response to the read enable signal.” Accordingly, ‘262 teaches outputting data in response to read enable while inputting additional data. Therefore, claim 12 is not patentably distinct.
Regarding claim 13, ‘262 claim 8 expressly recites lookahead circuitry configured to generate read enable “based on the threshold number of memory entries storing the portion of the data,” where the threshold number is less than the plurality of memory entries. Therefore, claim 13 is not patentably distinct.
Regarding claim 14, ‘262 claim 8 expressly recites determining the threshold number of memory entries “based on determining a difference between frequencies of the first clock signal and the second clock signal.” Therefore, claim 14 is not patentably distinct.
Regarding claim 15, ‘262 claim 14 recites Receiving, by a FIFO, data associated with a packet using a first clock signal; Generating, by lookahead circuitry, a read-enable signal; Outputting at least a portion of the packet data using a second clock signal; and Reducing delay by permitting transmission while a remaining portion is being stored.
‘262 does not expressly claim “generating, by the FIFO, a read enable signal in response to detecting the EOP indication.”
Liu method claim 23 teaches “responsive to detecting the writing of input data words including a start-of-packet indicator and of an end-of-packet indicator, enabling the output of data words corresponding to the packet.” Liu further explains that the FIFO asserts RD_RDY when the EOP has been stored or a sufficient amount of packet data has been stored. Thus, Liu teaches detecting EOP and responsively enabling output [0068].
It would have been obvious to modify the method claimed by ‘262 so that ‘262’s read-enable signal is generated in response to detecting EOP, as taught by Liu. The reason would have been to permit immediate release of a completed short packet that does not satisfy ‘262’s threshold, thereby reducing delay compared with waiting for additional data or an unnecessary buffer interval. The resulting method would output the stored packet portion using the second clock with reduced delay after receiving EOP. Therefore, claim 15 is not patentably distinct from ‘262 claim 14 in view of Liu.
Regarding claim 16, Foo claim 15 teaches transmission of EOP one or more clock cycles after storing EOP. Liu teaches output following read enable after an access time of, for example, one clock cycle. The combined teachings therefore encompass output in fewer than six clock cycles after receiving EOP. Alternatively, the recited limit would have been an obvious result-effective optimization of FIFO latency. Therefore, claim 16 is not patentably distinct.
Regarding claim 17, ‘262 claim 14 expressly recites “allowing, by the FIFO, transmission of the portion of the data…in response to the read enable signal.” Therefore, claim 17 is not patentably distinct.
Regarding claim 18, ‘262 claim 14 teaches “allowing, by the FIFO, transmission of the portion of the data…while storing a remaining portion of the data in response to the read enable signal.” ‘262 claim 18 further recites that allowing transmission of the stored portion is simultaneous with storing the remaining portion. Therefore, ‘262 teaches outputting data in response to read enable while inputting additional data. Liu supplies the EOP-responsive enabling condition. Therefore, claim 18 is not patentably distinct.
Regarding claim 19, ‘262 claim 14 recites storing data in “a plurality of data entries of a memory of the FIFO.” ‘262 claim 4 further teaches that at least one memory entry stores a plurality of data bytes. Thus, ‘262 teaches storing the input data in a plurality of memory entries, each capable of storing a number of data bytes. Therefore, claim 19 is not patentably distinct.
Regarding claim 20, ‘262 claim 14 expressly recites generating the read-enable signal based on “the threshold number of data entries storing the portion of the data,” where the threshold number is less than the plurality of data entries. Liu teaches additionally enabling output when EOP has been written, particularly where a complete packet does not reach the sufficient-data threshold. It would have been obvious to employ both conditions so that a packet is released upon reaching the threshold or, for a shorter packet, upon receiving EOP. Therefore, claim 20 is not patentably distinct.
In summary, the subject matter of claims 1–20 would have been an obvious variation of the inventions claimed in U.S. Patent No. 12,147,262 in view of Liu. The claimed EOP-responsive read-enable condition represents the predictable application of Liu’s known complete-packet/EOP detection technique to the threshold-controlled lookahead FIFO claimed by Foo.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 10-11, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holm et al. US Patent No. 6,687,225 (“Holm”) in view of Koutsoures et al. US Pub. No. 2009/0323728 (“Koutsoures”)1 .
Regarding claim 1, Holm teaches a first-in first-out buffer (FIFO) [transmit FIFO 16 or receive FIFO 18, including FIFO queue 50 and frame-in-FIFO detector 52] comprising:
a memory [dual-port RAM of FIFO queue 50] configured to input data using a first clock signal [WRITE CLOCK], and output the data using a second clock signal [READ CLOCK], wherein the data is associated with a data packet [data frames or packets written as successive words or bytes] [SEE FIGS. 1 and 2];
FIFO 16, 18 includes FIFO queue 50 and frame-in-FIFO detector 52. FIFO queue 50 has a write port 54 and a read port 56. Write port 54 includes a data input labeled DATA[7:0], an end-of-frame flag input labeled EOF, and a write control input labeled WRITE_STROBE. Read port 56 includes a start threshold flag output labeled START, a data output labeled DATA[7:0], an end-of-frame flag output labeled EOF, and a read control input labeled READ_STROBE. In one embodiment, FIFO queue 50 includes a dual-port RAM. [col. 5, lines 55-66]
In the embodiment shown in FIG. 2, FIFO 16, 18 is asynchronous. Dashed line 60 represents a dividing line between a first, WRITE_CLOCK domain and second, READ_CLOCK domain, which are asynchronous to one another. Write port 54 resides in the WRITE_CLOCK domain, while read port 56 resides in the READ_CLOCK domain. [col. 6, lines 3-11]
During a write operation, DMA controller 20, for example, writes each successive data frame to FIFO queue 50 one byte at a time. DMA controller 20 applies each byte to data input DATA[7:0] along with a corresponding EOF flag to the EOF input and pulses write control input WRITE_STROBE. FIFO queue 50 receives the write pulse and stores the data byte and corresponding EOF flag at a selected address. The control circuitry within FIFO queue 50 maintains a write pointer (not shown) which points to a current address within the FIFO at which the word or byte will be stored. FIFO queue 50 increments the address of the write pointer after each word or byte is written into the FIFO. When the last word or byte of a data frame is being written to FIFO queue 50, DMA controller 20 asserts the corresponding EOF flag.
(In other words, during a write operation, DMA controller 20 writes each successive data frame to FIFO queue 50 one byte at a time. FIFO queue 50 stores each data byte and its corresponding EOF flag at a selected address. When the last word or byte of the data frame is written, DMA controller 20 asserts the corresponding EOF flag. [col. 6, lines 25-46]
lookahead circuitry coupled to the memory [frame-in-FIFO detector 52, including AND gates 70 and 72, Gray-code counters 74 and 76, re-synchronizing circuit 78, and comparator 80], wherein the lookahead circuitry detects the memory inputting an end of packet (EOP) indication of the data packet [the EOF flag stored with the last word or byte] and produces a FRAME_IN_FIFO output indicating that a complete unread frame is stored;
Frame-in-FIFO detector 52 detects whether the end of at least one data frame is stored in FIFO queue 50 by monitoring the signals supplied to write port 54 and read port 56. The detector includes logic AND gates 70 and 72, Gray-code counters 74 and 76, re-synchronizing circuit 78, and comparator 80. [col. 7, lines 1-10]
Whenever the last byte of a data frame is being written into FIFO queue 50, the EOF flag is asserted while the WRITE_STROBE input is pulsed. This causes the WRITE_INCREMENT output of AND gate 70 to go high, and Gray-code counter 74 increments WRITE_COUNT. Thus, WRITE_COUNT indicates the number of data frames written to FIFO queue 50. [col. 7, lines 15-27]
Comparator 80 compares the number of data frames written into FIFO queue 50, as indicated by WRITE_COUNT_RESYNC, with the number of data frames read from FIFO queue 50, as indicated by READ_COUNT, and generates a compare output on FRAME_IN_FIFO output 94. FRAME_IN_FIFO output 94 indicates whether at least one data frame is in FIFO queue 50. [col. 7, lines 54-63]
The FRAME_IN_FIFO output can be used by the reading device (either data interface controller 14 or DMA controller 20) to ensure that all data frames are read from FIFO queue 50 efficiently. For example, during a transmit operation, if the data frame being written to FIFO queue 50 is not large enough to trigger the START threshold flag, and the data frame is the last data frame being sent by DMA controller 20, data interface controller 14 can monitor the FRAME_IN_FIFO output to determine whether there are any remaining data frames in FIFO queue 50 that can be transmitted. If the FRAME_IN_FIFO output is asserted (or-non-zero), then data interface controller 14 can begin. transmitting another data frame from FIFO queue 50 (even if the START flag is not asserted). [col. 8, lines 19-33]
Holm therefore teaches detecting storage of the packet's EOF/EOP and generating a frame-available signal that causes or permits the reading device to begin reading. Holm, however, does not expressly characterize FRAME_IN_FIFO output 94 itself as the claimed read enable signal that directly controls output of the memory. Holm does not expressly teach the lookahead circuitry is configured to generate the read enable signal.
Koutsoures teaches an asynchronous FIFO having circuitry that generates an asserted read-data-ready signal to authorize output of packet data in a receiving clock domain. Specifically, Koutsoures teaches packet data entering a FIFO in a producer clock domain and leaving the FIFO in a consumer clock domain, with a read-data-ready signal indicating that buffered data is available for output [SEE FIGS. 1 and 3].
It is common for packet based digital systems to send and receive data across clock domains. One known method for sending packets between digital systems having different clock domains is to use an asynchronous FIFO. [¶ 2-3]
The transmitting circuitry's clock and the receiving circuitry's clock are independent of each other and are not synchronized. The provision of data clocked at a first frequency by a sending device and received and sampled at a second clock frequency may produce metastability concerns. [¶ 17-18]
The asynchronous FIFO includes circuitry that determines the level of data in the buffer and provides a read-data-ready signal at an output of the asynchronous FIFO when the specified safe data-level condition is satisfied. [¶ 5-7; claims 1 and 3]
Koutsoures further expressly recites receiving data packets in association with a first clock signal, providing an asserted read-data-ready signal, and providing the packets for reading in association with a second clock signal. [claim 14 of Koutsoures]
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to configure Holm's frame-in-FIFO detector and FRAME_IN_FIFO output to generate or control the read-data-ready/read-enable signal taught by Koutsoures. Holm expressly teaches that FRAME_IN_FIFO is asserted when its EOF-responsive write count establishes that a complete unread frame is stored, and that the reading device uses the asserted signal to begin reading even when the ordinary START threshold has not been reached. Koutsoures teaches using a read-data-ready signal as the interface by which asynchronous FIFO control circuitry authorizes output of buffered packet data in the receiving clock domain. The modification would have predictably provided an explicit read-enable control responsive to Holm's detection that the EOP/EOF had entered the FIFO, thereby enabling prompt and efficient packet output while reducing the risk of FIFO underflow, data interruption, and clock-domain synchronization error. Thus, the combination would have resulted in lookahead configured to generate the read enable signal in response to the memory inputting an end of packet (EOP) indication.
Regarding claim 2, Holm in view of Koutsoures teaches the FIFO of claim 1 for the reasons set forth above. Holm further teaches that its EOF-responsive FRAME_IN_FIFO output permits the reading device to begin transmitting a completed frame even when the ordinary START threshold has not been asserted.
Holm teaches The FRAME_IN_FIFO output can be used by the reading device to ensure that all data frames are read efficiently. If a frame is not large enough to trigger the START threshold, the data interface controller can monitor FRAME_IN_FIFO and, when that output is asserted, begin transmitting the frame from FIFO queue 50 even though START is not asserted. [col. 8, lines 19-33]
Koutsoures teaches an asynchronous FIFO in which decision circuitry produces a read-data-ready signal indicating when data is available to the receiving clock domain. The transmitting and receiving clocks are independent, and the read-data-ready signal is derived through comparison and synchronization circuitry. [¶ 5-7 and 17-18; claims 1, 3, and 14 of Koutsoures]
Holm and Koutsoures do not expressly teach that the first output occurs in “less than six” cycles. However, once Holm's synchronized frame-complete indication is asserted, the number of read-clock cycles before output is a result-effective timing parameter governed by the number of synchronization and output-register stages. A person of ordinary skill would have been motivated to use fewer than six cycles through routine selection of the number of pipeline/synchronization stages because both references seek prompt and efficient FIFO transfer while avoiding metastability and underflow. Selecting fewer than six cycles would have predictably reduced latency while retaining the known synchronization protection, and determining a workable number within that range would have required only routine timing verification. Accordingly, it would have been obvious to configure the lookahead circuitry to cause output of at least a portion of the data in fewer than six cycles of the second clock after inputting the EOP indication.
Regarding claim 3, Holm in view of Koutsoures teaches the memory is configured to output at least a portion of the data without a buffer time in response to inputting the EOP indication. Holm teaches by passing the ordinary START-threshold wait when EOF establishes that the complete frame has entered the FIFO. Thus, the frame may be output without the additional threshold buffer time that would otherwise occur after EOP.
Holm further teaches if FRAME_IN_FIFO is asserted, the reading device can begin transmitting the frame even if the START flag is not asserted. During receive operation, the DMA controller may likewise continue reading through the end of the frame even after START has been deasserted. [see col. 8, lines 19-33]
It would have been obvious to use Koutsoures's read-data-ready signal to implement Holm's EOF-responsive authorization without an additional post-EOP buffer interval. The modification would have eliminated unnecessary waiting after the FIFO already established that the EOP and complete packet were stored, predictably reducing packet latency while maintaining complete-packet output.
Regarding claim 10, Holm teaches an electronic system comprising:
a transmitting circuit [data routing circuit/DMA controller 20] transmitting a data packet using a first clock signal [WRITE CLOCK], the data packet comprising an end of packet (EOP) indication [EOF flag asserted with the final word or byte of the frame] [SEE FIGS. 1 and 2];
Holm teaches DMA controller 20 operates as a data routing circuit and routes transmit data in multiple-bit data frames or packets from external memory 30 to transmit FIFO 16. DMA controller 20 transfers each data frame or packet a byte or word at a time at the DMA transfer rate until the entire data frame has been transferred. [col. 4, lines 43-62]
During a write operation, DMA controller 20 writes each successive data frame to FIFO queue 50 one byte at a time. DMA controller 20 applies each byte to data input DATA[7:0] along with a corresponding EOF flag and pulses WRITE_STROBE. FIFO queue 50 stores the data byte and corresponding EOF flag at a selected address. When the last word or byte of the frame is written, DMA controller 20 asserts the corresponding EOF flag. [col. 6, lines 25-46]
a receiving circuit [data interface controller 14] receiving the data packet using a second clock signal [READ CLOCK] [SEE FIGS. 1 and 2]; and
Write port 54 resides in the WRITE_CLOCK domain, while read port 56 resides in the READ_CLOCK domain. In transmit FIFO 16, write port 54 is coupled to DMA controller 20, which operates the write port in the WRITE_CLOCK domain at the DMA transfer rate. Read port 56 is coupled to data interface controller 14, which operates the read port in the READ_CLOCK domain at the fixed-speed data-interface rate. [col. 6, lines 19-29]
a first-in first-out buffer (FIFO) [transmit FIFO 16, including FIFO queue 50 and frame-in-FIFO detector 52] comprising:
a memory [dual-port RAM of FIFO queue 50] configured to input data of the data packet based on the first clock signal [WRITE CLOCK] and output the data based on the second clock signal [READ CLOCK] [SEE FIG. 2]; and
FIFO 16, 18 includes FIFO queue 50 and frame-in-FIFO detector 52. FIFO queue 50 has write port 54 and read port 56. Write port 54 includes a data input, an EOF input, and WRITE_STROBE. Read port 56 includes data and EOF outputs and READ_STROBE. In one embodiment, FIFO queue 50 includes a dual-port RAM. [col. 5, lines 55-67]
lookahead circuitry coupled to the memory [frame-in-FIFO detector 52, including AND gates 70 and 72, Gray-code counters 74 and 76, re-synchronizing circuit 78, and comparator 80], wherein the lookahead circuitry detects the memory inputting the EOP indication [the EOF flag stored with the last word or byte] and produces FRAME_IN_FIFO output 94 indicating that a complete unread frame is stored.
Holm teaches Frame-in-FIFO detector 52 detects whether the end of at least one data frame is stored in FIFO queue 50 by monitoring the signals supplied to write port 54 and read port 56. The detector includes logic AND gates 70 and 72, Gray-code counters 74 and 76, re-synchronizing circuit 78, and comparator 80. [col. 7, lines 1-10]
Whenever the last byte of a data frame is being written into FIFO queue 50, the EOF flag is asserted while WRITE_STROBE is pulsed. This causes WRITE_INCREMENT to go high and Gray-code counter 74 to increment WRITE_COUNT, which indicates the number of data frames written to FIFO queue 50. [col. 7, lines 15-27]
Comparator 80 compares WRITE_COUNT_RESYNC with READ_COUNT and generates FRAME_IN_FIFO output 94, which indicates whether at least one data frame is stored in FIFO queue 50. [col. 7, lines 53-62]
The FRAME_IN_FIFO output can be used by the reading device to ensure that all data frames are read efficiently. If a frame is not large enough to trigger the START threshold, the data interface controller can monitor FRAME_IN_FIFO and, when the output is asserted, begin transmitting the frame from FIFO queue 50. [col. 8, lines 19-33]
Holm therefore teaches first and second circuitry operating in respective write and read clock domains, an asynchronous FIFO memory between those circuits, storage and detection of an EOF/EOP indication, and a resulting FRAME_IN_FIFO signal that causes or permits the reading device to begin reading. Holm, however, does not expressly identify its transmitting and receiving circuits as separate first and second integrated circuits or characterize FRAME_IN_FIFO output 94 itself as the claimed read enable signal that directly controls memory output.
Koutsoures teaches a packet-based digital system having producer circuitry in a producer clock domain and consumer circuitry in a consumer clock domain, with an asynchronous FIFO transferring packet data between the independently clocked circuits. Thus, Koutsoures teaches a first integrated circuit transmitting a data and a second integrated circuit receiving data. Koutsoures further teaches FIFO decision circuitry that generates a read-data-ready signal authorizing the consumer-side output of buffered data [SEE FIGS. 1 and 3].
Koutsoures teaches it is common for packet based digital systems to send and receive data across clock domains. One known method for sending packets between digital systems having different clock domains is to use an asynchronous FIFO. [¶ 2-3]
The transmitting circuitry's clock and the receiving circuitry's clock are independent of each other and are not synchronized. The provision of data clocked at a first frequency by a sending device and received and sampled at a second frequency by a receiving device may present metastability concerns. [¶ 17-18]
The asynchronous FIFO includes circuitry that determines the level of data in the buffer and provides a read-data-ready signal at an output of the asynchronous FIFO when the specified safe data-level condition is satisfied. [¶ 5-7; claims 1 and 3]
Koutsoures expressly recites receiving data packets in association with a first clock signal, providing an asserted read-data-ready signal, and providing the data packets for reading in association with a second clock signal. [claim 14 of Koutsoures]
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to implement Holm's transmitting and receiving circuitry as respective integrated circuits operating in the producer and consumer clock domains taught by Koutsoures, and to configure Holm's frame-in-FIFO detector and FRAME_IN_FIFO output to control Koutsoures's read-data-ready/read-enable signal. Both references address packet transfer through an asynchronous FIFO between independently clocked transmitting and receiving circuitry. Implementing the functional blocks as integrated circuits was a conventional hardware implementation. Using Holm's EOF-responsive frame-complete indication to control Koutsoures's read-data-ready signal would have predictably authorized reading once a complete unread packet was present, thereby improving packet transfer while reducing underflow and clock-domain synchronization error.
Regarding claim 11, Holm teaches that its EOF-responsive FRAME_IN_FIFO output permits the reading device to begin transmitting a completed frame even when the ordinary START threshold has not been asserted. Holm further teaches the FRAME_IN_FIFO output can be used by the reading device to ensure that all data frames are read efficiently. If a frame is not large enough to trigger the START threshold, the data interface controller can monitor FRAME_IN_FIFO and, when that output is asserted, begin transmitting the frame from FIFO queue 50 even though START is not asserted.
Koutsoures teaches an asynchronous FIFO whose decision circuitry generates a read-data-ready signal indicating that buffered data may be output using the receiving clock. The transmitting and receiving clocks are independent, and the signal is derived using comparison and synchronization circuitry. [¶ 5-7 and 17-18; claims 1, 3, and 14]
Holm and Koutsoures do not expressly recite “less than six” receiving-clock cycles. However, after Holm's synchronized frame-complete indication is asserted, the number of cycles before output is a result-effective timing parameter governed by the synchronization and output stages. A person of ordinary skill would have used fewer than six cycles through routine selection of those stages to reduce latency while retaining synchronization protection. Determining a workable number would have required only routine timing verification. Accordingly, outputting at least a portion of the data in fewer than six cycles after EOP would have been obvious.
15. A method comprising:
inputting, by a first-in first-out buffer (FIFO), data using a first clock signal, wherein the data is associated with a data packet having an end of packet (EOP) indication;
generating, by the FIFO, a read enable signal in response to detecting the EOP indication; and
outputting, by the FIFO, at least a portion of the data using a second clock signal with a reduced delay after receiving the EOP indication based on the read enable signal, wherein the reduced delay is compared to a delay associated with outputting the portion of the data using the second clock signal without generating the read enable signal.
Regarding claim 15, Holm teaches a method comprising:
inputting, by a first-in first-out buffer (FIFO) [transmit FIFO 16 or receive FIFO 18, including FIFO queue 50], data using a first clock signal [WRITE CLOCK], wherein the data is associated with a data packet having an end of packet (EOP) indication [a frame or packet whose final word or byte includes an asserted EOF flag] [SEE FIGS. 1 and 2];
FIFO 16, 18 includes FIFO queue 50 and frame-in-FIFO detector 52. FIFO queue 50 has a write port 54 and a read port 56. Write port 54 includes a data input labeled DATA[7:0], an end-of-frame flag input labeled EOF, and a write control input labeled WRITE_STROBE. Read port 56 includes a start threshold flag output labeled START, a data output labeled DATA[7:0], an end-of-frame flag output labeled EOF, and a read control input labeled READ_STROBE. In one embodiment, FIFO queue 50 includes a dual-port RAM. [col. 5, lines 55-66]
In the embodiment shown in FIG. 2, FIFO 16, 18 is asynchronous. Dashed line 60 represents a dividing line between a first, WRITE_CLOCK domain and second, READ_CLOCK domain, which are asynchronous to one another. Write port 54 resides in the WRITE_CLOCK domain, while read port 56 resides in the READ_CLOCK domain. [col. 6, lines 3-11]
During a write operation, DMA controller 20, for example, writes each successive data frame to FIFO queue 50 one byte at a time. DMA controller 20 applies each byte to data input DATA[7:0] along with a corresponding EOF flag to the EOF input and pulses write control input WRITE_STROBE. FIFO queue 50 receives the write pulse and stores the data byte and corresponding EOF flag at a selected address. The control circuitry within FIFO queue 50 maintains a write pointer (not shown) which points to a current address within the FIFO at which the word or byte will be stored. FIFO queue 50 increments the address of the write pointer after each word or byte is written into the FIFO. When the last word or byte of a data frame is being written to FIFO queue 50, DMA controller 20 asserts the corresponding EOF flag.
(In other words, during a write operation, DMA controller 20 writes each successive data frame to FIFO queue 50 one byte at a time. FIFO queue 50 stores each data byte and its corresponding EOF flag at a selected address. When the last word or byte of the data frame is written, DMA controller 20 asserts the corresponding EOF flag. [col. 6, lines 25-46]
detecting the EOP indication [frame-in-FIFO detector 52 detects that the EOF flag associated with the final byte has been stored] and generating a frame-available output in response [FRAME_IN_FIFO output 94]; and
Frame-in-FIFO detector 52 detects whether the end of at least one data frame is stored in FIFO queue 50 by monitoring the signals supplied to write port 54 and read port 56. The detector includes logic AND gates 70 and 72, Gray-code counters 74 and 76, re-synchronizing circuit 78, and comparator 80. [col. 7, lines 1-10]
Whenever the last byte of a data frame is being written into FIFO queue 50, the EOF flag is asserted while WRITE_STROBE is pulsed. This causes WRITE_INCREMENT to go high and Gray-code counter 74 to increment WRITE_COUNT, which indicates the number of data frames written to FIFO queue 50. [col. 7, lines 15-27]
Comparator 80 compares WRITE_COUNT_RESYNC with READ_COUNT and generates FRAME_IN_FIFO output 94, which indicates whether at least one unread data frame is stored in FIFO queue 50. [col. 8, lines 3-13]
outputting, by the FIFO, at least a portion of the data using a second clock signal [READ CLOCK] with a reduced delay after receiving the EOP indication based on the FRAME_IN_FIFO output, wherein the reduced delay is compared with the delay associated with waiting for the ordinary START threshold without using the EOP-responsive FRAME_IN_FIFO output.
The FRAME_IN_FIFO output can be used by the reading device to ensure that all data frames are read from FIFO queue 50 efficiently. During a transmit operation, if the frame written to FIFO queue 50 is not large enough to trigger the START threshold flag, the data interface controller can monitor FRAME_IN_FIFO and, when that output is asserted, begin transmitting the frame from FIFO queue 50 even though START is not asserted. [col. 8, lines 19-33]
Similarly, during a receive operation, the DMA controller can monitor FRAME_IN_FIFO to determine whether the end of a frame is stored in FIFO queue 50 and, if so, continue reading successive bytes or words in burst mode even when START is not asserted. [col. 8, lines 34-47]
Holm therefore teaches that EOP/EOF detection eliminates the additional delay that otherwise results from waiting for the normal START threshold. Once the EOF-responsive FRAME_IN_FIFO output is asserted, the reader may begin or continue outputting the packet immediately, even though the non-EOP-based START condition has not occurred. Holm, however, does not expressly call FRAME_IN_FIFO output 94 a read enable signal generated by the FIFO.
Koutsoures teaches an asynchronous FIFO having control circuitry that generates an asserted read-data-ready signal to authorize output of packet data in a receiving clock domain. Specifically, Koutsoures teaches packet data entering a FIFO using a producer-side first clock and leaving the FIFO using a consumer-side second clock, with the read-data-ready signal indicating that buffered data is available for output [see FIGS. 1 and 3].
It is common for packet based digital systems to send and receive data across clock domains. One known method for sending packets between digital systems having different clock domains is to use an asynchronous FIFO. [¶ 2-3]
The transmitting circuitry's clock and the receiving circuitry's clock are independent of each other and are not synchronized. Data clocked at a first frequency by a sending device is received and sampled at a second clock frequency by a receiving device. [¶ 17-18]
The asynchronous FIFO includes circuitry that determines the level of data in the buffer and provides a read-data-ready signal at an output of the FIFO when the specified safe data condition is satisfied. [¶ 5-7; claims 1 and 3 of Koutsoures]
Koutsoures expressly recites receiving data packets in association with a first clock signal, providing an asserted read-data-ready signal, and providing the data packets for reading in association with a second clock signal while the signal is asserted. [claim 14 of Koutsoures]
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to configure Holm's EOF-responsive FRAME_IN_FIFO output as, or to control, the read-data-ready/read-enable signal taught by Koutsoures. Holm expressly uses the asserted FRAME_IN_FIFO output to permit reading immediately after determining that the frame's EOF is stored, even when the ordinary START threshold is not asserted. Koutsoures teaches an explicit read-data-ready signal by which asynchronous FIFO circuitry authorizes output in the receiving clock domain. The modification would have predictably reduced the post-EOP delay relative to operation without the EOP-responsive signal, because the reading device would no longer wait for the normal threshold condition. The combination would thereby have improved packet-transfer latency while avoiding incomplete-packet output, underflow, and clock-domain synchronization error.
Regarding claim 16, Holm teaches that an EOF-responsive FRAME_IN_FIFO indication permits the reading device to begin transmitting a completed frame even when the ordinary START threshold has not been asserted.
Holm teaches The FRAME_IN_FIFO output can be used by the reading device to ensure that all data frames are read efficiently. If a frame is not large enough to trigger the START threshold, the data interface controller can monitor FRAME_IN_FIFO and, when that output is asserted, begin transmitting the frame from FIFO queue 50 even though START is not asserted. [col. 8, lines 19-33]
Koutsoures teaches an asynchronous FIFO whose decision circuitry generates a read-data-ready signal indicating that buffered data may be output using the receiving clock. The transmitting and receiving clocks are independent, and the signal is derived using comparison and synchronization circuitry. [¶ 5-7 and 17-18; claims 1, 3, and 14 of Koutsoures]
Holm and Koutsoures do not expressly recite “less than six” cycles of the second clock. After the synchronized frame-complete indication is received, however, the number of receiving-clock cycles before output is a result-effective timing parameter governed by the synchronization and output stages. A person of ordinary skill would have selected fewer than six cycles through routine timing design and verification to reduce packet latency while retaining reliable clock-domain synchronization. Thus, outputting at least a portion of the data fewer than six cycles after receiving EOP would have been obvious.
Regarding claim 17, Holm in view of Koutsoures teaches generating a read-enable or read-data-ready signal in response to the frame-complete/EOP condition and outputting the buffered data based on that signal. In Holm, the data interface controller monitors FRAME_IN_FIFO and begins transmitting the frame when that output is asserted. [Holm, col. 8, lines 19-33] Koutsoures likewise generates the read-data-ready signal to indicate that data is available to be output in the receiving clock domain. [Koutsoures, ¶ 17-18; claims 1 and 14 of Koutsoures] Therefore, the outputting is based on the read enable signal as claimed.
Claim(s) 4-9, 12-14, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holm/Koutsoures as applied to claim 1 or 10 or 15 above, and further in view of Liu US Pub. No. 2004/0257856.
Regarding claim 4, Holm in view of Koutsoures does not expressly teach output the data in response to the read enable signal while inputting additional data. Liu teaches this limitation through its configurable cut-through mode.
[0075] In general, packet management logic is provided to ensure the coherence of packets that are read from FIFO memory 40. In this regard, it is important for control logic 47 to comprehend the number of packets that are stored within FIFO memory 40, and to comprehend the start and end of these stored packets. In addition, FIFO memory 40 according to this embodiment of the invention has the capability of handling "cut through" packets, which are packets of a size greater than a configurable threshold. For packets of a size greater than this threshold, the reading out of the beginning of the packet from FIFO memory 40 is permitted prior to the writing in of the end of the packet. As such, the "cut through" packet will not have both a start and end within FIFO memory 40 at any given time.
[0081] This operation of FIFO memory 40 continues in this manner, with control logic 47 managing the possibility of zero, one, or more than one packet being stored. To handle "cut-through" packets, control logic 47 enters cut thru state 78 from first_sop state 72, in response to state variable pass_cut_thru_Th indicating, in the true condition, that the size of the packet for which an SOP has been written (state 72) is greater than a preselected threshold size. In connection with this transition, state variable sending_pkt is set to indicate that this packet is readable from FIFO memory 40. Both of the state variables writing_pkt and sending_pkt are set in this condition, indicating that the same large packet is both being written and being read simultaneously. In cut_thru state 78, receipt of the end of the jumbo packet (write_eop) by FIFO memory 40 causes control logic 47 to make a transition to tx_last_pkt state 76, incrementing state variable #pkt and clearing the writing_pkt state variable. The last remaining packet in FIFO memory 40 at this point is the remainder of the jumbo packet.
Before the effective filing date, it would have been obvious to incorporate Liu's known cut-through mode into the asynchronous FIFO of Holm and Koutsoures so that sufficiently long packets could be read while their remaining data was still being written. Liu concern packet FIFOs and avoiding stalls or underflow; the modification would have predictably reduced latency and increased throughput while retaining a sufficient buffered-data margin.
Regarding claim 5, Holm teaches that FIFO queue 50 includes a dual-port RAM having successive storage locations for storing the bytes or words of each frame. Holm's FIFO control maintains write and read pointers identifying the current storage addresses. [col. 6, lines 3-14 and 30-57]
Liu additionally teaches FIFO memory 40 having memory array 45 and write buffer 42 with multiple buffer entries/storage locations. Liu's claims expressly recite a plurality of buffer storage locations arranged in rows and columns. [59-64; claims 1-4 of Liu]
Accordingly, Holm/Koutsoures/Liu teaches the memory comprises a plurality of memory entries configured to store the data.
Regarding claim 6, Holm teaches that DMA controller 20 passes successive words or bytes of a frame to successive storage locations in FIFO queue 50 and that the FIFO may store each data byte and its corresponding EOF flag at a selected address. [col. 5, lines 47-54; col. 6, lines 30-46]
Liu similarly teaches that each write-buffer entry stores a data word and that pairs of stored data words are transferred to the double-word-width memory array. [¶ 55-64; claims 2-4 of Liu] A data word comprises a fixed number of data bytes in the disclosed packet-memory architecture. Thus, Holm/Koutsoures/Liu teaches each of the plurality of memory entries is configured to store a number of data bytes.
Regarding claim 7, Holm teaches a START threshold corresponding to a set amount of data stored in the FIFO before reading begins. [col. 2, lines 3-26] Liu more specifically teaches control logic that determines whether the stored portion of a packet exceeds a configurable cut-through threshold and, when the threshold is reached, generates the ready/read control that permits the beginning of the packet to be read before EOP. [¶ 70 and 75-81]
Liu teaches FIFO memory 40 is ready to be read when an EOP has been stored for a packet or when a sufficient amount of data for a packet has been stored. Output FIFO 48 then asserts RD_RDY to the downstream destination. [Liu, ¶ 70]
Because the threshold triggers reading while additional entries remain available and while the remainder of the packet is still being written, the threshold necessarily represents fewer entries than the total plurality of entries of FIFO memory 40. It would have been obvious to use Liu's threshold-triggered RD_RDY operation as the threshold branch of the read-enable logic in Holm and Koutsoures to begin output at the earliest safe occupancy level, predictably reducing latency without causing underflow.
Regarding claim 8, Liu teaches that the threshold is associated with the size of the currently stored portion of a packet. Specifically, pass_cut_thru_Th becomes true when the size of the packet portion for which SOP has been written exceeds the threshold; the beginning of the packet is then readable before the packet's EOP is written. [¶ 75-81] Thus, Liu teaches the threshold number of memory entries is associated with a portion of the data packet.
Regarding claim 9, Holm describes the conventional START threshold as a “set amount” of stored data selected to accommodate worst-case transfer delays. [col. 2, lines 3-26] Liu expressly describes the cut-through threshold as “configurable” and “preselected.” [¶ 75 and 81] A preselected threshold is determined before it is applied to the stored-entry count. Accordingly, the combined FIFO uses a predetermined threshold number of memory entries.
It would have been obvious to select the threshold before FIFO operation based on expected packet size, write/read rates, and underflow tolerance. Holm identifies these considerations as reasons for choosing the amount of buffered data required before reading, while Liu teaches implementing that choice as the configurable cut-through threshold. The modification would have provided predictable threshold comparison and repeatable packet-transfer behavior.
Regarding claim 12, See discussion in claim 4.
Regarding claim 13, Holm teaches a START threshold corresponding to a set amount of data stored in the FIFO before reading begins and a FIFO RAM having a plurality of successive storage locations. [col. 2, lines 3-26; col. 6, lines 3-14 and 30-57] Liu more specifically teaches control logic that determines whether the stored portion of a packet exceeds a configurable cut-through threshold and generates a ready/read control permitting output before EOP. [Liu ¶ 70 and 75-81]
FIFO memory 40 is ready to be read when an EOP has been stored for a packet or when a sufficient amount of data for the packet has been stored. Output FIFO 48 then asserts RD_RDY to the downstream destination. [ ¶ 70]
Because Liu's threshold causes reading to begin while the remainder of the packet is still being written and additional storage locations remain available, the threshold number of occupied entries is less than the plurality of entries of FIFO memory 40. It would have been obvious to use Liu's threshold-triggered RD_RDY operation as an additional branch of the read-enable logic in Holm and Koutsoures to begin output at the earliest safe occupancy level, predictably reducing latency without causing FIFO underflow. Thus, the combination would have resulted in the lookahead circuitry is configured to generate the read enable signal based on the data being stored on a threshold number of memory entries less than a plurality of memory entries of the memory.
Regarding claim 14, Holm/Koutsoures does not expressly teach the threshold number of memory entries is based on a difference between frequencies of the first clock signal and the second clock signal. Holm expressly teaches that the write and read sides of the FIFO operate in different clock domains at respective transfer rates. In transmit FIFO 16, DMA controller 20 operates write port 54 in the WRITE_CLOCK domain at the DMA transfer rate, whereas data interface controller 14 operates read port 56 in the READ_CLOCK domain at the fixed-speed interface rate. [col. 8, lines 19-33]
Holm further teaches that the time before beginning transmission may be based on a predetermined relationship between the data-routing-circuit transmission rate and the fixed-speed data-interface rate, and that the amount of stored data required before reading is selected to avoid underflow in view of the applicable transfer delays. [col. 2, lines 4-32]
Liu teaches implementing the safe buffered-data amount as a configurable, preselected cut-through threshold. When that threshold is reached, control logic identifies the packet as readable even though the packet is still being written. [¶ 75 and 81]
It would have been obvious to set Liu's stored-entry threshold according to Holm's relationship between the write-side and read-side rates, which correspond to the first and second clock frequencies. A faster read clock requires more buffered entries to prevent underflow; a smaller frequency difference permits fewer entries. This would predictably optimize latency while preventing underflow. Thus, Holm/Koutsoures combined with Liu would resulted in the threshold number of memory entries is based on a difference between frequencies of the first clock signal and the second clock signal.
Regarding claim 18, see discussion in claim 4.
Regarding claim 19, see discussion in claim 5 and 6.
Regarding claim 20, see discussion in claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent No. 11,010,293 to Kovishaner teaches asynchronous FIFOs are logically divided into two sides, with the operations of each side being governed by a different clock with a different clock pulse rate. One side, at which data is written into the FIFO, is designated as the write side while the other side, at which data is read out of the FIFO, is designated as the read side. The data storage buffer is accessible by both sides, allowing for transport of data from the write side to the read side. A write-to-read control channel conveys information about the data (e.g., the number of words that have been loaded into the data storage buffer) from the write side to the read side. A binary write pointer is converted, at the write side, into a corresponding Gray code symbol and is conveyed to the read side via a write-to-read clock synchronization channel. The gray code is then converted back to the corresponding binary value at the read side. The read side includes a used-words register that indicates the number of used words (i.e., filled locations within the data storage buffer) available to be read. This used-words register is updated based on the write pointer received at the read side.
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VINCENT H TRAN
Primary Examiner
Art Unit 2115
/VINCENT H TRAN/Primary Examiner, Art Unit 2115
1 IDS filed on 10/10/2024.
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