DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 11496147. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claims in the pending application are transparently found in US 11496147 with obvious wording variations. See below for mapping:
Claim 21: A device comprising:
a plurality of cells forming an array and configured to be selectively activated based on a digital signal; and
a data path comprising a plurality of branch points disposed within the array, wherein the data path is configured to provide the digital signal to the plurality of cells via respective branches of the data path, wherein the respective branches terminate at respective cells of the plurality of cells.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1 and 12 o U.S. Patent No. 11,496,147. The patent claims recite a unit-cell array containing a recursively branching data path that directs decision-unit outputs along different branches to respective unit cells. Claim 21 merely omits the fractal-pattern and decision-unit limitations.
Claim 22: The device of claim 21, wherein a first branch point of the plurality of branch points is disposed along a centerline of the array that evenly divides the array into a first half and a second half.
Claim 22 is rejected on die ground of nonstatutory double patenting as being unpatentable over at least claims 3, 4, and 12 of U.S. Patent No. 11,496,147. Patent claims 3 and 4 require a bifurcating data path arranged symmetrically about a central axis. Locating the first bifurcation on the centerline dividing the symmetric array into two halves is an obvious geometric implementation of that arrangement.
Claim 23: The device of claim 22, wherein the first branch point splits the data path into a first branch and a second branch, wherein the first branch is configured to feed the first half of the array and the second branch is configured to feed the second half of the array.
Claim 23 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 3, 4, 12, and 14 of U.S. Patent No. 11,496,147. The patent claims require a symmetric branching data path in which a decision unit directs respective outputs along different branches. Directing the two branches from the central bifurcation to the respective halves is an obvious implementation of the patented arrangement.
Claim 24: The device of claim 23, wherein a second branch point splits the first branch into a first sub-branch of the of the first branch and a second sub-branch of the first branch, wherein the first sub-branch is configured to feed a first quarter of the array and the second sub-branch is configured to feed a second quarter of the array.
Claim 24 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3, 4, 12, and 14 of U.S. Patent No. 11,496,147. Patent claim 14 expressly requires successive branching layers in which each branch is split by a respective decision-unit circuit. Dividing one half of the symmetric array into first and second quarters is the ordinary result of the next bifurcation level.
Claim 25: The device of claim 21, wherein each branch point of the plurality of branch points splits the data path symmetrically relative to a physical layout of the array.
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3 and 4 of U.S. Patent No. 11,496,147. Patent claim 3 requires bifurcation at each decision-unit circuit, and patent claim 4 expressly requires the fractal pattern, branching data path, and decision-unit circuits to be symmetric about a central axis.
Claim 26: The device of claim 21, wherein providing the digital signal to the plurality of cells comprises providing respective decoded portions of the digital signal to the respective cells via the respective branches, wherein cells of the plurality of cells are configured to selectively activate based on the respective decoded portions of the digital signal.
Claim 26 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 5, and 12 of U.S. Patent No. 11,496,147. The patent claims require decision-unit circuits to decode portions of an incoming digital signal and direct the resulting outputs along separate branches to enable respective unit cells.
Claim 27: The device of claim 26, wherein the respective decoded portions of the digital signal, in an aggregate, form a thermometer coded digital signal.
Claim 27 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 19 and 20 of U.S. Patent No. 11,496,147. Patent claim 20 expressly requires conversion of the digital signal from binary format to thermometric format such that each unit cell receives a respective bit.
Claim 28: The device of claim 26, wherein a branch point of the plurality of branch points comprises a decision unit configured to decode, at least in part, a received portion of the digital signal and output a first decision unit output down a first outgoing branch of the branch point and a second decision unit output down a second outgoing branch of the branch point, wherein the first decision unit output and second decision unit output each comprise- respective bit depths less than a bit depth of received portion of the digital signal.
Claim 28 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 5, 6, and 21 of U.S. Patent No. 11,496,147. The patent claims require a decision-unit circuit to decode an incoming multi-bit signal and provide respective most-significant-bit and least-significant-bit portions along separate outgoing branches, with each output containing fewer bits than the incoming signal.
Claim 29: The device of claim 21, wherein the device comprises a digital-to-analog converter (DAC), and wherein activated cells of the plurality of cells are configured to output respective outputs that, in an aggregate, form an analog signal corresponding to the digital signal.
Claim 29 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 12 of U.S. Patent No. 11,496,147. Patent claim 12 expressly recites a DAC in which enabled unit cells provide respective outputs that, in the aggregate, form an analog signal corresponding to the digital signal.
Claim 30: The de vice of claim 21, wherein each respective branch of the respective branches to the plurality of cells comprises a same data path length.
Claim 30 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 9 and 13 of U.S. Patent No. 11,496,147. These claims require the individual data paths to the respective unit cells to be substantially equal in length. Requiring the paths to be the same rather than substantially equal does not establish a patentable distinction.
Claim 31: A physical data path configured to provide respective portions of an input digital signal to a plurality of cells forming an array, wherein the physical data path comprises:
a first branch point disposed centrally within the array, wherein the first branch point is configured to split an input branch of the input digital signal into a first branch of the physical data path and a second branch of the physical data path, wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the input digital signal to a first half of the array and the second branch is configured to direct a second intermediate signal indicative of a second portion of the input digital signal to a second half of the array; and
a second branch point disposed along the first branch of the physical data path and configured to split the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch.
Claim 31 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 3, 4, 12, 14, and 21 of U.S. Patent No. 11,496,147. Claim 31 merely recasts the patented recursively branching data path as a claimed article and identifies the first two levels of its symmetric bifurcating structure.
Claim 32: The physical data path of claim 31, comprising a third branch point disposed along the second branch of the physical data path and configured to split the second branch into a first sub-branch of the second branch and a second sub-branch of the second branch.
Claim 32 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3, 4, 12, and 14 of U.S. Patent No. 11,496,147. The cited claims require repeated branch splitting at successive layers in a symmetric fractal pattern. Providing a corresponding split on the second branch is an obvious implementation of that patented structure.
Claim 33: The physical data path of claim 32, wherein the second branch point and the third branch point disposed centrally within the first half of the array and the second half of the array, respectively, such that splitting of the first branch and splitting of the second branch are symmetrical with respect to an axis of the array.
Claim 33 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3, 4, 12, and 14 of U.S. Patent No. 11,496,147. Centrally locating corresponding branch points in the respective halves is an obvious geometric implementation of the patented symmetric, recursively branching fractal arrangement.
Claim 34: The physical data path of claim 31, wherein the first branch point comprises a decision unit configured to decode, at least in part, the input digital signal, wherein the decision unit comprises:
an input configured to receive the digital signal, wherein the digital signal is indicative of respective activation signals for the plurality of cells;
a first output configured to output the first intermediate signal, wherein the first intermediate signal is indicative of the respective activation signals for a first portion of the plurality of cells disposed in the first half of the array;
a second output configured to output the second intermediate signal, wherein the second intermediate signal is indicative of the respective activation signals for a second portion of the plurality of cells disposed in the second half of the array; and circuitry configured to generate the first intermediate signal and the second intermediate signal based on the digital signal.
Claim 34 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 3-6, 12, 14, and 21 of U.S. Patent No. 11,496,147. The patent claims require decision-unit circuitry that receives an incoming digital signal, decodes the signal, and provides first and second outputs indicative of activation information for separate portions of the unit-cell array along respective branches.
Claim 35: The physical data path of claim 34, wherein the input digital signal comprises a first bit depth, the first intermediate signal comprises a second bit depth less than the first bit depth, and the second intermediate signal comprises a third bit depth less than the first bit depth.
Claim 35 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 5, 6, and 21 of U.S. Patent No. 11,496,147. Dividing the incoming signal into a most-significant-bit output and an output containing the remaining least-significant bits produces respective outputs having fewer bits than the original incoming signal.
Claim 36: The physical data path of claim 34, wherein the circuitry is configured to generate the first intermediate signal and the second intermediate signal based on a partial decoding of the input digital signal, wherein the physical data path comprises a plurality of decision units configured to, in an aggregate, decode the input digital signal into the respective activation signals.
Claim 36 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 1, 5, 12, and 19-21 of U.S. Patent No. 11,496,147. The cited claims require individual decision units to decode respective portions of the incoming signal and require the plurality of decision units, in the aggregate, to convert the digital signal into respective signals supplied to the unit cells.
Claim 37: A method comprising:
receiving, at a first branch point of a data path, a digital signal indicative of activation signals for a plurality of cells disposed in an array;
splitting, via the first branch point, the data path into a first branch of the data path and a second branch of the data path, wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the digital signal to a first half of the array and the second branch is configured to direct a second intermediate signal indicative of a second portion of the digital signal to a second half of the array; and
splitting, via a second branch point disposed along the fmt branch of the data path, the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch.
Claim 37 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3, 4, 14, 19, and 21 of U.S. Patent No. 11,496,147. Patent claims 19 and 21 recite receiving and distributing a digital signal through a branching data path and splitting the data path into from and second branches. Claims 3, 4, and 14 require the splitting to repeat symmetrically through successive layers.
Claim 38: The method of claim 37, wherein the first branch point is disposed at a center of the array.
Claim 38 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 4 and 19 of U.S. Patent No. 11,496,147. Locating the initial branch point at the center is an obvious geometric implementation of the fractal arrangement that is symmetric about the central axis.
Claim 39: The method of claim 37, wherein the data path comprises one or more multi-bit data buses.
Claim 39 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 10, 19, and 21 of U.S. Patent No. 11,496,147. Patent claim 10 expressly requires the branching data path to include a plurality of data buses, and patent claim 21 requires the branches to cany respective portions of a multi-bit incoming digital signal.
Claim 40: The method of claim 37, wherein a physical layout of the data path is symmetrical about an axis of the array.
Claim 40 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 4 and 19 of U.S. Patent No. 11,496,147. Patent claim 4 expressly requires the branching data path and associated unit-cell arrangement to be symmetric about a central axis.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12119838. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claims in the pending application are transparently found in US 12119838 with obvious wording variations. See below for mapping:
Claim 21: A device comprising:
a plurality of cells forming an array and configured to be selectively activated based on a digital signal; and a data path comprising a plurality of branch points disposed within the array, wherein the data path is configured to provide the digital signal to the plurality of cells via respective branches of the data path, wherein the respective branches terminate at respective cells of the plurality of cells.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 1 of U.S. Patent No. 12,119,838. Patent claim 1 recites a unit-cell array having selectively activated unit cells and a branching data path having branch points that provide a digital signal to respective unit cells through respective terminating branches. Claim 21 merely omits the requirement that each unit cell output a unitary amount of power.
Claim 22: The device of claim 21, wherein a first branch point of the plurality of branch points is disposed along a centerline of the array that evenly divides the array into a first half and a second half.
Claim 22 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 10 of U.S. Patent No. 12,119,838. Patent claim 10 places the first chronological branch point centrally within die unit-cell array. Describing that central location as lying on a centerline that evenly divides the array into first and second halves does not patentably distinguish the claim.
Claim 23: The device of claim 22, wherein the first branch point splits the data path into a first branch and a second branch, wherein the first branch is configured to feed the first half of the array and the second branch is configured to feed the second half of the array.
Claim 23 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 6, 10, 11, and 16 of U.S. Patent No. 12,119,838. The patent claims provide a centrally positioned branch point or decision unit having first and second outputs directed along respective branches to separate first and second portions of the unit-cell array. Directing those branches to the respective halves of the array is an obvious implementation of the claimed central branching arrangement.
Claim 24: The device of claim 23, wherein a second branch point splits the first branch into a first sub-branch of the of the first branch and a second sub-branch of the first branch, wherein the first sub-branch is configured to feed a first quarter of the array and the second sub-branch is configured to feed a second quarter of the array.
Claim 24 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 6, 8, 10, and 16 of U.S. Patent No. 12,119,838. Patent claim 8 requires repeated bifurcation at the branch points in a fractal pattern. After the centrally located first branch point divides the array into halves, bifurcating the first branch at a second branch point to feed respective quarters is the-ordinary result of the next branching level.
Claim 25: The device of claim 21, wherein each branch point of the plurality of branch points splits the data path symmetrically relative to a physical layout of the array.
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 8 and 20 of U.S. Patent No. 12,119,838. Patent claim 8 requires bifurcation at each branch point in a fractal pattern, and patent claim 20 requires the physical data path to be symmetrical about an axis of the DAC.
Claim 26: The device of claim 21, wherein providing the digital signal to the plurality of cells comprises providing respective decoded portions of the digital signal to the respective cells via the respective branches, wherein cells of the plurality of cells are configured to selectively activate based on the respective decoded portions of the digital signal.
Claim 26 is rejected on die ground of nonstatutory double patenting as being unpatentable over at least claim 3 of U.S. Patent No. 12,119,838. Patent claim 3 provides decoded portions of the digital signal to respective unit cells through respective branches and selectively activates the unit cells based on those decoded portions.
Claim 27: The device of claim 26, wherein the respective decoded portions of the digital signal, in an aggregate, form a thermometer coded digital signal.
Claim 27 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 4 of U.S. Patent No. 12,119,838. Patent claim 4 expressly requires the decoded portions of the digital signal in the aggregate, to form a thermometer-coded digital signal.
Claim 28: The device of claim 26, wherein a branch point of the plurality of branch points comprises a decision unit configured to decode, at least in part, a received portion of the digital signal and output a first decision unit output down a first outgoing branch of the branch point and a second decision unit output down a second outgoing branch of the branch point, wherein the first decision unit output and the second decision unit output each comprise respective bit depths less than a bit depth of the received portion of the digital signal.
Claim 28 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 3, 6, 7, 11, 13, and 16 of U.S. Patent No. 12,119,838. The patent claims recite a decision unit that partially decodes a received portion of a digital signal and provides first and second reduced-bit-depth outputs along respective outgoing branches.
Claim 29: The device of claim 21, wherein the device comprises a digital-to-analog converter (DAC), and wherein activated cells of the plurality of cells are configured to output respective outputs that, in an aggregate, form an analog signal corresponding to the digital signal.
Claim 29 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 5 of U.S. Patent No. 12,119,838. Patent claim 5 expressly requires activated unit cells of a DAC to provide respective outputs that, in the aggregate, form an analog signal corresponding to the digital signal.
Claim 30: The device of claim 21, wherein each respective branch of the respective branches to the plurality of cells comprises a same data path length.
Claim 30 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 9 of U.S. Patent No. 12,119,838. Patent claim 9 expressly requires the data-path lengths to each unit cell to be the same.
Claim 31: A physical data path configured to provide respective portions of an input digital signal to a plurality of cells forming an array, wherein the physical data path comprises:
a first branch point disposed centrally within the array, wherein the first branch point is configured to split an input branch of the input digital signal into a first branch of the physical data path and a second branch of the physical data path, wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the input digital signal to a first half of the array and the second branch is configured to direct a second intermediate signal indicative of a second portion of the input digital signal to a second half of the array; and
a second branch point disposed along the first branch of the physical data path and configured to split the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch.
Claim 31 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 6, 8, 10, 11, and 16 of U.S. Patent No. 12,119,838. Claim 31 merely recasts the branching data path of the patented DAC as the claimed article and expressly recites the first two levels of its centrally positioned, repeatedly bifurcating branching structure.
Claim 32: The physical data path of claim 31, comprising a third branch point disposed along the second branch of the physical data path and configured to split the second branch into a first sub-branch of the second branch and a second sub-branch of the second branch.
Claim 32 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 8 and 20 of U.S. Patent No. 12,119,838. Patent claim 8 requires repeated bifurcation at the branch points, and patent claim 20 requires a symmetric data path. Providing a corresponding bifurcation along the second branch is an obvious implementation of the patented symmetric fractal branching arrangement.
Claim 33: The physical data path of claim 32, wherein the second branch point and the third branch point disposed centrally within the first half of the array and the second half of the array, respectively, such that splitting of the first branch and splitting of the second branch are symmetrical with respect to an axis of the array.
Claim 33 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 8, 10, and 20 of U.S. Patent No. 12,119,838. Repeating the centrally positioned branch structure in the respective halves of the array is an obvious geometric implementation of the centrally disposed, bifurcating, and symmetrical data path claimed in the patent.
Claim 34: The physical data path of claim 31, wherein the first branch point comprises a decision unit configured to decode, at least in part, the input digital signal, wherein the decision unit comprises:
an input configured to receive the digital signal, wherein the digital signal is indicative of respective activation signals for the-plurality of cells;
a first output configured to output the first intermediate signal, wherein the first intermediate signal is indicative of the respective activation signals for a first portion of the plurality of cells disposed in the first half of the array;
a second output configured to output the second intermediate signal, wherein the second intermediate signal is indicative of the respective activation signals for a second portion of the plurality of cells disposed in the second half of the array; and
circuitry configured to generate the first intermediate signal and the second intermediate signal based on the digital signal.
Claim 34 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 8, 10, 11, 13, and 16 of U.S. Patent No. 12,119,838. Patent claim 11 expressly recites a decision unit having an input, first and second outputs corresponding to separate portions of the unit-cell array, and circuitry generating die outputs based on the digital signal. Patent claim 13 requires at least partial decoding, while claims Band 10 establish the inherited central branching arrangement.
Claim 35: The physical data path of claim 34, wherein the input digital signal comprises a first bit depth, the first intermediate signal comprises a second bit depth less than the first bit depth, and the second intermediate signal comprises a third bit depth less than the first bit depth.
Claim 35 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 7, 11, and 16 of U.S. Patent No. 12,119,838. These claims expressly require first and second decision-unit outputs having respective bit depths less than the bit depth of the received digital signal.
Claim 36: The physical data path of claim 34, wherein the circuitry is configured to generate the first intermediate signal and the second intermediate signal based on a partial decoding of the input digital signal, wherein the physical data path comprises a plurality of decision units configured to, in an aggregate, decode the input digital signal into the respective activation signals.
Claim 36 is rejected on die ground of nonstatutory double patenting as being unpatentable over at least claims 11, 13, 15, and 16 of U.S. Patent No. 12,119,838. Patent claim 13 requires partial decoding by an individual decision unit, and claims 15 and 16 require a plurality of decision units positioned along the data path to collectively decode the digital signal into decoded portions used to activate the unit cells.
Claim 37: A method comprising:
receiving, at a first branch point of a data path, a digital signal indicative of activation signals for a plurality of cells disposed in an array;
splitting, via the first branch point, the data path into a first branch of the data path and a second branch of the data path, wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the digital signal to a first half of the array and the second branch is configured to direct a second intermediate signal indicative of a second portion of the digital signal to a second half of the array; and
splitting, via a second branch point disposed along the first branch of the data path, the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch.
Claim 37 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 6, 8, 10, 11, and 16 of U.S. Patent No. 12,119,838. Claim 37 merely recites the method necessarily or obviously performed when operating the patented centrally positioned, repeatedly bifurcating decision-unit and data-path structure.
Claim 38: The method of claim 37, wherein the first branch point is disposed at a center of the array.
Claim 38 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 10 of U.S. Patent No. 12,119,838. Patent claim 10 expressly requires the first chronological branch point to be centrally disposed within the unit-cell array.
Claim 39: The method of claim 37, wherein the data path comprises one or more multi-bit data buses.
Claim 39 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claims 7, 11, and 16 of U.S. Patent No. 12,119,838. The patent claims require a data path that carries an input signal having a first bit depth and first and second output signals having respective reduced bit depths. Conveying those multi-bit signals over one or more multi-bit data buses is a routine and obvious implementation of the patented data path.
Claim 40: The method of claim 37, wherein a physical layout of the data path is symmetrical about an axis of the array.
Claim 40 is rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 20 of U.S. Patent No. 12,119,838. Patent claim 20 expressly requires the data path to be symmetrical about an axis of the DAC.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-27, 29, 31-33, 37-40 are rejected under 35 U.S.C. 103 as being unpatentable over Galton (US 5684482, hereinafter “Galton”), and further in view of Bogaerts (US 20230251356, hereinafter “Bogaerts”).
Regarding claim 21, Galton discloses,
A device (a block diagram of one example of the DAC topology; Fig. 2) comprising:
a plurality of cells forming an array (the topology 100 includes eight one-bit DACs 130-137; Fig. 2) and configured to be selectively activated based on a digital signal (the eight one-bit output signals on the lines 152-159 are provided as inputs to the eight one-bit DACs 130-137. The output 152 of the switching block 123 is provided as the input to the DAC 130, and the output 153 of the switching block 123 is provided as the input to the one-bit DAC 131……The eight one-bit DACs 130-137 convert the input signals x.sub.1 [n] . . . x.sub.8 [n] into eight analog signals y.sub.1 [n] . . . y.sub.8 [n] on outputs 160-167, Col. 5; lines 45-Col. 6; lines 26); and
a data path comprising a plurality of branch points (Fig. 2 illustrates multiple layers of switching blocks 120-126. Switching blocks 120 divides the digital input into two signals, switching blocks 121and 122 divided those signal into four signal, and switching blocks 123-126 divide the four signals into eight final one-bit signals, also see Col. 5; lines 45-Col. 6; lines 26 ), wherein the data path is configured to provide the digital signal to the plurality of cells via respective branches of the data path (the eight one-bit output signals on the lines 152-159 are provided as inputs to the eight one-bit DACs 130-137, Col. 6; lines 3-24), wherein the respective branches terminate at respective cells of the plurality of cells (Fig. 2 illustrates outputs 152-159 of the final switching-block layer are respectively connected to one-bit DAC elements 130-137). However, Galton does not explicitly disclose, the branch points disposed within the array.
In the same field of endeavor, Bogaerts discloses, the branch points disposed within the array (The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]……. , the wiring extends from the output of the clock buffer 22 to the first branch point 51, is branched thereat, then one piece of the clock wiring 50 further extends from the one end of the pixel area 30 in the Y direction to a second branch point 57 positioned at a quarter distance, and is further bifurcated thereat, and one of the bifurcated pieces extends toward the one end of the unit pixel group array 35 of the Y direction and the other extends toward the first branch point 51 [0102]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed inventio to modify Galton by specifically providing the branch points disposed within the array, as taught by Bogaerts for the purpose of significantly improving the measurement accuracy by correction only in the Y direction when a correction in a system level is performed [0025].
Regarding claim 22, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 21), in addition Bogaerts discloses, wherein a first branch point of the plurality of branch points is disposed along a centerline of the array that evenly divides the array into a first half and a second half (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]).
Regarding claim 23, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 22), in addition Bogaerts discloses, wherein the first branch point splits the data path into a first branch and a second branch, wherein the first branch is configured to feed the first half of the array and the second branch is configured to feed the second half of the array (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]).
Regarding claim 24, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 23), in addition Bogaerts discloses, wherein a second branch point splits the first branch into a first sub-branch of the of the first branch and a second sub-branch of the first branch, wherein the first sub-branch is configured to feed a first quarter of the array and the second sub-branch is configured to feed a second quarter of the array (one piece of the clock wiring 50 further extends from the one end of the pixel area 30 in the Y direction to a second branch point 57 positioned at a quarter distance, and is further bifurcated thereat, … The other piece of clock wiring 50 branched at the first branch point 51 further extends from the one end of the pixel area 30 in the Y direction to a third branch point 58 positioned at a three-quarter distance, and is further bifurcated thereat, [0102] and Fig. 9).
Regarding claim 25, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 21), in addition Bogaerts discloses, wherein each branch point of the plurality of branch points splits the data path symmetrically relative to a physical layout of the array (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]; [0102]).
Regarding claim 26, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 21), further Galton discloses, wherein providing the digital signal to the plurality of cells comprises providing respective decoded portions of the digital signal (Because switching blocks 123-126 comprise the final layer of switching blocks, the eight one-bit output signals on the lines 152-159 are provided as inputs to the eight one-bit DACs 130-137. The output 152 of the switching block 123 is provided as the input to the DAC 130, and the output 153 of the switching block 123 is provided as the input to the one-bit DAC 131, Col. 6; lines 3-19 ) to the respective cells via the respective branches (The eight one-bit DACs 130-137 convert the input signals x.sub.1 [n] . . . x.sub.8 [n] into eight analog signals y.sub.1 [n] . . . y.sub.8 [n] on outputs 160-167, Col. 6; lines 19-29), wherein cells of the plurality of cells are configured to selectively activate based on the respective decoded portions of the digital signal (The coarse DACs required for .DELTA..SIGMA. data converters are typically implemented using switched-capacitor unit DAC-elements which each dump an ideally fixed amount of charge into the summing node of an op-amp based integrator (the adder 19) during each sample interval in which the input bit is high, Col 5; lines 3-22).
Regarding claim 27, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 26), further Galton discloses, wherein the respective decoded portions of the digital signal, in an aggregate, form a thermometer coded digital signal (The sequence is fed to an input 9 of the digital encoder 5. The digital encoder 5 maps each input sample to N output bits x.sub.1 [n], x.sub.2 [n], . . . x.sub.N [n], Col. 4; lines 43-65 and Col. 6; lines 19-44).
Regarding claim 29, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 26), further Galton discloses, wherein the device comprises a digital-to-analog converter (DAC), and wherein activated cells of the plurality of cells are configured to output respective outputs that, in an aggregate, form an analog signal corresponding to the digital signal (Each output signal y.sub.r [n] is then provided as an input to an adder 19 which sums the outputs to create an analog signal y[n] on an output 20, Col. 4; lines 42-67).
Regarding claim 31, Galton discloses,
A physical data path configured to provide respective portions of an input digital signal to a plurality of cells forming an array (Fig. 2 illustrates switching-block tree receives a multi-bit input signal and progressively generates respective lower-bit-depth portions that are ultimately supplied to respective unit DAC elements), wherein the physical data path comprises:
a first branch point, wherein the first branch point is configured to split an input branch of the input digital signal into a first branch of the physical data path and a second branch of the physical data path ((Fig. 2 illustrates multiple layers of switching blocks 120-126. Switching blocks 120 divides the digital input into two signals, switching blocks 121and 122 divided those signal into four signal, and switching blocks 123-126 divide the four signals into eight final one-bit signals, also see Col. 5; lines 45-Col. 6; lines 26 )), wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the input digital signal to a first half of the array (Fig. 2 shows first three-bit output is supplied to switching block 121 and ultimately controls one group of four DAC elements, DACs 130-133) and the second branch is configured to direct a second intermediate signal indicative of a second portion of the input digital signal to a second half of the array (Fig. 2 shows first three-bit output is supplied to switching block 121 and ultimately controls the remaining group of four DAC elements, DACs 134-137); and
a second branch point disposed along the first branch of the physical data path and configured to split the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch (Fig. 2 illustrates the switching blocks 121 and 122 split their respective three-bit input signals into four two-bit output signals 144-147. Fig. 2 also shows the two outputs attributable to switching block 121 and output 144 and 145, which proceed to switching blocks 123 and 124, respectively).
However, Galton does not explicitly disclose, the branch points disposed centrally within the array.
In the same field of endeavor, Bogaerts discloses, the branch points disposed centrally within the array (The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]……. , the wiring extends from the output of the clock buffer 22 to the first branch point 51, is branched thereat, then one piece of the clock wiring 50 further extends from the one end of the pixel area 30 in the Y direction to a second branch point 57 positioned at a quarter distance, and is further bifurcated thereat, and one of the bifurcated pieces extends toward the one end of the unit pixel group array 35 of the Y direction and the other extends toward the first branch point 51 [0102]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed inventio to modify Galton by specifically providing the branch points disposed centrally within the array, as taught by Bogaerts for the purpose of significantly improving the measurement accuracy by correction only in the Y direction when a correction in a system level is performed [0025].
Regarding claim 32, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 31), in addition Bogaerts discloses, a third branch point disposed along the second branch of the physical data path and configured to split the second branch into a first sub-branch of the second branch and a second sub-branch of the second branch (one piece of the clock wiring 50 further extends from the one end of the pixel area 30 in the Y direction to a second branch point 57 positioned at a quarter distance, and is further bifurcated thereat, … The other piece of clock wiring 50 branched at the first branch point 51 further extends from the one end of the pixel area 30 in the Y direction to a third branch point 58 positioned at a three-quarter distance, and is further bifurcated thereat, [0102] and Fig. 9).
Regarding claim 33, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 32), in addition Bogaerts discloses, wherein the second branch point and the third branch point disposed centrally within the first half of the array and the second half of the array, respectively, such that splitting of the first branch and splitting of the second branch are symmetrical with respect to an axis of the array (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]; [0102]).
Regarding claim 37, Galton discloses,
A method comprises:
receiving, at a first branch point of a data path, a digital signal indicative of activation signals for a plurality of cells (A digital signal x[n] is input into the switching block 120 via a four-bit bus 113. As indicated in the figure, x[n] can be up to a four-bit signal, however its value is limited to the range 0 . . . 8. The switching block 120 splits the input signal into two 3-bit output signals on outputs 140 and 141, Fig. 2 and Col. 5; lines 46-50);
splitting, via the first branch point, the data path into a first branch of the data path and a second branch of the data path (Fig. 2 illustrates multiple layers of switching blocks 120-126. Switching blocks 120 divides the digital input into two signals, switching blocks 121and 122 divided those signal into four signal, and switching blocks 123-126 divide the four signals into eight final one-bit signals, also see Col. 5; lines 45-Col. 6; lines 26 )), wherein the first branch is configured to direct a first intermediate signal indicative of a first portion of the input digital signal to a first half of the array (Fig. 2 shows first three-bit output is supplied to switching block 121 and ultimately controls one group of four DAC elements, DACs 130-133) and the second branch is configured to direct a second intermediate signal indicative of a second portion of the input digital signal to a second half of the array (Fig. 2 shows first three-bit output is supplied to switching block 121 and ultimately controls the remaining group of four DAC elements, DACs 134-137); and
splitting, via a second branch point disposed along the first branch of the data path, the first branch into a first sub-branch of the first branch and a second sub-branch of the first branch (Fig. 2 illustrates the switching blocks 121 and 122 split their respective three-bit input signals into four two-bit output signals 144-147. Fig. 2 also shows the two outputs attributable to switching block 121 and output 144 and 145, which proceed to switching blocks 123 and 124, respectively).
However, Galton does not explicitly disclose, the branch points disposed centrally within the array.
In the same field of endeavor, Bogaerts discloses, the branch points disposed centrally within the array (The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]……. , the wiring extends from the output of the clock buffer 22 to the first branch point 51, is branched thereat, then one piece of the clock wiring 50 further extends from the one end of the pixel area 30 in the Y direction to a second branch point 57 positioned at a quarter distance, and is further bifurcated thereat, and one of the bifurcated pieces extends toward the one end of the unit pixel group array 35 of the Y direction and the other extends toward the first branch point 51 [0102]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed inventio to modify Galton by specifically providing the branch points disposed centrally within the array, as taught by Bogaerts for the purpose of significantly improving the measurement accuracy by correction only in the Y direction when a correction in a system level is performed [0025].
Regarding claim 38, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 37), in addition Bogaerts discloses,
wherein the first branch point is disposed at a center of the array (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point, [0091).
Regarding claim 39, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 37), further Galton discloses, wherein the data path comprises one or more multi-bit data buses (A digital signal x[n] is input into the switching block 120 via a four-bit bus 113, Col. 5; lines 65-Col. 6; lines 13).
Regarding claim 40, the combination Galton and Bogaerts discloses everything claimed as applied above (see claim 37), in addition Bogaerts discloses, wherein a physical layout of the data path is symmetrical about an axis of the array (FIG. 5 is a schematic diagram showing an example of a clock wiring layout of the TOF sensor 100. The output of the clock buffer 22 (TG1, TG2) on the last stage in the clock buffer area 20 extends to a first branch point 51 positioned at the midpoint of the pixel area 30 in the Y direction without connecting to any pixel, and bifurcated at this point [0091]; [0102]).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Galton, in view of Bogaerts and further in view of Norman et al. (US 20080143379, hereinafter “Norman”).
Regarding claim 30, the combination of Galton and Bogaerts discloses everything claimed as applied above (see claim 21), however the combination of Galton and Bogaerts does not disclose, wherein each respective branch of the respective branches to the plurality of cells comprises a same data path length.
In the same field of endeavor, Norman discloses, wherein each respective branch of the respective branches to the plurality of cells comprises a same data path length ( The key component of de-skewing circuitry is the distribution of the clock signal that coordinates the receiving and the re-sending of the signals. An H-tree clock distribution, as shown in FIG. 5, uses a series of H-shaped branchings of decreasing size to distribute a clock signal to a number of end-points [0285]-[0287]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Galton and Bogaerts by specifically providing wherein each respective branch of the respective branches to the plurality of cells comprises a same data path length, as taught by Norman for the purpose of providing an efficient internal network for interconnecting the contacts of components affixed to a programmable circuit board [0034].
Allowable Subject Matter
Claims 28 and 34-36 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 28, the following is a statement of reasons for the indication of allowable subject matter: the closest prior arts, Galton and Bogaerts, whether taken alone or in combination does not teach the following novel features:
“the device comprises wherein a branch point of the plurality of branch points comprises a decision unit configured to decode, at least in part, a received portion of the digital signal and output a first decision unit output down a first outgoing branch of the branch point and a second decision unit output down a second outgoing branch of the branch point, wherein the first decision unit output and the second decision unit output each comprise respective bit depths less than a bit depth of the received portion of the digital signal”, in combination with the other limitations in claims 21 and 26.
Regarding claim 34, the following is a statement of reasons for the indication of allowable subject matter: the closest prior arts, Galton and Bogaerts, whether taken alone or in combination does not teach the following novel features:
“wherein the first branch point comprises a decision unit configured to decode, at least in part, the input digital signal, wherein the decision unit comprises: an input configured to receive the digital signal, wherein the digital signal is indicative of respective activation signals for the plurality of cells; a first output configured to output the first intermediate signal, wherein the first intermediate signal is indicative of the respective activation signals for a first portion of the plurality of cells disposed in the first half of the array; a second output configured to output the second intermediate signal, wherein the second intermediate signal is indicative of the respective activation signals for a second portion of the plurality of cells disposed in the second half of the array; and circuitry configured to generate the first intermediate signal and the second intermediate signal based on the digital signal”, in combination with the other limitations in claim 31.
Claims 35 and 36 are allowed as those inherit the allowable subject matter from
claim 34.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 20210250038: The converter comprises capacitors. A control circuitry is provided to charge first and second subsets of the capacitors to respective first and second precharge voltages during a precharge interval by coupling the output node to a first voltage source. The inputs of the capacitors of the first subset is coupled to a first reference voltage and coupling the inputs of the capacitors of the second subset to a second reference voltage. The output node is decoupled from the first voltage source upon conclusion of the precharge interval.
US 11044422: Techniques are disclosed for systems and methods for facilitating pixel readout with partitioned analog-to-digital conversion. A device includes a detector, a capacitor coupled to the detector, a counter circuit coupled to the capacitor, a reset circuit coupled to the capacitor, and a processing circuit. The detector is configured to detect electromagnetic radiation associated with a scene and generate an associated detection signal. The capacitor is configured to, during an integration period, accumulate a voltage based on the detection signal.
US 20210073650: The method involves receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix. The multiplication results are modified by simulated binary-neural-processing hardware noise, simulating process voltage and temperature (PVT) variations of the hardware, to generate a binary output vector. The simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM SOROWAR whose telephone number is (571)270-3761. The examiner can normally be reached Mon-Fri: 8:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Appiah can be reached at (571) 272-7904. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GOLAM SOROWAR/ Primary Examiner, Art Unit 2641
Prosecution Insights