DETAILED ACTION
Claims 1-20 are pending.
Priority: 5/10/2024
Assignee: SK Hynix
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It is ambiguous based on the language of the claims and the spec, how the term “closed” is applied. In claims 1, 6, 9 and 14, an open block is “closed” after data is moved. But does this mean that the data is moved, and therefore it is closed or is there a more complex operation being applied, such as making sure there are no open sections. Applicant should further clarify how the term relates to the term open and the migration.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no clear teaching in the claims or the spec as to how the background operation closes all the open blocks of the second memory region. There is no teaching of a specific operation that does this. The most viable interpretation is that a background operation can close all the open blocks if there are open blocks to migrate to migrate data towards. But this is more of a vague functional than describing a specific operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 5, 6, 8, 18, 9 11, 12-14, 16-17, 18, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun(20210117122), and further in view of Xu et al.(20230360704).
As per claim 1, Byun discloses:
A memory controller which controls a storage medium(Byun, [0023 -- The memory system 110 includes a memory device 150 which stores data to be accessed by the host 102, and a controller 130 which controls storage of data in the memory device 150]) including a first memory region and a second memory region,(Byun, [0026 -- The nonvolatile memory 1501 may include a first region 1501A and a second region 1501B. ]);
each of which has a plurality of memory blocks(Byun, [0058 -- he nonvolatile memory 1501 may divide the plurality of memory blocks into the first region 1501A and the second region 1501B]), the memory controller comprising:
a background operation manager configured to determine an open block in the second memory region when a background operation is triggered(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host], [0060 -- Next, the migration module 136 selects, as a destination block, an open block in the second region 1501B], [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B]), move data of at least one victim block to the determined open block,( Byun, [0059 -- The open block OB is a block that stores data and includes at least one empty page capable of programming data therein. For example, the fifth memory block BLK5 of the second region 1501B may be an open block], [0059 -- The source block SB is a block that stores data and is in a closed state where a page capable of programming data therein is exhausted.]), the at least one victim block selected from at least one of the first memory region and the second memory region,(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.]) and erase the at least one victim block to generate at least one free block(Byun, [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]), and a processor configured to provide the at least one free block as a write block in response to a write request(Byun, [0059 -- Each of the plurality of memory blocks BLK1 to BLK10 may be classified into any of a free block FB, an open block OB or active block, and a source block SB. The free block FB indicates a block where no data is stored. For example, in FIG. 3, the fourth memory block BLK4 of the first region 1501A and the eighth to tenth memory blocks BLK8 to BLK10 of the second region 1501B may be free blocks.], [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block.]).
Byun does not explicitly disclose the following, however Xu discloses:
and to close the determined open block after the data is moved(Xu, [0058 -- If, however, the predetermine period of time has expired, at operation 315, the processing logic can logically closing the block], [0060 -- If, however, the block is a partial block, at operation 330, the processing logic initiates a partial block handling protocol for the block 410. In one embodiment, as described in more detail blow, block handling component 113 performs a series of padding operations on the block to program the unprogrammed subset of the plurality of wordlines (e.g., the wordlines storing pages 422-6 through 422-n) with padding data having a mixed data pattern. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Xu into the system of Byun for the benefit of ensuring that the partial block handling in a non-volatile memory device of a memory sub-system can be performed efficiently. The data can be stored at the memory device and retrieved from the memory devices. The performance of the host system can be improved. The power consumption can be reduced. The reliability of the memory system is increased. The cost involved in the manufacture of the system is reduced(Xu, 0019).
As per claim 3, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the background operation includes at least one of a garbage collection operation and a read reclaim operation(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host 102, and may include a background operation such as garbage collection, wear leveling, mapping table update, a rebuild operation by SPO, and read reclaim.]).
As per claim 4, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the first memory region supports a first program speed(Byun, [0027 -- the first region 1501A may be implemented as a memory that performs a high speed operation, and a mapping scheme suitable for the high speed operation may be applied to the first region 1501A]), and the second memory region supports a second program speed slower than the first program speed(Byun, [0028 -- On the other hand, the second region 1501B may be implemented as a memory that performs a low speed operation, and a mapping scheme suitable for the low speed operation may be applied to the second region 1501B… Since the second region 1501B needs to store 3-bit data per memory cell, it may take a longer time to perform signal processing and error correction operations, so that the processing speed in the second region 1501B may be relatively slower than the write operation speed in the first region 1501A.]).
As per claim 5, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the first memory region is controlled to operate to store n-bit data in one memory cell, where n is a natural number greater than or equal to 1(Byun, [0027 -- Furthermore, the first region 1501A may be configured as a single-level flash memory (SLC flash memory) that stores 1-bit data per memory cell.]), and the second memory region is controlled to operate to store k-bit data in one memory cell, where k is a natural number greater than or equal to 2(Byun, [0028 -- The second region 1501B may be configured as a multi-level flash memory (MLC flash memory) that stores N-bit data (N is an integer equal to or more than 2) per memory cell. ]).
As per claim 6, Byun discloses:
A memory controller which controls a storage medium(Byun, [0023 -- The memory system 110 includes a memory device 150 which stores data to be accessed by the host 102, and a controller 130 which controls storage of data in the memory device 150]) including a first memory region and a second memory region(Byun, [0026 -- The nonvolatile memory 1501 may include a first region 1501A and a second region 1501B. ]), each of which has a plurality of memory blocks(Byun, [0058 -- he nonvolatile memory 1501 may divide the plurality of memory blocks into the first region 1501A and the second region 1501B]), the memory controller comprising:
a processor configured to primarily program write data in a first memory block, which is a free block, selected from the first memory region in response to a write request(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.], [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]);
and a background operation manager configured to, in a background operation mode, select a second memory block, which is in an open state, from the second memory region(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host], [0060 -- Next, the migration module 136 selects, as a destination block, an open block in the second region 1501B], [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B]), program background data in the selected second memory block(Byun, [0059 -- The open block OB is a block that stores data and includes at least one empty page capable of programming data therein. For example, the fifth memory block BLK5 of the second region 1501B may be an open block], [0059 -- The source block SB is a block that stores data and is in a closed state where a page capable of programming data therein is exhausted.]), the background data detected from at least one of the first memory region and the second memory region,;
and generate, as a free block, a memory block in which the background data was detected(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.], [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]).
Byun does not explicitly disclose the following, however Xu discloses:
close the selected second memory block programmed with the background data(Xu, [0058 -- If, however, the predetermine period of time has expired, at operation 315, the processing logic can logically closing the block], [0060 -- If, however, the block is a partial block, at operation 330, the processing logic initiates a partial block handling protocol for the block 410. In one embodiment, as described in more detail blow, block handling component 113 performs a series of padding operations on the block to program the unprogrammed subset of the plurality of wordlines (e.g., the wordlines storing pages 422-6 through 422-n) with padding data having a mixed data pattern. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Xu into the system of Byun for the benefit of ensuring that the partial block handling in a non-volatile memory device of a memory sub-system can be performed efficiently. The data can be stored at the memory device and retrieved from the memory devices. The performance of the host system can be improved. The power consumption can be reduced. The reliability of the memory system is increased. The cost involved in the manufacture of the system is reduced(Xu, 0019).
As per claim 8, the rejection of claim 6 is incorporated, in addition, Byun discloses:
wherein the first memory region is controlled to operate to store n-bit data in one memory cell, where n is a natural number greater than or equal to 1(Byun, [0027 -- Furthermore, the first region 1501A may be configured as a single-level flash memory (SLC flash memory) that stores 1-bit data per memory cell.]), and the second memory region is controlled to operate to store k-bit data in one memory cell, where k is a natural number greater than or equal to 2(Byun, [0028 -- The second region 1501B may be configured as a multi-level flash memory (MLC flash memory) that stores N-bit data (N is an integer equal to or more than 2) per memory cell.]).
As per claim 9 discloses, Byun discloses:
A storage apparatus(Byun, [0021 -- The memory system 110 operates in response to a request of the host ]) comprising:
a storage medium including a first memory region and a second memory region(Byun, [0026 -- The nonvolatile memory 1501 may include a first region 1501A and a second region 1501B. ]), each of which has a plurality of memory blocks(Byun, [0058 -- The nonvolatile memory 1501 may divide the plurality of memory blocks into the first region 1501A and the second region 1501B]);
and a memory controller configured to, in a background operation, determine an open block in the second memory region(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host], [0060 -- Next, the migration module 136 selects, as a destination block, an open block in the second region 1501B], [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B]), move data of at least one victim block to the determined open block(Byun, [0059 -- The open block OB is a block that stores data and includes at least one empty page capable of programming data therein. For example, the fifth memory block BLK5 of the second region 1501B may be an open block], [0059 -- The source block SB is a block that stores data and is in a closed state where a page capable of programming data therein is exhausted.]), the at least one victim block selected from at least one of the first memory region and the second memory region(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.]),;
erase the at least one victim block to generate at least one free block(Byun, [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]), and provide the at least one free block as a write block in response to a write request(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.], [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]).
Byun does not explicitly disclose the following, however Xu discloses:
close the open block where the data of the at least one victim block has been moved to(Xu, [0058 -- If, however, the predetermine period of time has expired, at operation 315, the processing logic can logically closing the block], [0060 -- If, however, the block is a partial block, at operation 330, the processing logic initiates a partial block handling protocol for the block 410. In one embodiment, as described in more detail blow, block handling component 113 performs a series of padding operations on the block to program the unprogrammed subset of the plurality of wordlines (e.g., the wordlines storing pages 422-6 through 422-n) with padding data having a mixed data pattern. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Xu into the system of Byun for the benefit of ensuring that the partial block handling in a non-volatile memory device of a memory sub-system can be performed efficiently. The data can be stored at the memory device and retrieved from the memory devices. The performance of the host system can be improved. The power consumption can be reduced. The reliability of the memory system is increased. The cost involved in the manufacture of the system is reduced(Xu, 0019).
Claim 11 is directed to a storage apparatus that implements the memory controller limitations of claim 3, and therefore the corresponding citations are incorporated.
Claim 12 is directed to a storage apparatus that implements the memory controller limitations of claim 4, and therefore the corresponding citations are incorporated.
Claim 13 is directed to a storage apparatus that implements the memory controller limitations of claim 5, and therefore the corresponding citations are incorporated.
As per claim 14, Byun discloses:
An operating method of a memory controller which controls(Byun, [0023 -- The memory system 110 includes a memory device 150 which stores data to be accessed by the host 102, and a controller 130 which controls storage of data in the memory device 150.]) a storage medium including a first memory region and a second memory region(Byun, [0026 -- The nonvolatile memory 1501 may include a first region 1501A and a second region 1501B. ]), each of which has a plurality of memory blocks(Byun, [0058 -- The nonvolatile memory 1501 may divide the plurality of memory blocks into the first region 1501A and the second region 1501B]), the method comprising:
determining an open block in the second memory region when a background operation is triggered(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host], [0060 -- Next, the migration module 136 selects, as a destination block, an open block in the second region 1501B], [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B]);
moving data of at least one victim block to the determined open block(Byun, [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B, which has a page capable of programming valid data therein, and copies valid data stored in the victim block of the first region 1501A into the destination block]), the at least one victim block selected from at least one of the first memory region and the second memory region(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.]);
erasing the at least one victim block to generate at least one free block(Byun, [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]) and providing the at least one free block as a write block in response to a write request(Byun, [0064 -- In step S403, the migration module 136 selects, as a victim block, a source block with the smaller number of valid pages than an arbitrarily set threshold value among the checked source blocks in the first region 1501A.], [0066 -- In step S407, when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]).
Byun does not explicitly disclose the following, however Xu discloses:
converting the determined open block where the data of the at least one victim block has been moved to, into a closed state(Xu, [0058 -- If, however, the predetermine period of time has expired, at operation 315, the processing logic can logically closing the block], [0060 -- If, however, the block is a partial block, at operation 330, the processing logic initiates a partial block handling protocol for the block 410. In one embodiment, as described in more detail blow, block handling component 113 performs a series of padding operations on the block to program the unprogrammed subset of the plurality of wordlines (e.g., the wordlines storing pages 422-6 through 422-n) with padding data having a mixed data pattern. ]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Xu into the system of Byun for the benefit of ensuring that the partial block handling in a non-volatile memory device of a memory sub-system can be performed efficiently. The data can be stored at the memory device and retrieved from the memory devices. The performance of the host system can be improved. The power consumption can be reduced. The reliability of the memory system is increased. The cost involved in the manufacture of the system is reduced(Xu, 0019).
Claim 16 is directed to method/steps that implements the memory controller limitations of claim 3, and therefore the corresponding citations are incorporated.
Claim 17 is directed to method/steps that implements the memory controller limitations of claim 5, and therefore the corresponding citations are incorporated.
As per claim 18, the rejection of claim 6 is incorporated, in addition, Byun discloses:
wherein the first memory region supports a first program speed(Byun, [0027 -- the first region 1501A may be implemented as a memory that performs a high speed operation, and a mapping scheme suitable for the high speed operation may be applied to the first region 1501A]), and the second memory region supports a second program speed slower than the first program speed(Byun, [0028 -- On the other hand, the second region 1501B may be implemented as a memory that performs a low speed operation, and a mapping scheme suitable for the low speed operation may be applied to the second region 1501B… Since the second region 1501B needs to store 3-bit data per memory cell, it may take a longer time to perform signal processing and error correction operations, so that the processing speed in the second region 1501B may be relatively slower than the write operation speed in the first region 1501A.]).
Claim 19 is directed to method/steps that implements the memory controller limitations of claim 4, and therefore the corresponding citations are incorporated.
As per claim 20, the rejection of claim 1 is incorporated, in addition, Byun does not explicitly disclose the following, however Xu discloses:
wherein the background operation manager is configured to perform the background operation to close all of the open blocks of the second memory region(Xu, [0058 -- If, however, the predetermine period of time has expired, at operation 315, the processing logic can logically closing the block], [0060 -- If, however, the block is a partial block, at operation 330, the processing logic initiates a partial block handling protocol for the block 410. In one embodiment, as described in more detail blow, block handling component 113 performs a series of padding operations on the block to program the unprogrammed subset of the plurality of wordlines (e.g., the wordlines storing pages 422-6 through 422-n) with padding data having a mixed data pattern. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Xu into the system of Byun for the benefit of ensuring that the partial block handling in a non-volatile memory device of a memory sub-system can be performed efficiently. The data can be stored at the memory device and retrieved from the memory devices. The performance of the host system can be improved. The power consumption can be reduced. The reliability of the memory system is increased. The cost involved in the manufacture of the system is reduced(Xu, 0019).
Claim(s) 2, 7, 10 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun(20210117122), Byun(20210117122), and further in view of Xu et al.(20230360704) and further in view of Kim et al.(20210034536).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), and the memory controller is configured to, in response to the write request, primarily program the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]) and secondarily program, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 7, the rejection of claim 6 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the processor is configured to secondarily program, in a memory block selected from the second memory region, the write data primarily programmed in the first memory block(Kim, [0138 -- For example, the user data may migrate or move between the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np depending on an explicit request of the host 1100, an internal policy of the storage device 1200, or a change of the internal policy according to a request of the host 1100.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 10, the rejection of claim 9 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), and the memory controller is configured to, in response to the write request, primarily program the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]) and secondarily program, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 15, the rejection of claim 14 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, and the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), further comprising, in response to the write request, primarily programming the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]);
and secondarily programming, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 2/4/2026 have been considered but are moot because the new ground of rejection does not rely the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al.(20200409835) where the data storage device has a non-volatile memory that comprises a storage space that is divided into blocks. A controller is configured to control the non-volatile memory. The controller records a programming order of the blocks when programming write data issued by a host to the non-volatile memory. The controller copies valid data of a first source block to a first destination block and then copies valid data of a second source block to the first destination block. the controller releases the first source block and second source block to complete a first type of garbage collection after coping valid data from the first source block and the second source block to the first destination block.
Natarajan et al.(20220004495) where the semiconductor apparatus comprises a logic that is coupled to substrates, where the logic is implemented partly in configurable, or fixed-functionality hardware logic. The logic receives a set of read and write requests from a host via a memory controller (104) of a memory device, and maintains a valid unit count of operational memory cells on a block-by-block basis for memory blocks via the memory controller. The memory controller maintains a hotness index count based on hotness data, and selects the memory blocks for eviction based on the valid and hotness indexes counts, where eviction is from a single level cell region to an x-level cell region.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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