DETAILED ACTION
Claims 1-19 are pending.
Priority: 5/10/2024
Assignee: SK Hynix
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/3/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-6, 8-9, 11-14, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun(20210117122), in view of Yanagida(20180276118), and further in view of Pletka et al.(20200257621).
As per claim 1, Byun discloses:
A memory controller which controls a storage medium including a first memory region and a second memory region, each of which has a plurality of memory blocks(Byun, [0026 -- The memory device 150 may include a plurality of nonvolatile memories and may perform operations (for example, a read operation, a write operation, and the like) corresponding to requests of the controller 130 under the control of the controller]), the memory controller comprising:
a background operation manager configured to determine an open block in a state in use in the second memory region when a background operation is triggered(Byun, [0059 -- Each of the plurality of memory blocks BLK1 to BLK10 may be classified into any of a free block FB, an open block OB or active block, and a source block SB. The free block FB indicates a block where no data is stored.]), move data of at least one victim block selected from at least one of the first memory region and the second memory region to the determined open block,(Byun, [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B, which has a page capable of programming valid data therein, and copies valid data stored in the victim block of the first region]);
and erase the at least on victim block to generate at least one free block(Byun, [0066 -- when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]);
Byun does not explicitly disclose the following, however Yanagida discloses:
and close the determined open block by setting the determined open block not to store data after the data is moved,(Yanagida, [0055 -- In S220, in a case where data is written up to the end of the logical block of the garbage collection destination (Yes in S220), the GC write unit 36 increments the count value of the write completion counter 45 (S240) and requests the data management unit 31 so that the writing destination block in which data is written up to the end thereof is managed as an active block in stream management information 44. The GC write unit 36 determines whether the incremented count value reaches the target value C2 of the write completion number or not]);
Therefore it would have been obvious to a POSITA to incorporate the features of Yanagida into the system of Byun for the benefit of a system that enables all pieces of data associated with the same stream identification data to be invalidated together when the host erases pieces of data to decrease execution frequency of rubbish collection and improve performance deterioration and lifetime reduction of the system by a control circuit executing a second rubbish collection for a second stream by reading valid third data stored in a fourth block associated with the second stream and valid fourth data stored in a fifth block associated with the second stream from a nonvolatile memory and writing the read third and fourth data into sixth blocks of the nonvolatile memory that are associated with the second stream(Yanagida, 0072).
Byun, Yanagida does not explicitly disclose the following, however Pletka discloses:
a processor configured to provide the at least one free block in the first memory region as a write block in response to a subsequent write request after the determined open block is closed(Pletka, [0034 -- Once programming of physical pages in a block or block stripe has closed, flash controller 140 places an identifier of the block or block stripe into one of the pools in the occupied block pools 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection.], [0045 -- As has been described, in at least some embodiments, a non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block]).
Therefore it would have been obvious to a POSITA to incorporate the features of Pletka into the system of Byun, Yanagida for the benefit of a controller of a non-volatile memory that promotes improved read threshold voltage calibration by fully programming a dependent layer in a target block written during garbage collection, and thus, avoiding leaving an open interface by transferring a valid data from a source block (204) to a target block by a controller based on determination to perform garbage collection for a non-volatile memory. A valid data is transferred from the source block to the target block. The garbage collection on source block is ended with a valid data present in the source block based on all interfaces of the target block being closed at the boundary of independent physical layers within the non-volatile memory(Pletka, 009).
As per claim 3, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the background operation includes at least one of a garbage collection operation and a read reclaim operation(Byun, [0054 -- The device task is a term used to mean a task in which the controller 130 performs a background operation of the memory device 150 in a specific state independently of the host 102, and may include a background operation such as garbage collection, wear leveling, mapping table update, a rebuild operation by SPO, and read reclaim.]).
As per claim 4, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the first memory region supports a first program speed(Byun, [0027 -- the first region 1501A may be implemented as a memory that performs a high speed operation, and a mapping scheme suitable for the high speed operation may be applied to the first region 1501A]), and the second memory region supports a second program speed slower than the first program speed(Byun, [0028 -- On the other hand, the second region 1501B may be implemented as a memory that performs a low speed operation, and a mapping scheme suitable for the low speed operation may be applied to the second region 1501B… Since the second region 1501B needs to store 3-bit data per memory cell, it may take a longer time to perform signal processing and error correction operations, so that the processing speed in the second region 1501B may be relatively slower than the write operation speed in the first region 1501A.]).
As per claim 5, the rejection of claim 1 is incorporated, in addition, Byun discloses:
wherein the first memory region is controlled to operate to store n-bit data in one memory cell, where n is a natural number greater than or equal to 1(Byun, [0027 -- Furthermore, the first region 1501A may be configured as a single-level flash memory (SLC flash memory) that stores 1-bit data per memory cell.]), and the second memory region is controlled to operate to store k-bit data in one memory cell, where k is a natural number greater than or equal to 2(Byun, [0028 -- The second region 1501B may be configured as a multi-level flash memory (MLC flash memory) that stores N-bit data (N is an integer equal to or more than 2) per memory cell. ]).
As per claim 6, Byun discloses:
A memory controller which controls a storage medium including a first memory region and a second memory region, each of which has a plurality of memory blocks(Byun, [0026 -- The memory device 150 may include a plurality of nonvolatile memories and may perform operations (for example, a read operation, a write operation, and the like) corresponding to requests of the controller 130 under the control of the controller]), the memory controller comprising:
and a background operation manager configured to, in a background operation mode, select a second memory block, which is open block in a in use, from the second memory region(Byun, [0059 -- Each of the plurality of memory blocks BLK1 to BLK10 may be classified into any of a free block FB, an open block OB or active block, and a source block SB. The free block FB indicates a block where no data is stored. For example, in FIG. 3, the fourth memory block BLK4 of the first region 1501A and the eighth to tenth memory blocks BLK8 to BLK10 of the second region 1501B may be free blocks. ]), program background data in the selected second memory block, the background data detected from at least one of the first memory region and the second memory region,(Byun, [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B, which has a page capable of programming valid data therein, and copies valid data stored in the victim block of the first region ]);
generate, as a free block, at least one a-memory block in the first memory region in which the background data was detected,(Byun, [0066 -- when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]);
Byun does not explicitly disclose the following, however Yanagida discloses:
close the selected second memory block programmed with the background data by setting not to store data,(Yanagida, [0055 -- In S220, in a case where data is written up to the end of the logical block of the garbage collection destination (Yes in S220), the GC write unit 36 increments the count value of the write completion counter 45 (S240) and requests the data management unit 31 so that the writing destination block in which data is written up to the end thereof is managed as an active block in stream management information 44. The GC write unit 36 determines whether the incremented count value reaches the target value C2 of the write completion number or not]);
Therefore it would have been obvious to a POSITA to incorporate the features of Yanagida into the system of Byun for the benefit of a system that enables all pieces of data associated with the same stream identification data to be invalidated together when the host erases pieces of data to decrease execution frequency of rubbish collection and improve performance deterioration and lifetime reduction of the system by a control circuit executing a second rubbish collection for a second stream by reading valid third data stored in a fourth block associated with the second stream and valid fourth data stored in a fifth block associated with the second stream from a nonvolatile memory and writing the read third and fourth data into sixth blocks of the nonvolatile memory that are associated with the second stream(Yanagida, 0072).
Byun, Yanagida does not explicitly disclose the following, however Pletka discloses:
a processor configured to primarily program write data in a first memory block, which is a free block, selected from the first memory region in response to a write request(Pletka, [0034 -- Once programming of physical pages in a block or block stripe has closed, flash controller 140 places an identifier of the block or block stripe into one of the pools in the occupied block pools 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection. As noted above, through the write process, logical pages are invalidated, and therefore portions of the NAND flash memory system 150 become unused.]);
and provide the at least one free block in the first memory region as a write block in response to a subsequent write request after the determined open block is closed(Pletka, [0034 -- Once programming of physical pages in a block or block stripe has closed, flash controller 140 places an identifier of the block or block stripe into one of the pools in the occupied block pools 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection.], [0045 -- As has been described, in at least some embodiments, a non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block]).
Therefore it would have been obvious to a POSITA to incorporate the features of Pletka into the system of Byun, Yanagida for the benefit of a controller of a non-volatile memory that promotes improved read threshold voltage calibration by fully programming a dependent layer in a target block written during garbage collection, and thus, avoiding leaving an open interface by transferring a valid data from a source block (204) to a target block by a controller based on determination to perform garbage collection for a non-volatile memory. A valid data is transferred from the source block to the target block. The garbage collection on source block is ended with a valid data present in the source block based on all interfaces of the target block being closed at the boundary of independent physical layers within the non-volatile memory(Pletka, 009).
As per claim 8, the rejection of claim 6 is incorporated, in addition, Byun discloses:
wherein the first memory region is controlled to operate to store n-bit data in one memory cell, where n is a natural number greater than or equal to 1(Byun, [0027 -- Furthermore, the first region 1501A may be configured as a single-level flash memory (SLC flash memory) that stores 1-bit data per memory cell.]), and the second memory region is controlled to operate to store k-bit data in one memory cell, where k is a natural number greater than or equal to 2(Byun, [0028 -- The second region 1501B may be configured as a multi-level flash memory (MLC flash memory) that stores N-bit data (N is an integer equal to or more than 2) per memory cell.]).
As per claim 9, Byun discloses:
A storage apparatus comprising: a storage medium including a first memory region and a second memory region, each of which has a plurality of memory blocks(Byun, [0026 -- The memory device 150 may include a plurality of nonvolatile memories and may perform operations (for example, a read operation, a write operation, and the like) corresponding to requests of the controller 130 under the control of the controller]) and a memory controller configured to,;
in a background operation, determine an open block in a state in use in the second memory region(Byun, [0059 -- Each of the plurality of memory blocks BLK1 to BLK10 may be classified into any of a free block FB, an open block OB or active block, and a source block SB. The free block FB indicates a block where no data is stored.]), move data of at least one victim block to the determined open block, the at least one victim block selected from at least one of the first memory region and the second memory region,(Byun, [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B, which has a page capable of programming valid data therein, and copies valid data stored in the victim block of the first region]);
erase the at least one victim block in the first memory region to generate at least one free block,(Byun, [0066 -- when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]);
Byun does not explicitly disclose the following, however Yanagida discloses:
close the open block, by setting the determined open block not to store data, where the data of the victim block has been moved to,(Yanagida, [0055 -- In S220, in a case where data is written up to the end of the logical block of the garbage collection destination (Yes in S220), the GC write unit 36 increments the count value of the write completion counter 45 (S240) and requests the data management unit 31 so that the writing destination block in which data is written up to the end thereof is managed as an active block in stream management information 44. The GC write unit 36 determines whether the incremented count value reaches the target value C2 of the write completion number or not]);
Therefore it would have been obvious to a POSITA to incorporate the features of Yanagida into the system of Byun for the benefit of a system that enables all pieces of data associated with the same stream identification data to be invalidated together when the host erases pieces of data to decrease execution frequency of rubbish collection and improve performance deterioration and lifetime reduction of the system by a control circuit executing a second rubbish collection for a second stream by reading valid third data stored in a fourth block associated with the second stream and valid fourth data stored in a fifth block associated with the second stream from a nonvolatile memory and writing the read third and fourth data into sixth blocks of the nonvolatile memory that are associated with the second stream(Yanagida, 0072).
Byun, Yanagida does not explicitly disclose the following, however Pletka discloses:
and provide the at least one free block in the first memory region as a write block in response to a subsequent write request after the determined open block is closed(Pletka, [0034 -- Once programming of physical pages in a block or block stripe has closed, flash controller 140 places an identifier of the block or block stripe into one of the pools in the occupied block pools 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection.], [0045 -- As has been described, in at least some embodiments, a non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block]).
Therefore it would have been obvious to a POSITA to incorporate the features of Pletka into the system of Byun, Yanagida for the benefit of a controller of a non-volatile memory that promotes improved read threshold voltage calibration by fully programming a dependent layer in a target block written during garbage collection, and thus, avoiding leaving an open interface by transferring a valid data from a source block (204) to a target block by a controller based on determination to perform garbage collection for a non-volatile memory. A valid data is transferred from the source block to the target block. The garbage collection on source block is ended with a valid data present in the source block based on all interfaces of the target block being closed at the boundary of independent physical layers within the non-volatile memory(Pletka, 009).
Claim 11 is directed to a storage apparatus that implements the memory controller limitations of claim 3, and therefore the corresponding citations are incorporated.
Claim 12 is directed to a storage apparatus that implements the memory controller limitations of claim 4, and therefore the corresponding citations are incorporated.
Claim 13 is directed to a storage apparatus that implements the memory controller limitations of claim 5, and therefore the corresponding citations are incorporated.
As per claim 14, Byun discloses:
An operating method of a memory controller which controls a storage medium including a first memory region and a second memory region, each of which has a plurality of memory blocks(Byun, [0026 -- The memory device 150 may include a plurality of nonvolatile memories and may perform operations (for example, a read operation, a write operation, and the like) corresponding to requests of the controller 130 under the control of the controller]), the method comprising:
determining an open block in a state in use in the second memory region when a background operation is triggered(Byun, [0059 -- Each of the plurality of memory blocks BLK1 to BLK10 may be classified into any of a free block FB, an open block OB or active block, and a source block SB. The free block FB indicates a block where no data is stored.]), moving data of at least one victim block selected from at least one of the first memory region and the second memory region to the determined open block(Byun, [0065 -- In step S405, the migration module 136 selects, as a destination block, an open block in the second region 1501B, which has a page capable of programming valid data therein, and copies valid data stored in the victim block of the first region]);
erasing the at least one victim block in the first memory region to generate at least one free block(Byun, [0066 -- when the valid data stored in the victim block of the first region 1501A is copied into the destination block in the second region 1501B, the migration module 136 may erase all data stored in the victim block of the first region 1501A, and then set the victim block as a free block]);
Byun does not explicitly disclose the following, however Yanagida discloses:
converting, by setting the determined open block not to store data, the determined open block, where the data of the at least one victim block has been moved to, into a closed state(Yanagida, [0055 -- In S220, in a case where data is written up to the end of the logical block of the garbage collection destination (Yes in S220), the GC write unit 36 increments the count value of the write completion counter 45 (S240) and requests the data management unit 31 so that the writing destination block in which data is written up to the end thereof is managed as an active block in stream management information 44. The GC write unit 36 determines whether the incremented count value reaches the target value C2 of the write completion number or not]);
Therefore it would have been obvious to a POSITA to incorporate the features of Yanagida into the system of Byun for the benefit of a system that enables all pieces of data associated with the same stream identification data to be invalidated together when the host erases pieces of data to decrease execution frequency of rubbish collection and improve performance deterioration and lifetime reduction of the system by a control circuit executing a second rubbish collection for a second stream by reading valid third data stored in a fourth block associated with the second stream and valid fourth data stored in a fifth block associated with the second stream from a nonvolatile memory and writing the read third and fourth data into sixth blocks of the nonvolatile memory that are associated with the second stream(Yanagida, 0072).
Byun, Yanagida does not explicitly disclose the following, however Pletka discloses:
and providing the at least one free block in the first memory region as a write block in response to a subsequent write request after the determined open block is closed(Pletka, [0034 -- Once programming of physical pages in a block or block stripe has closed, flash controller 140 places an identifier of the block or block stripe into one of the pools in the occupied block pools 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection.], [0045 -- As has been described, in at least some embodiments, a non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block]).
Therefore it would have been obvious to a POSITA to incorporate the features of Pletka into the system of Byun, Yanagida for the benefit of a controller of a non-volatile memory that promotes improved read threshold voltage calibration by fully programming a dependent layer in a target block written during garbage collection, and thus, avoiding leaving an open interface by transferring a valid data from a source block (204) to a target block by a controller based on determination to perform garbage collection for a non-volatile memory. A valid data is transferred from the source block to the target block. The garbage collection on source block is ended with a valid data present in the source block based on all interfaces of the target block being closed at the boundary of independent physical layers within the non-volatile memory(Pletka, 009).
Claim 16 is directed to method/steps that implements the memory controller limitations of claim 3, and therefore the corresponding citations are incorporated.
Claim 17 is directed to method/steps that implements the memory controller limitations of claim 5, and therefore the corresponding citations are incorporated.
As per claim 18, the rejection of claim 6 is incorporated, in addition, Byun discloses:
wherein the first memory region supports a first program speed(Byun, [0027 -- the first region 1501A may be implemented as a memory that performs a high speed operation, and a mapping scheme suitable for the high speed operation may be applied to the first region 1501A]), and the second memory region supports a second program speed slower than the first program speed(Byun, [0028 -- On the other hand, the second region 1501B may be implemented as a memory that performs a low speed operation, and a mapping scheme suitable for the low speed operation may be applied to the second region 1501B… Since the second region 1501B needs to store 3-bit data per memory cell, it may take a longer time to perform signal processing and error correction operations, so that the processing speed in the second region 1501B may be relatively slower than the write operation speed in the first region 1501A.]).
Claim 19 is directed to method/steps that implements the memory controller limitations of claim 4, and therefore the corresponding citations are incorporated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 7, 10 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun(20210117122), in view of Yanagida(20180276118), in view of Pletka et al.(20200257621), and further in view of Kim et al.(20210034536).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), and the memory controller is configured to, in response to the write request, primarily program the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]) and secondarily program, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun, Yanagida, Pletka for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 7, the rejection of claim 6 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the processor is configured to secondarily program, in a memory block selected from the second memory region, the write data primarily programmed in the first memory block(Kim, [0138 -- For example, the user data may migrate or move between the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np depending on an explicit request of the host 1100, an internal policy of the storage device 1200, or a change of the internal policy according to a request of the host 1100.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun, Yanagida, Pletka for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 10, the rejection of claim 9 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), and the memory controller is configured to, in response to the write request, primarily program the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]) and secondarily program, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun, Yanagida, Pletka for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
As per claim 15, the rejection of claim 14 is incorporated, in addition, Byun does not explicitly disclose the following in its entirety, however Kim discloses:
wherein the write request includes write data, and the at least one victim block is selected from the first memory region(Kim, [0159 -- In other words, the storage device 1200 may perform the turbo write on the first data DT1. In an exemplary embodiment of the inventive concept, in the case where the turbo write function is enabled, whether to store data in any one of the pinned turbo write buffer TWB-p and the non-pinned turbo write buffer TWB-np may be determined through various schemes.]), further comprising, in response to the write request, primarily programming the write data in the write block of the first memory region(Kim, [0158 -- Referring to FIGS. 1, 8, and 10A, the storage device 1200 may receive first data DT1 corresponding to a first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the turbo write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the turbo write buffer TWB (e.g., the non-pinned turbo write buffer TWB-np).]);
and secondarily programming, in the second memory region, the write data primarily programmed in the first memory region(Kim, [0138 -- user data may be flushed, migrated, or moved between the pinned turbo write buffer TWB-p, the non-pinned turbo write buffer TWB-np, and the user storage UST.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Kim into the system of Byun, Yanagida, Pletka for the benefit of a user capacity reduction mode being provided as a mode to reduce user capacity of user storage for the purpose of using a turbo write buffer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al.(20200409835) where the data storage device has a non-volatile memory that comprises a storage space that is divided into blocks. A controller is configured to control the non-volatile memory. The controller records a programming order of the blocks when programming write data issued by a host to the non-volatile memory. The controller copies valid data of a first source block to a first destination block and then copies valid data of a second source block to the first destination block. the controller releases the first source block and second source block to complete a first type of garbage collection after coping valid data from the first source block and the second source block to the first destination block.
Natarajan et al.(20220004495) where the semiconductor apparatus comprises a logic that is coupled to substrates, where the logic is implemented partly in configurable, or fixed-functionality hardware logic. The logic receives a set of read and write requests from a host via a memory controller (104) of a memory device, and maintains a valid unit count of operational memory cells on a block-by-block basis for memory blocks via the memory controller. The memory controller maintains a hotness index count based on hotness data, and selects the memory blocks for eviction based on the valid and hotness indexes counts, where eviction is from a single level cell region to an x-level cell region.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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