DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks submitted on 07/13/2026, with respect to the restriction requirement has been considered and they are persuasive. The restriction requirement has been withdrawn. Accordingly, claims 1-20 will be examined.
Priority
The present application, 18913524, filed 10/11/2024 is a Divisional of 16403245, filed 05/03/2019, now U.S. Patent # 12118056.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/28/2024 and 10/30/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Control logic first recited in claim 6
Memory sense component first recited in claim 6
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Control logic (first recited in claim 6): See fig. 3A, 5A-5C reference 315/508 and paragraph [0114] “the logic includes internal processor-in-memory”
memory sense component (first recited in claim 6): See Fig. 3 reference 318 and paragraph [0097] "The column decoder 318 can selectively sense/drive various ones of the column terminals so as to "read" and/or "write" to the corresponding memory cell that is uniquely identified by the selected row and column (as emphasized in FIG. 3 by the heavier line width and blackened cell element); paragraph [0126] "analog-to-digital (ADC) sense amps"; paragraph [0162] "the column decoder is reconfigured to sense analog signals corresponding to a column of varying conductance cells that are driven by corresponding rows of varying signaling. The column decoder converts an analog signal to a digital value"
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 15 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “wherein the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure are logically combined” in lines 4-6. This limitation is unclear because it merely states a function (that the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure must somehow be logically combined) that is not performed by any structure recited in the claim. The recited function does not follow from the structure recited in the claim, i.e., the processor, so it is unclear whether the function requires some other structure or is simply a result of operating the device in a certain manner. For purposes of examination, this is interpreted as wherein the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure are logically combined using an arithmetic and logic unit (ALU) consistent with Fig. 4 and paragraphs [0104-0105].
Claim 15 recites “the row and column terminals” in line 2. There is insufficient antecedent basis for this limitation in the claim. Row and column terminals are introduced in claim 14, however, claim 15 does not depend on claim 14. For purposes of examination, claim 15 is interpreted to depend on claim 14.
Claim 20 recites “the memory sense component” in line 1. There is insufficient antecedent basis for this limitation in the claim. Memory sense component is introduced in claim 19, however, claim 20 does not depend on claim 19. For purposes of examination, claim 20 is interpreted to depend on claim 19.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 7 fails to further limit the subject matter of claim 6 upon which it depends because the limitations of claim 7 are already incorporated into claim 6 and are merely rephrasing the limitations in claim 6. Claim 7 recites “wherein the receipt of the one or more instructions comprises receipt of the one or more instructions from the processor apparatus” which is merely rephrasing the limitations of “receive one or more instructions for an input transformation from the processor apparatus” recited in claim 6.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 3-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-13 of U.S. Patent No. US 11449577 B2 (reference patent). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 3-5 under examination are anticipated by claims 10-13 respectively of the reference patent. Every limitation in the application under examination claims are recited in the conflicting reference patent claim as shown in the table below.
18913524
US 11449577 B2
1. A device, comprising:
10. A device, comprising:
a processor coupled to a non-transitory computer readable medium;
a processor coupled to a non-transitory computer readable medium;
wherein the non-transitory computer readable medium comprises one or more instructions which, when executed by the processor, cause the processor to:
wherein the non-transitory computer readable medium comprises one or more instructions which, when executed by the processor, cause the processor to:
write a matrix transformation opcode and a matrix transformation operand to the non-transitory computer readable medium;
write a discrete cosine transform (DCT) matrix transformation opcode and a matrix transformation operand to the non-transitory computer readable medium;
wherein the matrix transformation opcode causes the non-transitory computer readable medium to operate an array of memory cells as a matrix structure;
wherein the DCT matrix transformation opcode causes the non-transitory computer readable medium to operate an array of memory cells as a matrix structure;
wherein the matrix transformation operand modifies one or more analog values of the matrix structure; and
wherein the matrix transformation operand modifies one or more analog values of the matrix structure; and
read a matrix transformation result from the matrix structure.
read a matrix transformation result from the matrix structure.
3. The device of claim 1, wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to:
11. The device of claim 10, wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to:
receive video data comprising one or more image blocks;
receive video data comprising one or more image blocks;
wherein the matrix transformation operand comprises the one or more image blocks and the matrix transformation result comprises one or more frequency domain image coefficients; and
wherein the matrix transformation operand comprises the one or more image blocks and the matrix transformation result comprises one or more DCT frequency domain image coefficients; and
wherein the one or more analog values of the matrix structure accumulate the one or more frequency domain image coefficients from video data over time.
wherein the one or more analog values of the matrix structure accumulate the one or more DCT frequency domain image coefficients from video data over time.
4. The device of claim 1, wherein the matrix transformation opcode causes the non-transitory computer readable medium to operate another array of memory cells as another matrix structure; and
12. The device of claim 10, wherein the DCT matrix transformation opcode causes the non-transitory computer readable medium to operate another array of memory cells as another matrix structure; and
wherein the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure are logically combined.
wherein the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure are logically combined.
5. The device of claim 1, wherein the one or more analog values of the matrix structure are stored within a look-up-table data structure.
13. The device of claim 10, wherein the one or more analog values of the matrix structure are stored within a look-up-table (LUT) data structure.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 11449577 B2 in view of Hu et al. (NPL – “Accelerating Discrete Fourier Transforms with Dot-product Engine”), hereinafter Hu. Hu is cited in the IDS submitted on 10/28/2024.
Regarding claim 2, claim 1 of the reference patent teaches all the limitations of claim 1 as stated above.
Claim 1 of the reference patent does not explicitly teach wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values.
However, on the same field of endeavor, Hu discloses capturing image data comprising one or more captured color values; and performing a matrix transformation using the captured image data as a matrix transformation operand and wherein a matrix transformation result comprises one or more shifted color values (Hu page 4 section V subsection A-B and Figs. 7-9).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify claim 1 of the reference patent using Hu and configure the non-transitory computer readable medium to include one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values in order to implement a system for performing DFT and/or DCT (Hu section IV and V).
Therefore, the combination of claim 1 of the reference patent as modified in view of Hu teaches wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of U.S. Patent No. US 12118056 B2 (reference patent). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 16-20 under examination are anticipated by claims 1, 7, 1, 1, 1 respectively of the reference patent. Every limitation in the application under examination claims are recited in the conflicting reference patent claim as shown in the table below.
16403245
US 12118056 B2
16. A device comprising:
1. An apparatus comprising:
a plurality of arrays of memory cells, wherein:
a plurality of arrays of memory cells
the plurality of arrays of memory cells comprises a first bank of arrays of the plurality of arrays of memory cells configured as a memory, the plurality of arrays of memory cells comprises a second bank of arrays of the plurality of arrays of memory cells configured as a matrix fabric, and
wherein: the plurality of arrays of memory cells comprises a first bank of arrays of the plurality of arrays of memory cells and a second bank of arrays of the plurality of arrays of memory cells, the first bank of arrays is configured as a memory, the second bank of arrays is configured as a matrix fabric
the plurality of arrays of memory cells are dynamically configurable to be partitioned in either of the first bank of arrays or the second bank of arrays.
the plurality of arrays of memory cells are dynamically configurable to be partitioned in either of the first bank of arrays or the second bank of arrays
17. The device of claim 16, wherein the memory cells of the plurality of arrays of memory cells comprise resistive random access memory cells.
7. The apparatus of claim 1, wherein each memory cell of the MMU comprises resistive random access memory (ReRAM) cells.
18. The device of claim 16, wherein the first bank of arrays are configurable as the memory at the same time as the second bank of arrays being configurable as the matrix fabric.
1. the plurality of arrays of memory cells comprises a first bank of arrays of the plurality of arrays of memory cells and a second bank of arrays of the plurality of arrays of memory cells, the first bank of arrays is configured as a memory, the second bank of arrays is configured as a matrix fabric, and the plurality of arrays of memory cells are dynamically configurable to be partitioned in either of the first bank of arrays or the second bank of arrays;
19. The device of claim 16, wherein each memory cell of the plurality of arrays of memory cells are configured to store a digital value as an analog value in an analog medium, and wherein the device further comprises a memory sense component configured to read the analog value of a first memory cell as a first digital value.
1. a plurality of arrays of memory cells, where each memory cell of the plurality of arrays of memory cells are configured to store a digital value as an analog value in an analog medium; a memory sense component, where the memory sense component is configured to read the analog value of a first memory cell as a first digital value
20. The device of claim 16, wherein the memory sense component is configured to convert the analog value of the first memory cell into a second digital value in accordance with a matrix transformation opcode and a matrix transformation operand.
1. the memory sense component to convert the analog value of the first memory cell into a second digital value in accordance with the matrix transformation opcode and the matrix transformation operand;
Claims 6-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12-15 of U.S. Patent No. US 12118056 B2 (reference patent) in view of Chi et al. (NPL – “PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory”), hereinafter Chi. Chi is cited in the IDS submitted on 10/28/2024.
Regarding claim 6, claim 12 of the reference patent teaches all the limitations of claim 6 as shown in the Table below.
16403245
US 12118056 B2
6. A computerized apparatus comprising:
12. A computerized memory apparatus comprising:
a memory;
a plurality of memory elements
a data interface configured to perform data communication with a processor apparatus;
a data interface configured to perform data communication with a processor apparatus;
control logic configured to, when operated:
control logic configured to, when operated:
receive one or more instructions for an input transformation from the processor apparatus;
receive one or more instructions for an input transformation from the processor apparatus;
cause configuration of a plurality of memory elements of the memory as a matrix multiplication unit based at least on the received one or more instructions;
cause configuration of the first bank of memory elements as a matrix multiplication unit (MMU) based at least on the received one or more instructions,
cause a memory sense component to convert an analog value associated with a memory element of
cause the memory sense component to convert a first analog value, associated with a memory element of the second bank of memory elements configured as a memory, into a first digital value based at least on the received one or more instructions;
based at least on the converted digital value, obtain an output result from the memory sense component.
based at least on the converted first digital value, obtain an output result from the memory sense component
7. The computerized apparatus of Claim 6, wherein the receipt of the one or more instructions comprises receipt of the one or more instructions from the processor apparatus.
12. receive one or more instructions for an input transformation from the processor apparatus;
8. The computerized apparatus of Claim 6, wherein the control logic is further configured to, when operated, configure respective impedance values for the plurality of memory elements.
13. The computerized memory apparatus of claim 12, wherein the control logic is further configured to, when operated, configure respective impedance values for the plurality of memory elements.
9. The computerized apparatus of Claim 8, wherein the one or more instructions for the input transformation comprise one or more opcodes for performance of at least a matrix transformation using the configured impedance values.
14. The computerized memory apparatus of claim 13, wherein the one or more instructions for the input transformation comprise one or more opcodes for performance of at least a matrix transformation via use of the configured impedance values.
10. The computerized apparatus of Claim 6, wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element from a lookup table, the analog value comprising a value associated with one of a voltage or a current.
15. The computerized memory apparatus of claim 12, wherein the control logic is further configured to, when operated, obtain the first analog value associated with the memory element from a lookup table (LUT), the first analog value comprising a value associated with one of a voltage or a current.
Claim 12 of the reference patent does not explicitly teach cause a memory sense component to convert an analog value associated with a memory element of the matrix multiplication unit into a digital value based at least on the received one or more instructions.
However, Chi discloses a memory sense component to convert an analog value associated with a memory element of a matrix multiplication unit into a digital value (Chi Figs. 4-5 and page 32 Sense Amplifier subsection, Benefits of Our Design subsection; page 32 Morphing Between Two Modes subsection; page 34 subsection E).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Claim 12 of the reference patent using Chi and configure the memory sense component to convert an analog value associated with a memory element of the matrix multiplication unit into a digital value based at least on the received one or more instructions in order to implement a system for performing matrix-vector multiplication where the output of the matrix-vector multiplication is read by the memory sense component and converted to a digital value (Chi Figs. 4-5 and page 32 Morphing Between Two Modes subsection).
Therefore, the combination of Claim 12 of the reference patent as modified in view of Chi teaches cause a memory sense component to convert an analog value associated with a memory element of the matrix multiplication unit into a digital value based at least on the received one or more instructions.
Regarding claims 7-10, claims 12-15 of the reference patent anticipates claims 7-10 respectively as shown in the table above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chi.
Regarding claim 1, Chi teaches
a processor coupled to a non-transitory computer readable medium (Chi Fig. 3C processor – CPU; non-transitory computer readable medium – ReRAM);
wherein the non-transitory computer readable medium comprises one or more instructions which, when executed by the processor, cause the processor to (Chi Fig. 7 and page 32 PRIME Controller subsection “the PRIME controller that decodes instructions and provides control signals to all the peripheral circuits in the FF subarrays”):
write a matrix transformation opcode and a matrix transformation operand to the non-transitory computer readable medium (Chi Fig. 7 and page 32 PRIME Controller subsection; matrix transformation opcode – NN computation instruction; matrix transformation operand – weights or input vector; section II.B “The input data
a
i
is represented by analog input voltages on the wordlines. The synaptic weights
w
i
,
j
are programmed into the cell conductances in the crossbar array”; page 32 Morphing Between Two Modes subsection “in computation mode, the FF subarray fetches the input data of the NN from the Buffer subarray into the latch of the wordline decoder and driver”);
wherein the matrix transformation opcode causes the non-transitory computer readable medium to operate an array of memory cells as a matrix structure (Chi section II.B “The input data
a
i
is represented by analog input voltages on the wordlines. The synaptic weights
w
i
,
j
are programmed into the cell conductances in the crossbar array. Then the current flowing to the end of each bitline is viewed as the result of the matrix-vector multiplication”; page 32 Morphing Between Two Modes subsection; array of memory cells – FF subarray);
wherein the matrix transformation operand modifies one or more analog values of the matrix structure (Chi section II.B “Then the current flowing to the end of each bitline is viewed as the result of the matrix-vector multiplication”); and
read a matrix transformation result from the matrix structure (Chi section II.B “sensing the current on each bitline”; page 31 Sense Amplifier subsection; page 32 Morphing Between Two Modes subsection; matrix transformation result – output of the sense amplifiers).
Regarding claim 4, Chi teaches all the limitations of claim 1 as stated above. Further, Chi teaches wherein the matrix transformation opcode causes the non-transitory computer readable medium to operate another array of memory cells as another matrix structure (Chi page 29 left col bottom “ Also, a sigmoid unit as well as a subtraction unit is required, since matrices with positive and negative weights are implemented as two separated crossbar arrays”; page 31 left col top “we employ two crossbar arrays store positive and negative weights, respectively, and allow them to share the same input port”; Figs. 4-5; another array of memory cells – another FF/crossbar subarray); and wherein the matrix transformation result associated with the matrix structure and another matrix transformation result associated with the another matrix structure are logically combined (Chi Fig. 5 and page 32 left col Morphing Between Two Modes subsection “After the computation in the crossbar arrays that store positive and negative weights, their output signals are fed into the subtraction unit, and then the difference signal goes into the sigmoid unit”; page 34 Implementing NN Algorithms subsection “A subtraction unit (as shown in Figure 4 B ) is used to subtract the result of the negative part from that of the positive part”).
Regarding claim 6, Chi teaches
a memory (Chi Figs. 3C and 4 and section III subsection A; memory – FF subarray);
a data interface configured to perform data communication with a processor apparatus (Chi Fig. 3A; data interface – system bus between the CPU and ReRAM; processor apparatus – CPU);
control logic configured to, when operated (Chi Fig. A and page 32 right column subsection C; control logic – controller):
receive one or more instructions for an input transformation from the processor apparatus (Chi Fig. 7 and page 32 PRIME Controller subsection “the PRIME controller that decodes instructions and provides control signals to all the peripheral circuits in the FF subarrays”; page 34 left column subsection E; input transformation – NN computation or matrix-vector multiplication);
cause configuration of a plurality of memory elements of the memory as a matrix multiplication unit based at least on the received one or more instructions (Chi Figs. 2B, 5 and page 32 PRIME Controller subsection; page 32 Morphing Between Two Modes subsection; page 29 subsection B; plurality of memory elements – memory cells/memristors);
cause a memory sense component to convert an analog value associated with a memory element of the matrix multiplication unit into a digital value based at least on the received one or more instructions (Chi Fig. 4 page 31 Sense Amplifier subsection and Benefits of Our Design subsection; page 32 Morphing Between Two Modes subsection “The analog output is converted to digital signal by the SA” memory sense component – sense amplifiers); and
based at least on the converted digital value, obtain an output result from the memory sense component (Chi Figs. 4-5 page 31 Sense Amplifier subsection and Benefits of Our Design subsection; page 32 Morphing Between Two Modes subsection).
Regarding claim 7, Chi teaches all the limitations of claim 6 as stated above. Further, Chi teaches wherein the receipt of the one or more instructions comprises receipt of the one or more instructions from the processor apparatus (Chi Figs. 3A and 7 and section IV subsection A).
Regarding claim 8, Chi teaches all the limitations of claim 6 as stated above. Further, Chi teaches wherein the control logic is further configured to, when operated, configure respective impedance values for the plurality of memory elements (Chi Figs. 1-2 and section II subsection A-B).
Regarding claim 9, Chi teaches all the limitations of claim 8 as stated above. Further, Chi teaches wherein the one or more instructions for the input transformation comprise one or more opcodes for performance of at least a matrix transformation using the configured impedance values (Chi Figs. 2B and 7; section II subsection B; page 32 subsection C; page 32 subsection E).
Regarding claim 11, Chi teaches a memory device comprising (Chi Figs. 3C, and 4):
an array of memory cells (Chi Figs. 3C, and 4; section III.A; array of memory cells – FF subarray); and
control logic stored in the memory device and configured to (Chi Fig. 4 and section III.C; control logic - controller):
operate the array of memory cells as a memory (Chi section III second paragraph “In memory mode, the FF subarrays serve as conventional memory; in computation mode, they can execute NN computation. There is a PRIME controller to control the operation and the reconfiguration of the FF subarrays”; section III.C “A key role of the controller is to configure the FF subarrays in memory and computation modes”; memory – memory mode), and
operate the array of memory cells as a matrix fabric (Chi section III second paragraph “In memory mode, the FF subarrays serve as conventional memory; in computation mode, they can execute NN computation. There is a PRIME controller to control the operation and the reconfiguration of the FF subarrays”; section III.C “A key role of the controller is to configure the FF subarrays in memory and computation modes”; matrix fabric - computation mode).
Regarding claim 12, Chi teaches all the limitations of claim 11 as stated above. Further, Chi teaches wherein the same memory cells are used while the array of memory cells is operated as the memory and while the array of memory cells is operated as a matrix fabric (Chi Figs. 4-5 and section III second paragraph “In memory mode, the FF subarrays serve as conventional memory; in computation mode, they can execute NN computation. There is a PRIME controller to control the operation and the reconfiguration of the FF subarrays”; section III.A Morphing Between Two Modes subsection “Figure 5 shows two FF subarrays that are configured into computation and memory modes, respectively”).
Regarding claim 13, Chi teaches all the limitations of claim 11 as stated above. Further, Chi teaches further comprising memory array circuitry, the memory array circuitry configured to operate as a row decoder and column decoder while the array of memory cells is operated as the memory, and the memory array circuitry configured to operate as a row driver and a matrix multiplication unit while the array of memory cells is operated as the matrix fabric (Chi Fig. 4 and section III.A decoder and driver and column multiplexer subsections; memory array circuitry – word line decoder/driver and column multiplexer).
Regarding claim 14, Chi teaches all the limitations of claim 11 as stated above. Further, Chi teaches wherein while the array of memory cells is operated as the matrix fabric, all row and column terminals of the array of memory cells are active (Chi section III.A Decoder and Driver subsection “NN computation requires that all input data are simultaneously fed into the corresponding wordline”; Fig. 2B and section II.B second paragraph).
Regarding claim 15, Chi teaches all the limitations of claim 11 as stated above. Further, Chi teaches wherein while the array of memory cells is operated as the memory, only a subset of all of the row and column terminals of the array of memory cells are active at a given time (Chi Figs. 4, 5B conventional memory operation).
Regarding claim 16, Chi teaches
a plurality of arrays of memory cells (Chi Figs. 3C and 4; plurality of arrays of memory cells – FF subarray in each bank; section IV.B Bank-level Parallelism and Data Placement subsection “PRIME contains 64 NPUs in total (8 banks × 8 chips) so that 64 images can be processed in parallel”), wherein:
the plurality of arrays of memory cells comprises a first bank of arrays of the plurality of arrays of memory cells configured as a memory (Chi section III second paragraph “In memory mode, the FF subarrays serve as conventional memory; in computation mode, they can execute NN computation. There is a PRIME controller to control the operation and the reconfiguration of the FF subarrays”; section III.C “A key role of the controller is to configure the FF subarrays in memory and computation modes”; first bank of arrays – FF subarrays configured in memory mode), and
the plurality of arrays of memory cells comprises a second bank of arrays of the plurality of arrays of memory cells configured as a matrix fabric (Chi section III second paragraph “In memory mode, the FF subarrays serve as conventional memory; in computation mode, they can execute NN computation. There is a PRIME controller to control the operation and the reconfiguration of the FF subarrays”; section III.C “A key role of the controller is to configure the FF subarrays in memory and computation modes”; second bank of arrays - FF subarrays configured in computation mode), and
the plurality of arrays of memory cells are dynamically configurable to be partitioned in either of the first bank of arrays or the second bank of arrays (Chi page 28 left column first paragraph “Our circuit, architecture, and software interface designs allow these ReRAM arrays to dynamically reconfigure between memory and accelerators, and also to represent various NNs”; Fig. 5 and page 32 left column Morphing Between Two Modes subsection; section III.C).
Regarding claim 17, Chi teaches all the limitations of claim 16 as stated above. Further, Chi teaches wherein the memory cells of the plurality of arrays of memory cells comprise resistive random access memory cells (Chi Figs. 1-2, 3C, 4 and section II.A).
Regarding claim 18, Chi teaches all the limitations of claim 16 as stated above. Further, Chi teaches wherein the first bank of arrays are configurable as the memory at the same time as the second bank of arrays being configurable as the matrix fabric (Chi Fig. 5 and section III.A “The design goal for FF subarray is to support both storage and computation with a minimum area overhead … We employ a multiplexer to switch the voltage driver between memory and computation modes … Figure 5 shows two FF subarrays that are configured into computation and memory modes, respectively”).
Regarding claim 19, Chi teaches all the limitations of claim 16 as stated above. Further, Chi teaches wherein each memory cell of the plurality of arrays of memory cells are configured to store a digital value as an analog value in an analog medium (Chi Figs. 1-2 and section II.A “a ReRAM cell can be switched between a high resistance state (HRS) and a low resistance state (LRS), which are used to represent the logic “0” and “1”, respectively. Figure 1(b) shows the I-V characteristics of a typical bipolar ReRAM cell. Switching a cell from HRS (logic “0”) to LRS (logic “1”) is a SET operation, and the reverse process is a RESET operation”), and wherein the device further comprises a memory sense component configured to read the analog value of a first memory cell as a first digital value (Chi Fig. 4 and section III.A Sense Amplifier subsection; Benefits of Our Design subsection; memory sense component – sense amplifiers).
Regarding claim 20, Chi teaches all the limitations of claim 19 as stated above. Further, Chi teaches wherein the memory sense component is configured to convert the analog value of the first memory cell into a second digital value in accordance with a matrix transformation opcode and a matrix transformation operand (Chi Figs. 4 and 7 and section III.A Sense Amplifier subsection; Benefits of Our Design subsection; matrix transformation opcode – neural network program instructions; matrix transformation operand – inputs or weights; section II.B).
Claims 6-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gupta et al. (US 20190205741 A1), hereinafter Gupta. Gupta is cited in the IDS submitted on 10/28/2024.
Regarding claim 6, Gupta teaches
a memory (Gupta Figs. 1-5 and 9 and paragraphs [0063, 0094] memory – VMM engine);
a data interface configured to perform data communication with a processor apparatus (Gupta Fig. 9 and paragraph [0087] data interface – system bus; processor apparatus – host processor);
control logic configured to, when operated (Gupta Fig. 9 and paragraph [0087] control logic – controller):
receive one or more instructions for an input transformation from the processor apparatus (Gupta Fig. 9 and paragraphs [0021,0026, 0030, 0087-0088, 0111] an input transformation – multiplication or convolution);
cause configuration of a plurality of memory elements of the memory as a matrix multiplication unit based at least on the received one or more instructions (Gupta Figs. 2-3, 5 and paragraphs [0050, 0063, 0094] plurality of memory elements – memory cells/memristors);
cause a memory sense component to convert an analog value associated with a memory element of the matrix multiplication unit into a digital value based at least on the received one or more instructions (Gupta Figs. 2, 4 and 5 and paragraphs [0018, 0022-0023] “the readout circuit may be further configured to detect currents at a plurality of nodes of the memristor network, where the output signal is a function of the currents. The readout circuit may further comprise an analog-to-digital converter (ADC) configured to output a digital value representing the output signal … The readout circuit may further include a transimpedence amplifier configured to convert the output current to a voltage value, the output signal including the voltage value”; paragraphs [0064, 0071] memory sense component – readout circuitry); and
based at least on the converted digital value, obtain an output result from the memory sense component (Gupta Figs. 3-4 and paragraphs [0022, 0024, 0071, 0106,0119]).
Regarding claim 7, Gupta teaches all the limitations of claim 6 as stated above. Further, Gupta teaches wherein the receipt of the one or more instructions comprises receipt of the one or more instructions from the processor apparatus (Gupta Fig. 9 and paragraphs [0087-0088]).
Regarding claim 8, Gupta teaches all the limitations of claim 6 as stated above. Further, Gupta teaches wherein the control logic is further configured to, when operated, configure respective impedance values for the plurality of memory elements (Gupta paragraphs [0090, 0093-0094]).
Regarding claim 9, Gupta teaches all the limitations of claim 8 as stated above. Further, Gupta teaches wherein the one or more instructions for the input transformation comprise one or more opcodes for performance of at least a matrix transformation using the configured impedance values (Gupta paragraphs [0094, 0106, 0111, 0117-0118]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Hu et al. (NPL – “Accelerating Discrete Fourier Transforms with Dot-product Engine”), hereinafter Hu.
Regarding claim 2, Chi teaches all the limitations of claim 1 as stated above.
Chi does not explicitly teach wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values.
However, on the same field of endeavor, Hu discloses capturing image data comprising one or more captured color values; and performing a matrix transformation using the captured image data as a matrix transformation operand and wherein a matrix transformation result comprises one or more shifted color values (Hu page 4 section V subsection A-B and Figs. 7-9).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chi using Hu and configure the non-transitory computer readable medium to include one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values in order to implement a system for performing DFT and/or DCT (Hu section IV and V).
Therefore, the combination of Chi as modified in view of Hu teaches wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: capture image data comprising one or more captured color values; and wherein the matrix transformation operand comprises the one or more captured color values and the matrix transformation result comprises one or more shifted color values.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chi as applied to claim 1 above, and further in view of Strachan et al. (US 10,621,267 B2), hereinafter Strachan. Strachan is cited in the IDS submitted on 10/28/2024.
Regarding claim 3, Chi teaches all the limitations of claim 1 as stated above. Further, Chi teaches wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: receive (Chi page 28 left column first paragraph, page 35 right column bottom).
Chi does not explicitly teach wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: receive video data comprising one or more image blocks; wherein the matrix transformation operand comprises the one or more image blocks and the matrix transformation result comprises one or more frequency domain image coefficients; and wherein the one or more analog values of the matrix structure accumulate the one or more frequency domain image coefficients from video data over time.
However, on the same field of endeavor, Strachan discloses receiving video data and performing matrix transformation the using video data as a matrix transformation operand to generate a matrix transformation result comprising one or more frequency domain image coefficients; and wherein one or more analog values of a matrix structure accumulate the one or more frequency domain image coefficients from video data over time (Strachan Figs. 1-3 and col 1 line 46 to col 2 line 20).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chi using Strachan and configure the non-transitory computer readable medium to include one or more instructions which, when executed by the processor, cause the processor to: receive video data comprising one or more image blocks; wherein the matrix transformation operand comprises the one or more image blocks and the matrix transformation result comprises one or more frequency domain image coefficients; and wherein the one or more analog values of the matrix structure accumulate the one or more frequency domain image coefficients from video data over time in order to implement a system for performing DFT which normally takes video data as an input (Strachan col 1 lines 46-60).
Therefore, the combination of Chi as modified in view of Strachan teaches wherein the non-transitory computer readable medium further comprises one or more instructions which, when executed by the processor, cause the processor to: receive video data comprising one or more image blocks; wherein the matrix transformation operand comprises the one or more image blocks and the matrix transformation result comprises one or more frequency domain image coefficients; and wherein the one or more analog values of the matrix structure accumulate the one or more frequency domain image coefficients from video data over time.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chi as applied to claim 1 above, and further in view of Hongxia et al. (NPL – “High Performance Algorithm for Twiddle Factor of Variable-size FFT Processor and Its Implementation”), hereinafter Hongxia. Hongxia is cited in the IDS submitted on 10/28/2024.
Regarding claim 5, Chi teaches all the limitations of claim 1 as stated above.
Chi does not explicitly teach wherein the one or more analog values of the matrix structure are stored within a look-up-table data structure.
However, on the same field of endeavor, Hongxia discloses storing values for a matrix transformation in a look-up-table data structure (Hongxia page 1078 section I first paragraph).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chi using Hongxia and configure the system to include a look-up-table data structure for storing a mapping table of the matrix operand to conductance values of each cell of the crossbar array for a more efficient programming of the crossbar array and in order implement a system for performing FFT (Hongxia page 1078 section I first paragraph).
Therefore, the combination of Chi as modified in view of Hongxia teaches wherein the one or more analog values of the matrix structure are stored within a look-up-table data structure.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gupta as applied to claim 6 above, and further in view of Hongxia.
Regarding claim 10, Gupta teaches all the limitations of claim 6 as stated above. Further, Gupta teaches wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element (Gupta paragraphs [0064, 0067]).
Gupta does not explicitly teach wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element from a lookup table, the analog value comprising a value associated with one of a voltage or a current.
However, on the same field of endeavor, Hongxia discloses storing values for a matrix transformation in a look-up-table data structure (Hongxia page 1078 section I first paragraph).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gupta using Hongxia and configure the system to obtain the analog value associated with the memory element from a lookup table a more efficient programming of the crossbar array and in order implement a system for performing FFT (Hongxia page 1078 section I first paragraph).
Therefore, the combination of Gupta as modified in view of Hongxia teaches wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element from a lookup table, the analog value comprising a value associated with one of a voltage or a current.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chi as applied to claim 6 above, and further in view of Hongxia.
Regarding claim 10, Chi teaches all the limitations of claim 6 as stated above. Further, Chi teaches wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element (Chi Fig. 1B and page 28 section II subsection A “By applying an external voltage across it, a ReRAM cell can be switched between a high resistance state (HRS) and a low resistance state (LRS), which are used to represent the logic “0” and “1”, respectively”)
Chi does not explicitly teach wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element from a lookup table, the analog value comprising a value associated with one of a voltage or a current.
However, on the same field of endeavor, Hongxia discloses storing values for a matrix transformation in a look-up-table data structure (Hongxia page 1078 section I first paragraph).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Chi using Hongxia and configure the system to obtain the analog value associated with the memory element from a lookup table a more efficient programming of the crossbar array and in order implement a system for performing FFT (Hongxia page 1078 section I first paragraph).
Therefore, the combination of Chi as modified in view of Hongxia teaches wherein the control logic is further configured to, when operated, obtain the analog value associated with the memory element from a lookup table, the analog value comprising a value associated with one of a voltage or a current.
Conclusion
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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