DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 15 are objected to because of the following informalities: “substrate , wherein” in line 3 of claim 1 and “the substrate ;” in line 3 of claim 15 should be changed to “substrate, wherein” and “the substrate;”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schuele et al. (US 2008/0057649 A1; hereinafter “Schuele”).
Regarding claim 1, referring to Fig. 7 and related text, Schuele teaches a thin film transistor substrate comprising: a substrate (502) (paragraph 31); a buffer layer (504) having a buffer groove (506) disposed on the substrate, wherein the buffer groove includes an inclined surface (510 having an inclined surface with an angle of about 45 degrees) (paragraphs 31-36); an active layer (512) disposed on the buffer layer (paragraph 31); and a gate electrode (526) disposed on the active layer (paragraph 31), wherein the active layer is disposed to be stepped on the buffer groove (Fig. 7), and one end of the gate electrode overlaps the inclined surface of the buffer groove (Fig. 7).
Regarding claim 2, Schuele teaches wherein one end of the gate electrode overlaps a portion of the active layer disposed on the inclined surface of the buffer groove (Fig. 7).
Regarding claim 4, Schuele teaches further comprising: a gate insulating layer (514) disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps the buffer groove, and one end of the gate insulating layer is disposed between one end of the active layer and one end of the gate electrode (Fig. 7 and paragraph 31).
Regarding claim 5, Schuele teaches wherein the gate insulating layer has a first width (a width of 514), the gate electrode has a second width (a width of 526), the active layer has a first length (a horizontal length of 512), and the first width of the gate insulating layer is larger than the second width of the gate electrode and smaller than the first length of the active layer (Fig. 7).
Regarding claim 6, Schuele teaches wherein the active layer includes a channel part (528), a connection part (526) disposed on one side of the channel part, and a diffusion part (518) disposed between the channel part and the connection part, and the channel part includes a first region (a center portion of 528) in contact with a bottom surface of the buffer groove (508) and a second region (an edge portion of 528) in contact with the inclined surface of the buffer groove (Fig. 7 and paragraphs 32-34).
Regarding claim 7, Schuele teaches wherein one end of the second region of the channel part is disposed in the inclined surface (Fig. 7).
Regarding claim 8, Schuele teaches wherein one end of the second region of the channel part corresponds to one end of the gate electrode (Fig. 7).
Regarding claim 9, Schuele teaches wherein one end of the diffusion part is disposed on the inclined surface of the buffer groove (Fig. 7).
Regarding claim 10, Schuele teaches wherein another end of the diffusion part corresponds to one end of the gate electrode (Fig. 7).
Regarding claim 11, Schuele teaches wherein another end of the diffusion part is disposed between one end of the gate electrode and one end of the active layer (Fig. 7).
Regarding claim 12, Schuele teaches wherein the active layer includes a channel part (528), a connection part (526) disposed on one side of the channel part, and a diffusion part (518) disposed between the channel part and the connection part, one end of the channel part is disposed on a bottom surface of the buffer groove (508), and one end of the diffusion part is disposed on the inclined surface of the buffer groove, and one end of the channel part and one end of the diffusion part are in contact with each other at a boundary between the bottom surface of the buffer groove and the inclined surface of the buffer groove (Fig. 7).
Regarding claim 13, Schuele teaches wherein the buffer groove further includes a bottom surface (508) connected to the inclined surface (Fig. 7 and paragraph 31), and an angle formed between the bottom surface and the inclined surface is equal to 30 degrees or more and equal to 45 degrees or less (paragraph 36).
Regarding claim 15, referring to Fig. 7 and related text, Schuele Park teaches a thin film transistor substrate comprising: a substrate (502) (paragraph 31); a buffer layer (504) having a buffer groove (506) disposed on the substrate (paragraphs 31-36); an active layer (512) disposed on the buffer layer (paragraph 31); and a gate electrode (526) disposed on the active layer (paragraph 31), wherein the buffer groove includes a bottom surface (508) and an inclined surface (510 having an inclined surface with an angle of about 45 degrees) connected to the bottom surface (Fig. 7 and paragraph 36), the active layer includes a channel part (528), a connection part (526) disposed on one side of the channel part, and a diffusion part (518) disposed between the channel part and the connection part, and the channel part overlaps the bottom surface and the inclined surface (Fig. 7), and one end of the channel part is disposed on the inclined surface of the buffer groove (Fig. 7).
Regarding claim 16, Schuele teaches wherein a width of the bottom surface of the buffer groove (a width of 508) is smaller than a width of the gate electrode (a largest width of 526), and a width of the entire bottom surface and inclined surface of the buffer groove is larger than the width of the gate electrode (Fig. 7).
Regarding claim 17, Schuele teaches further comprising: a gate insulating layer (512) disposed between the active layer and the gate electrode, wherein an entire area of the diffusion part overlaps the gate insulating layer (Fig. 7 and paragraph 31).
Regarding claim 18, Schuele teaches wherein a portion of the diffusion part does not overlap the gate electrode (Fig. 7, an outermost portion of 518 at 522 does not overlap 526).
Regarding claim 19, Schuele teaches wherein one end of the channel part corresponds to one end of the gate electrode (Fig. 7).
Regarding claim 20, referring to Fig. 7 and related text, Schuele teaches a display device including a thin film transistor substrate comprising: a substrate (502) (paragraph 31); a buffer layer (504) disposed on the substrate and having a buffer groove (506) (paragraphs 31-36); an active layer (512) disposed on the buffer layer (paragraph 31); and a gate electrode (526) disposed on the active layer (paragraph 31), wherein the active layer is disposed to be stepped on the buffer groove (Fig. 7), and one end of the gate electrode overlaps an inclined surface (510 having an inclined surface with an angle of about 45 degrees) disposed in the buffer groove (Fig. 7 and paragraph 36). Furthermore, it is noted that the term “a display device” in the preamble of claim 20 does not limit the scope of the claim for completeness and has not been given patentable weight. See MPEP 2111.02 Effect of Preamble.
Claims 1-3, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0263017 A1; hereinafter “Park”).
Regarding claim 1, referring to Figs. 1-2, Park teaches a thin film transistor substrate comprising: a substrate (SUB) (paragraphs 54-60); a buffer layer (BUF) having a buffer groove (BUF having a trench area where ACT1 is formed therein) disposed on the substrate, wherein the buffer groove includes an inclined surface (an inclined surface of the trench area of BUF where ACT1 is formed therein) (paragraph 63); an active layer (ACT1) disposed on the buffer layer (paragraphs 64-67); and a gate electrode (GAT1) disposed on the active layer, wherein the active layer is disposed to be stepped on the buffer groove (Fig. 2), and one end of the gate electrode overlaps the inclined surface of the buffer groove (Fig. 2).
Regarding claim 2, Park teaches wherein one end of the gate electrode overlaps a portion of the active layer disposed on the inclined surface of the buffer groove (Fig. 2).
Regarding claim 3, Park teaches further comprising: a gate insulating layer (GI) disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps the buffer groove, and one end of the gate insulating layer corresponds to one end of the gate electrode (Fig. 2 and paragraph 68).
Regarding claim 15, referring to Figs. 1-2, Park teaches a thin film transistor substrate comprising: a substrate (SUB) (paragraphs 54-60); a buffer layer (BUF) having a buffer groove (BUF having a trench area where ACT1 is formed therein) disposed on the substrate (paragraph 63); an active layer (ACT1) disposed on the buffer layer (paragraphs 64-67); and a gate electrode (GAT1) disposed on the active layer, wherein the buffer groove includes a bottom surface and an inclined surface connected to the bottom surface (the trench area of BUF has a bottom surface and an inclined surface), the active layer includes a channel part (CH1 within the trench area), a connection part (SA1) disposed on one side of the channel part (a left-side of CH1), and a diffusion part (a portion of ACT1 at a boundary region between SA1 and CH1) disposed between the channel part and the connection part, and the channel part overlaps the bottom surface and the inclined surface (Fig. 2), and one end of the channel part is disposed on the inclined surface of the buffer groove (Fig. 2).
Regarding claim 20, referring to Figs. 1-2, Park teaches a display device including a thin film transistor substrate comprising: a substrate (SUB) (paragraphs 54-60); a buffer layer (BUF) disposed on the substrate and having a buffer groove (BUF having a trench area where ACT1 is formed therein) (paragraph 63); an active layer (ACT1) disposed on the buffer layer (paragraphs 64-67); and a gate electrode (GAT1) disposed on the active layer (paragraph 69), wherein the active layer is disposed to be stepped on the buffer groove (Fig. 2), and one end of the gate electrode overlaps an inclined surface (an inclined surface of the trench area of BUF where ACT1 is formed therein) disposed in the buffer groove (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Schuele.
Regarding claim 14, Schuele teaches wherein the buffer groove further includes a bottom surface (508) connected to the inclined surface, and a depth of the bottom surface of the buffer groove (a depth of 506) (Fig. 7 and paragraph 31).
While Schuele does not explicitly teach the depth of the bottom surface of the buffer groove to be equal to 1.41 μm or more and equal to 2 μm or less, it would have been obvious to one of ordinary skill in the art to adjust the depth of the trench 506 from Schuele in a desired range, including the depth equal to 1.41 μm or more and equal to 2 μm or less as claimed, by a routine experimentation in order to obtain the workable and optimal depth range of the trench 506.It has held that discovering an optimum or workable ranges involves only routine skill in the art: Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Im et al. (US 2023/0215955 A1) teaches a display device including a thin film transistor substrate as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL WHALEN/Primary Examiner, Art Unit 2893
Prosecution Insights