DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0233463 A1) in view of Holst (US 2016/0358644 A1), further in view of Murakami (US 2015/0055418 A1).
As to claim 1, Lee teaches a pixel for a display (see at least figs. 4-5), the pixel comprising: a latch circuit powered by an upper rail voltage and a lower rail voltage; a first bit line coupled to a first output of the latch circuit by a first transistor; a second bit line coupled to a second output of the latch circuit by a second transistor (see Lee at least figs. 4-5: a pixel with a 4T SRAM latch powered by Vdd and GND: see [0050] “The embedded pixel memory unit of the pixel circuit…may include 4T SRAM cells”; First and second transistors connected to bit lines and word line: see [0052] “The first transistor M1…drain terminal connected to a bit line BL…gate terminal connected to a word line WL”; see [0053] “The second transistor M2…drain terminal connected to a high potential supply source Vdd…gate terminal connected to a second node Q′…source terminal connected to the first node Q”).
Lee does not directly teach the first transistor controlled in a ON condition during a write operation by word line voltage on a word line and a LOW bit line voltage on the first bit line; the second transistor controlled in an OFF condition during the write operation by the word line voltage and a HIGH bit line voltage on the second bit line; and a word line regulator configured to receive the HIGH bit line voltage as a reference input and control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation.
Holst teaches the first transistor controlled in a ON condition during a write operation by word line voltage on a word line and a LOW bit line voltage on the first bit line; the second transistor controlled in an OFF condition during the write operation by the word line voltage and a HIGH bit line voltage on the second bit line (see at least figs. 3-4A-C: [0038] “BL and LBL may be driven to complementary values…which may be stored at nodes N₁ and N₂ of the memory cell 302”; Nacc transistors connecting bit lines to memory nodes: [0036] “When performing read or write operations, Nacc transistor 304 connects the bit line BL…Similarly, Nacc transistor 306 connects the complementary bit line LBL” – note driving complementary bit lines inherently results in one bit line LOW and the other HIGH during write, causing the corresponding access transistor to conduct while the complementary access transistor remains non-conductive. This teaches the claimed ON/OFF write relationship).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Holst’s complementary write scheme with Lee’s pixel latch because complementary bit line driving is a well-established SRAM write technique that improves write reliability and noise margin. Applying a known write technique to a known latch yields predictable results. Further rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
Lee and Holst do not directly teach a word line regulator configured to receive the HIGH bit line voltage as a reference input and control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation.
Murakami teaches a word line regulator configured to receive the HIGH bit line voltage as a reference input and control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation (see at least [0053]-[0054] “ … the regulator 210 is controlled … to output the voltage VCLMP of VREF+Vth.”; “[0057] … the voltage VCLMP is supplied … to the gate of each of the charge transfer transistors TG … Accordingly … deviation … is suppressed.”. Therefore, Murakami teaches a regulator (210) that receives a reference voltage (VREF) and outputs a gate voltage equal to the reference voltage plus a threshold voltage (VREF + Vth), which is supplied to a transistor gate. Supplying a gate voltage equal to the reference voltage plus a threshold voltage causes the gate voltage to be maintained approximately one threshold voltage above the reference voltage. Under the broadest reasonable interpretation, this corresponds to the claimed configuration in which a word line regulator receives a HIGH bit line voltage as a reference input and controls the word line voltage to float above the HIGH bit line voltage by approximately a threshold voltage. Holst teaches that during a write operation complementary bit lines are driven to opposite logic levels such that one bit line is LOW and the complementary bit line is HIGH (see at least [0038] “BL and LBL may be driven to complementary values… which may be stored at nodes N₁ and N₂”). When the word line is asserted, the access transistor coupled to the LOW bit line conducts while the complementary access transistor coupled to the HIGH bit line remains non-conductive. Thus, Holst teaches that the second transistor connected to the HIGH bit line is in an OFF condition during the write operation. When Murakami’s regulator-controlled gate biasing (VREF + Vth) is applied to the word line of the Lee/Holst pixel memory structure, the HIGH bit line corresponds to the high-potential reference present during the write operation. The regulator therefore sets the word line voltage relative to that reference such that the word line voltage floats above the HIGH bit line voltage by approximately a threshold voltage. Biasing the word line in this manner controls the effective gate-to-source bias of the access transistors and thereby limits current conduction through the transistor that remains OFF during the write operation (i.e., the second transistor connected to the HIGH bit line).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply Murakami’s known reference-plus-threshold gate biasing technique to the Lee/Holst SRAM pixel structure in order to control current conduction through the access transistor intended to remain OFF during the write operation. Controlling leakage and undesired current conduction in access transistors is a known design consideration in memory circuitry, as such leakage can degrade write margin and circuit stability. Applying Murakami’s biasing technique to the Lee/Holst structure therefore represents the predictable use of a known circuit biasing method to improve leakage control and write reliability without altering the fundamental operation of Lee’s pixel memory circuit.
As to claim 15, Lee teaches a method for writing to a memory cell of a pixel array (see at least figs. 4-5), the method comprising:
driving a first bit line to a lower rail voltage of the memory cell (see at least figs. 4-5 and [0057] “a voltage is applied to the word line WL so that the transistor M1 is turned on. A logic low voltage corresponding to the data ‘0’ is applied to the bit line BL. The logic low voltage is applied to the node Q…”), the first bit line coupled to a first output of a latch circuit via a first transistor (see at least figs. 4-5 and [0052] “The first transistor M1 may be an N-type transistor and may have a drain terminal connected to a bit line BL for transmitting data, a gate terminal connected to a word line WL, and a source terminal connected to a first node.”), the first transistor coupled at a first gate terminal to a word line (see at least figs. 4-5, [0052] “a gate terminal connected to a word line WL.” and [0057] “a voltage is applied to the word line WL so that the transistor M1 is turned on.”);
coupling the word line to the word line regulator so that the first transistor is biased in an ON condition to couple the lower rail voltage to the first output of the latch circuit (see at least figs. 4-5 and [0057] “a voltage is applied to the word line WL so that the transistor M1 is turned on. A logic low voltage corresponding to the data ‘0’ is applied to the bit line BL. The logic low voltage is applied to the node Q, the transistor M3 is turned on, and the transistor M4 is turned off…”);
configuring the latch circuit to output an upper rail voltage of the memory cell to the second output based on the first output being coupled to the lower rail voltage (see at least figs. 4-5 and [0057] “The logic low voltage is applied to the node Q, the transistor M3 is turned on, and the transistor M4 is turned off, thereby forming a logic high voltage in the second node Q′. The second transistor M2 is turned off by the logic high voltage of the second node Q′.”).
Lee does not directly teach driving a second bit line to a HIGH bit line voltage, the second bit line coupled to a second output of the latch circuit via a second transistor, the second transistor coupled at a second gate terminal to the word line; receiving the HIGH bit line voltage at a word line regulator coupled to the pixel array; controlling the word line to float above the HIGH bit line voltage by a threshold voltage using the word line regulator; and the second transistor is biased to limit a current at the second output of the latch circuit.
Holst teaches driving a second bit line to a HIGH bit line voltage, the second bit line coupled to a second output of the latch circuit via a second transistor, the second transistor coupled at a second gate terminal to the word line (see at least figs. 4-5: bit lines BL, LBL, second transistor 306, word line WL; and [0035] “… the bit cell 200 may be connected with a word line WL and between a pair of bit line BL/LBL running perpendicular to the word line WL. The bit cell 200 may comprise a memory cell 302 connected between the pair of bit line BL/LBL by an n-channel field-effect transistor (NFET) access (Nacc) transistor 304 and an Nacc transistor 306.”; [0036] “… Nacc transistor 304 connects the bit line BL to the memory cell 302 when a word line WL is activated. Similarly, Nacc transistor 306 connects the complementary bit line LBL when the word line WL is activated.”; [0037] “… the memory cell 302 of bit cell 200 may be represented as two cross-coupled inverters capable of storing data for reading and writing.”; and [0038] “… when a WL is logically high (i.e., WL=1) the Nacc transistors 304 and 306 may be turned on and data (i.e., voltage) applied to the pair of bit lines (i.e., BL and LBL) may be written into and stored at nodes N₁ and N₂ of the memory cell 302. For example, during a write operation, BL and LBL may be driven to complementary values by the column selection circuitry (e.g., driven to a high (VCC) and low (VSS) supply voltage, respectively), which may be stored at nodes N₁ and N₂…”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s SRAM structure to include the dual complementary bit lines of Holst. Dual-bit-line configurations were a well-known and routine feature of SRAM design for improving write margin and stability, as noted by Holst [0041]. Further rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
Lee and Holst do not directly teach receiving the HIGH bit line voltage at a word line regulator coupled to the pixel array; controlling the word line to float above the HIGH bit line voltage by a threshold voltage using the word line regulator.
Murakami teaches receiving the HIGH bit line voltage at a word line regulator coupled to the pixel array; controlling the word line to float above the HIGH bit line voltage by a threshold voltage using the word line regulator; coupling the word line to the word line regulator so that the first transistor is biased in an ON condition to couple the lower rail voltage to the first output of the latch circuit and so that the second transistor is biased to limit a current at the second output of the latch circuit (see at least [0053]-[0054] “ … the regulator 210 is controlled … to output the voltage VCLMP of VREF+Vth.”; “[0057] … the voltage VCLMP is supplied … to the gate of each of the charge transfer transistors TG … Accordingly … deviation … is suppressed.”. Note, under the broadest reasonable interpretation, this corresponds to: receiving the HIGH bit line voltage at a word line regulator coupled to the pixel array and controlling the word line to float above the HIGH bit line voltage by a threshold voltage using the word line regulator. Applying Murakami’s regulator to the Lee/Holst memory cell results in a word line voltage approximately equal to VHIGH + Vth. Accordingly, the access transistor coupled to the LOW bit line is biased strongly ON, coupling the lower rail voltage to the first latch node as taught by Lee; and the access transistor coupled to the HIGH bit line experiences a gate-to-source voltage approximately equal to the threshold voltage (VGS ≈ Vth), thereby limiting current conduction at the second output of the latch circuit. Thus the combined teachings correspond to: coupling the word line to the word line regulator so that the first transistor is biased in an ON condition to couple the lower rail voltage to the first output of the latch circuit and so that the second transistor is biased to limit a current at the second output of the latch circuit).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply Murakami’s reference-plus-threshold gate biasing technique to the complementary bit-line latch structure of Lee in view of Holst in order to control current through the access transistors during a write operation. Controlling transistor gate bias relative to a reference node to limit unwanted current conduction is a known circuit design technique. Applying Murakami’s regulator-based bias to the Lee/Holst memory cell would predictably improve write stability by limiting current through the access transistor connected to the HIGH bit line without altering the fundamental operation of the memory cell.
As to claim 19, Lee teaches a pixel for a display (see at least figs. 4-5) comprising:
a word line (see at least fig. 4: WL);
a first bit line driven at a HIGH bit line voltage or a lower rail voltage (see at least fig. 4 and [0052], [0057] “The first transistor M1 … has a drain terminal connected to a bit line BL for transmitting data… A logic low voltage corresponding to the data ‘0’ is applied to the bit line BL.”);
a latch circuit configured to output an upper rail voltage or the lower rail voltage (see at least fig. 4 and [0049]-[0051] “The embedded pixel memory unit … may include 4T SRAM cells.”; [0057] “… The logic low voltage is applied to the node Q, the transistor M3 is turned on, and the transistor M4 is turned off, thereby forming a logic high voltage in the second node Q′.”);
a first transistor connected at a first drain terminal to the latch circuit, connected at a first source terminal to the first bit line, and connected at a first gate terminal to the word line (see at least fig. 4 and [0052] “The first transistor M1 may be an N-type transistor and may have a drain terminal connected to a bit line BL … a gate terminal connected to a word line WL, and a source terminal connected to a first node.”; [0057]: WL applied so M1 turns on and BL drives node Q).
Lee does not directly teach a second bit line driven at the lower rail voltage when the first bit line is driven at the HIGH bit line voltage and driven at the HIGH bit line voltage when the first bit line is driven at the lower rail voltage; a second transistor connected at a second drain terminal to the latch circuit, connected at a second source terminal to the second bit line, and connected at a second gate terminal to the word line; and a word line regulator configured to generate a word line voltage on the word line that floats above the HIGH bit line voltage by a reference voltage, the HIGH bit line voltage being less than the upper rail voltage.
Holst teaches a word line (see at least figs. 3, 4A-C: WL);
a first bit line driven at a HIGH bit line voltage or a lower rail voltage (see at least figs. 3, 4A-C, [0035], [0038]: “the bit cell 200 may be connected … between a pair of bit line BL/LBL …” and “BL and LBL may be driven to complementary values … (e.g., driven to a high (VCC) and low (VSS) supply voltage, respectively).”);
a second bit line driven at the lower rail voltage when the first bit line is driven at the HIGH bit line voltage and driven at the HIGH bit line voltage when the first bit line is driven at the lower rail voltage (see at least fig. 3, 4A-C, [0035], [0038] “a second bit line driven at the lower rail voltage when the first bit line is driven at the HIGH bit line voltage and driven at the HIGH bit line voltage when the first bit line is driven at the lower rail voltage;”;
a latch circuit configured to output an upper rail voltage or the lower rail voltage (see at least figs. 3, 4A-C, [0037], [0038] “the memory cell 302 … may be represented as two cross-coupled inverters capable of storing data for reading and writing.” and “BL and LBL may be driven to complementary values … which may be stored at nodes N₁ and N₂ of the memory cell 302.”);
a first transistor connected at a first drain terminal to the latch circuit, connected at a first source terminal to the first bit line, and connected at a first gate terminal to the word line (see at least figs. 3, 4A-C, [0035]-[0036] “The bit cell 200 may comprise a memory cell 302 connected between the pair of bit line BL/LBL by an n-channel field-effect transistor (NFET) access (Nacc) transistor 304 and an Nacc transistor 306.” and “Nacc transistor 304 connects the bit line BL to the memory cell 302 when a word line WL is activated.”);
a second transistor connected at a second drain terminal to the latch circuit, connected at a second source terminal to the second bit line, and connected at a second gate terminal to the word line (see at least figs. 3, 4A-C: two Nacc transistors (304 and 306) each connecting BL and LBL to the memory cell and gated by WL and [0036] “Nacc transistor 306 connects the complementary bit line LBL when the word line WL is activated.”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel memory unit of Lee, which uses a latch circuit (4T SRAM) and an access transistor coupled to a bit line, in view of Holst’s teaching of SRAM bit cells having a pair of complementary bit lines (BL/LBL) and dual access transistors gated by the same word line. Holst expressly teaches that BL and LBL are driven to complementary values during write operations and accessed through two transistors controlled by the word line (see Holst [0036]–[0038]). The motivation for this combination would be to improve stability and reliable data storage/read-out in the pixel latch by employing the well-known complementary bit-line structure, as Holst explains is standard for robust SRAM read/write operations (see Holst [0041]). Thus, one of ordinary skill would have reasonably combined Lee’s pixel SRAM circuit with Holst’s dual complementary bit-line configuration to achieve predictable improvements in read/write margin. Further rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
Lee and Holst do not directly teach a word line regulator configured to receive the HIGH bit line voltage as a reference input and control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation.
Murakami teaches a word line regulator configured to receive the HIGH bit line voltage as a reference input and control the word line voltage on the word line to float above the HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation (see at least [0053]-[0054] “ … the regulator 210 is controlled … to output the voltage VCLMP of VREF+Vth.”; “[0057] … the voltage VCLMP is supplied … to the gate of each of the charge transfer transistors TG … Accordingly … deviation … is suppressed.”. Therefore, Murakami teaches a regulator (210) that receives a reference voltage (VREF) and outputs a gate voltage equal to the reference voltage plus a threshold voltage (VREF + Vth), which is supplied to a transistor gate. Supplying a gate voltage equal to the reference voltage plus a threshold voltage causes the gate voltage to be maintained approximately one threshold voltage above the reference voltage. Under the broadest reasonable interpretation, this corresponds to the claimed configuration in which a word line regulator receives a HIGH bit line voltage as a reference input and controls the word line voltage to float above the HIGH bit line voltage by approximately a threshold voltage. Holst teaches that during a write operation complementary bit lines are driven to opposite logic levels such that one bit line is LOW and the complementary bit line is HIGH (see at least [0038] “BL and LBL may be driven to complementary values… which may be stored at nodes N₁ and N₂”). When the word line is asserted, the access transistor coupled to the LOW bit line conducts while the complementary access transistor coupled to the HIGH bit line remains non-conductive. Thus, Holst teaches that the second transistor connected to the HIGH bit line is in an OFF condition during the write operation. When Murakami’s regulator-controlled gate biasing (VREF + Vth) is applied to the word line of the Lee/Holst pixel memory structure, the HIGH bit line corresponds to the high-potential reference present during the write operation. The regulator therefore sets the word line voltage relative to that reference such that the word line voltage floats above the HIGH bit line voltage by approximately a threshold voltage. Biasing the word line in this manner controls the effective gate-to-source bias of the access transistors and thereby limits current conduction through the transistor that remains OFF during the write operation (i.e., the second transistor connected to the HIGH bit line).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply Murakami’s known reference-plus-threshold gate biasing technique to the Lee/Holst SRAM pixel structure in order to control current conduction through the access transistor intended to remain OFF during the write operation. Controlling leakage and undesired current conduction in access transistors is a known design consideration in memory circuitry, as such leakage can degrade write margin and circuit stability. Applying Murakami’s biasing technique to the Lee/Holst structure therefore represents the predictable use of a known circuit biasing method to improve leakage control and write reliability without altering the fundamental operation of Lee’s pixel memory circuit.
As to claim 2, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), wherein: the LOW bit line voltage is the lower rail voltage; and the latch circuit is configured to output the upper rail voltage to the second output based on the first output being coupled to the lower rail voltage (see Lee at least fig. 4: lower rail is GND, upper rail is Vdd and [0053] “The second transistor M2…source terminal connected to the first node Q”; and Holst at least fig. 3, 4A-C and [0038] “BL and LBL…may be stored at nodes N₁ and N₂”).
As to claim 3, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), wherein the write operation is a first write operation, and: the first transistor is controlled in the OFF condition during a second write operation the word line voltage on the word line and the HIGH bit line voltage on the first bit line; the second transistor is controlled in the ON condition during the second write operation by the word line voltage on the word line and the LOW bit line voltage on the second bit line (see Lee at least fig. 4: first and second transistors connected to bit lines and word line and [0052]-[0053]; Holst at least figs. 3, 4A-C: complementary bit line driving, which allows swapping of ON/OFF states and [0038] “BL and LBL…driven to complementary values”); and the word line regulator is configured to control the word line voltage on the word line to float above the HIGH bit line voltage on the first bit line by the threshold voltage to limit the current conducted by the first transistor in the OFF condition during the second write operation (see Murakami at least [0054]: floating voltage regulator above bit line by Vth).
As to claim 4, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), wherein: the HIGH bit line voltage is less than the upper rail voltage; and the LOW bit line voltage is equal to the lower rail voltage (see Lee at least fig. 4: Vdd and GND are upper/lower rails and [0050], [0053] and Holst at least fig. 3, 4A-C: : bit lines driven to VCC and VSS during write; may be set below Vdd and [0038] – note it would be obvious to one skilled in the art to reduce HIGH bit line voltage below Vdd to save power while maintaining write operation, standard design in SRAM/pixel circuits).
As to claim 5, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 4 (see above rejection), wherein the lower rail voltage is ground (see Lee at least fig. 4: lower rail in GND and [0050] and Holst at least figs. 3, 4A-C and [0038]).
As to claim 6, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 4 (see above rejection), wherein the HIGH bit line voltage being less than the upper rail voltage reduces a power consumed by a bit line capacitance of the second bit line (see Holst at least figs. 3, 4A-C and [0038] “[BL and LBL] may be driven to complementary values…VCC and VSS” – note it would be obvious to one skilled in the art to select HIGH bit line < Vdd to reduce charging/discharging power).
As to claim 7, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), wherein: the HIGH bit line voltage is 50 percent or less the upper rail voltage; and the threshold voltage separating the HIGH bit line voltage and the word line voltage is in a range between about 0.2 volts and about 0.9 volts (see Lee at least fig. 4: Vdd and GND; Holst at least figs. 3, 4A-C and [0038]: complementary bit line driving confirms voltages can be set below upper rail; Murakami at least [0054]: regulator with VCLMP = VREF + Vth teaches threshold voltage control – note it would be obvious to one skilled in the art to set threshold within practical Vth range to control OFF transistor current).
As to claim 8, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 7 (see above rejection), wherein the word line regulator includes: a reference voltage source configured to receive the HIGH bit line voltage and generate a reference voltage at a reference node, the reference voltage being the HIGH bit line voltage increased by the threshold voltage (see Lee at least fig. 4; Holst at least figs. 3, 4A-C; and Murakami at least [0054] “The regulator 210…controls the voltage VCLMP…so that the voltage of the node N5 is equal to the reference voltage VREF” – note it would be obvious to one skilled in the art to combine Murakami’s regulator with Lee and Holst pixel design to provide reference voltage for word line, as controlling the word line voltage relative to the HIGH bit line to limit OFF transistor current is common in memory design).
As to claim 9, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 8 (see above rejection), wherein the reference voltage source is a diode-connected transistor that is substantially matched in dimensions to the first transistor and the second transistor, the diode-connected transistor coupled between the HIGH bit line voltage and the reference node (see Lee at least figs. 4-5: pixel transistors and latch operation; Holst figs. 3, 4A-C: bit line connections and write/read operations; and Murakami at least [0054] “NMOS emulate transistor 220…connected between the power supply VDD and the node N5…The voltage VCLMP is supplied to the gate of the emulate transistor 220” – note it would be obvious to one skilled in the art to match dimensions of the reference transistor to first and second transistors to ensure similar current/threshold characteristics which is common practice in voltage regulators).
As to claim 10, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 8 (see above rejection), wherein the word line regulator includes a mirror circuit to transmit the reference voltage from the reference node to an output (see Murakami at least [0029] “The constant voltage output element includes a current mirror circuit that generates the reference voltage according to the selected current value”).
As to claim 11, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 10 (see above rejection), wherein the mirror circuit includes: a reference transistor coupled at a first source terminal to the reference node and having a first gate terminal coupled to a first drain terminal; and a driver transistor coupled at a second gate terminal to the first gate terminal of the reference transistor and coupled at a second source terminal to the output (see Murakami at least [0054]-[0055] “Reference transistor coupled at a first source terminal to the reference node and having a first gate terminal coupled to a first drain terminal; driver transistor coupled at a second gate terminal to the first gate terminal of the reference transistor and coupled at a second source terminal to the output”).
As to claim 12, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 10 (see above rejection), wherein the word line regulator includes a coupling transistor configured to couple the output to the word line during the write operation (see Lee at least figs. 4-5: pixel transistors coupled to word line and bit lines; Holst at least figs. 3, 4A-C and [0036]: bit line access transistors connect bit line to memory nodes; Murakami at least [0054]-[0055]: feedback circuit – note it would be obvious to one skilled in the art to implement coupling transistor as part of feedback to drive word line during write which is common in memory/LED pixel designs).
As to claim 13, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), further comprising: a drive switch coupled between a current source and a light emitting diode, the drive switch controlled ON/OFF by the first output or the second output of the latch circuit (see Lee at least figs. 4-5, [0049] “a pixel driving circuit unit that drives a light-emitting element”; Holst at least figs. 3, 4A-C, [0036]-[0038]: bit line/memory cell).
As to claim 14, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 1 (see above rejection), wherein the word line regulator is configured to adjust the word line voltage in response to the HIGH bit line voltage so that a difference between the word line voltage and the HIGH bit line voltage is constant over time and temperature (see Holst at least figs. 3, 4A-C, [0038]: complementary bit line voltage driving; Murakami at least [0054] “The regulator 210…controls the voltage VCLMP…voltage of the node N5 is equal to the reference voltage VREF”).
As to claim 16, the combination of Lee, Holst and Murakami teach the method for writing to the memory cell of the pixel array according to claim 15 (see above rejection), wherein: the upper rail voltage of the memory cell is at least two times greater than the HIGH bit line voltage (see Lee at least fig. 4: Vdd and GND, [0050]; Holst at least [0038]: it line voltages may be below Vdd [0038] – note it would be obvious to one skilled in the art to select upper rail voltage sufficiently larger than HIGH bit line to ensure write margin).
As to claim 17, the combination of Lee, Holst and Murakami teach the method for writing to the memory cell of the pixel array according to claim 16 (see above rejection), wherein the HIGH bit line voltage being at least two times smaller than the upper rail voltage reduces a power consumed by a bit line capacitance (see Holst at least [0038] “when a WL is logically high (i.e., WL=1) the Nacc transistors 304 and 306 may be turned on and data (i.e., voltage) applied to the pair of bit lines (i.e., BL and LBL) may be written into and stored at nodes N₁ and N₂ of the memory cell 302. For example, during a write operation, BL and LBL may be driven to complementary values by the column selection circuitry (e.g., driven to a high (VCC) and low (VSS) supply voltage, respectively), which may be stored at nodes N₁ and N₂ of the memory cell 302.” – note this teaches that the HIGH bit line voltage corresponds to a supply potential applied by column circuitry during the write operation. It would have been obvious to a person of ordinary skill in the art to select the magnitude of the HIGH bit line voltage relative to the upper rail voltage (e.g., less than the full rail voltage) in order to reduce power consumed in charging and discharging the bit line capacitance. Power consumed by charging a capacitive node is proportional to the square of the voltage swing. Accordingly, reducing the HIGH bit line voltage relative to the upper rail voltage predictably reduces the dynamic power consumed by charging the bit line capacitance. Selecting the HIGH bit line voltage to be at least two times smaller than the upper rail voltage represents a routine design choice within the ordinary skill of the art to balance write margin and power consumption in memory circuits.). Therefore, the limitation that the HIGH bit line voltage is at least two times smaller than the upper rail voltage in order to reduce power consumed by a bit line capacitance would have been obvious as a predictable optimization of the voltage swing applied to the bit lines.
As to claim 18, the combination of Lee, Holst and Murakami teach the method for writing to the memory cell of the pixel array according to claim 15 (see above rejection),
wherein writing to the memory cell of the pixel array configures the memory cell in a first state, the method further comprising configuring the memory cell in a second state by: driving the first bit line to the HIGH bit line voltage, the first bit line coupled to the first output of the memory cell via the first transistor; driving the second bit line to the lower rail voltage of the memory cell, the second bit line coupled to the second output of the latch circuit via the second transistor (see Holst at least [0038] “when a WL is logically high (i.e., WL=1) the Nacc transistors 304 and 306 may be turned on and data (i.e., voltage) applied to the pair of bit lines (i.e., BL and LBL) may be written into and stored at nodes N₁ and N₂ of the memory cell 302. For example, during a write operation, BL and LBL may be driven to complementary values by the column selection circuitry (e.g., driven to a high (VCC) and low (VSS) supply voltage, respectively), which may be stored at nodes N₁ and N₂” – note this teaches complementary bit-line write operations in SRAM cells, including reversing the logic values on the bit lines in order to store the opposite state in the latch);
coupling the word line to the word line regulator so that the second transistor is biased in the ON condition to couple the lower rail voltage to the second output of the latch circuit and so that the first transistor is biased to limit a current at the first output of the latch circuit (see Murakami at least [0053]–[0054] and [0057] “the regulator 210… outputs the voltage VCLMP of VREF + Vth.”, “the voltage VCLMP is supplied… to the gate of each of the charge transfer transistors TG.” – note this teaches generating a gate bias equal to a reference voltage plus a threshold voltage and applying that voltage to transistor gates. Applying Murakami’s regulator to the Lee/Holst memory structure therefore teaches this limitation. Specifically, when the bit-line voltages are reversed to write the opposite state, the transistor connected to the LOW bit line conducts while the complementary transistor connected to the HIGH bit line remains effectively non-conductive. Murakami’s regulator-controlled gate bias (reference + threshold) limits current conduction through the transistor associated with the HIGH bit line while allowing the other transistor to conduct.); and
configuring the first output of the latch circuit at the upper rail voltage of the latch circuit based on the first output being coupled to the lower rail voltage (see Lee at least [0057] “The logic low voltage is applied to the node Q, the transistor M3 is turned on, and the transistor M4 is turned off, thereby forming a logic high voltage in the second node Q′.” – note this teaches the resulting latch behavior in which forcing one node low causes the complementary node to assume a high state).
As to claim 20, the combination of Lee, Holst and Murakami teach the pixel for the display according to claim 19 (see above rejection), wherein the word line regulator includes a diode-connected transistor configured to generate the reference voltage, the diode-connected transistor substantially matched in dimensions to the first transistor and the second transistor (see Lee at least fig. 4, [0052], [0055]: transistor structure and pixel latch; Holst at least fig. 3, 4A-C, [0036]-[0038]: bit line structure; and Murakami [0054] “NMOS emulate transistor 220…voltage VCLMP supplied to gate…matched”).
Response to Arguments
Applicant's arguments filed 12/31/2025 have been fully considered but they are not persuasive.
Applicant argues –
“Claims 1, 15, and 19 have been amended to clarify that the word line regulator is
configured to receive a HIGH bit line voltage as a reference input. This amendment explicitly distinguishes the claimed invention from the teachings of Murakami.
Murakami (e.g., Murakami FIG. 1), discloses a clamp voltage generating circuit (Murakami FIG. 1, item 10) to generate a reference voltage at a charge transfer transistor (Murakami FIG. 1, item 30). This reference voltage is derived from a voltage generated by adjustable circuitry (e.g., a variable resistor, current mirrors, and/or internal logic). Murakami discloses (e.g., Murakami para. 0056), that the settings for the adjustable circuitry are determined by data measured during wafer stage testing. This data can be stored in a memory (e.g., fuse register) for each wafer for use during operation. As a result, wafter-to-wafer variations, which could alter the reference voltage, can be eliminated.
In contrast, the claimed invention utilizes the dynamic (real-time) tracking of a bit line voltage (e.g., HIGH bit line voltage) to generate a word line voltage used to control a transistor coupling of a memory to a bit line. As amended, Claim 1 recites a word line regulator "configured to receive the HIGH bit line voltage as a reference input." Similarly, amended Claim 15 recites "receiving the HIGH bit line voltage at a word line regulator." This dynamic tracking ensures that the word line voltage is biased relative to the actual bit-line power rail present during a write operation so that the voltage difference between the bit-line power rail and the memory power rail domain does not cause current to flow in the transistor while it is supposed to be OFF. In contrast, Murakami's concept is used during a read operation and is for addressing wafer differences not power domain differences.
Because Murakami does not disclose a word line regulator configured to "receive the HIGH bit line voltage as a reference input" for the purpose of limiting a current conducted by a bit line transistor (in the OFF condition) during a write operation, the cited combination fails to teach or suggest the specific limitations of Claims 1, 15, and 19. Accordingly, Applicant requests that the rejection of Claims 1-20 be withdrawn.”
Examiner disagrees –
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., dynamic (real-time) tracking) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The amendment clarifying that the regulator “receives the HIGH bit line voltage as a reference input” does not structurally distinguish over the cited combination. The amendment clarifies the language but does not impose a structural or functional limitation not already taught or suggested by the prior art.
Lee teaches the pixel latch structure, and Holst teaches complementary bit line write operation in which one access transistor conducts while the complementary transistor coupled to the HIGH bit line remains OFF during the write operation (see Holst [0036], [0038]). Murakami teaches a regulator that receives a reference voltage (VREF) and generates a gate bias equal to the reference voltage plus a threshold voltage (VREF + Vth), which is supplied to a transistor gate (see at least [0053]–[0054], [0057]).
The claim does not require real-time sensing, dynamic tracking, or direct electrical coupling to the instantaneous bit line node. Rather, the claim requires receiving a HIGH bit line voltage as a reference input and generating a word line voltage that floats above that reference by a threshold voltage. Under the broadest reasonable interpretation, Murakami’s reference voltage corresponds to the claimed reference input because it defines the voltage level relative to which the gate bias (VREF + Vth) is generated.
Murakami’s discussion of calibration for wafer-to-wafer variation ([0056]) concerns how the reference voltage may be set or adjusted, but does not negate the structural teaching that the regulator receives a reference voltage and generates a gate bias equal to the reference voltage plus a threshold voltage. The claims do not exclude calibration or programmable reference voltage generation.
Although Murakami discusses operation in a read context, the disclosed regulator structure is not limited to read operation, and the claims do not require the regulator to operate exclusively during a write operation. A regulator that biases a transistor gate at a reference voltage plus a threshold voltage represents a general transistor biasing technique that may be applied wherever control of transistor conduction relative to a reference voltage is desired.
A person of ordinary skill in the art would have recognized that applying Murakami’s known reference-plus-threshold gate biasing technique to the Lee/Holst pixel memory structure would control current conduction through the access transistor that remains OFF during the complementary write operation. Such application represents the predictable use of a known circuit technique to improve leakage control and write stability.
KSR does not require the prior art to address the identical operational mode if the underlying technical principle is the same.
Accordingly, the combination of Lee, Holst, and Murakami teaches or renders obvious all limitations of claims 1, 15, and 19 for at least the reasons discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 3/4/2026
/KE XIAO/ Supervisory Patent Examiner, Art Unit 2627