DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Diard (patent No. 9,536,275).
As to claim 11 Diard taught the invention as claimed including A method comprising: providing a matrix engine having multiple pipelines(302) including a first pipeline and a second pipeline (e.g., see figs. 2,3,4 and col. 6, lines 3-12)[note Diard taught an array of parallel processing engines where the processor engines 302(0)-302(p-1) include functional units that may be pipelined]; sharing a common input between the first pipeline and the second pipeline of the multiple pipelines (e.g., see fig. 3); associating a first output memory(204,306) with the first pipeline and a second output memory with the second pipeline (e.g., see figs. 2,3)[note Diard taught the coupling of memory 204 and/or 306 to the output of the pipelined functional units of cores 208(0)-208(c-1) which provides this limitation]; and configuring common output circuitry to output from one of the first output memory and the second output memory(e.g., see fig. 2)[note the memory interface 214 provides a common output for the memory 204 and memory 306 to host interface and memory bridge].
Due to the similarities between claims 11 and 1; claim 1 is rejection for the same reasons as claim 11 above.
As to the further limitations of claim 1 Diard taught an accelerator device comprising: a system interconnect; and a general-purpose parallel processing engine (e.g., see col. 4, lines 30-43) coupled with the system interconnect (memory bridge 105)(e.g., see fig. 1,2).
As to claim 2 Diard taught The accelerator device as in claim 1, wherein the first pipeline is to operate concurrently with the second pipeline (e.g., see col. 6,lines 21-36)[note the SIMD operation of plural processing engines in different lanes populated with data for different threads executing the same program corresponds to this limitation].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-10,12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Diard as applied to claim 2 above, and further in view of Beu ( patent application publication No. 2021/0389948).
As to claim 3 Diard taught The accelerator device as in claim 2, wherein and the common input that is shared between the first pipeline and the second pipeline (e.g., see Fig 2 [note the input from the work distribution unit to the plural cores in fig. 2 and the inputs shared inputs to processing engines 302(1) to 302(p-1) in fig 3 corresponds to this limitation. Diard did not expressly detail the matrix engine includes a first set of multiple inputs associated with an accumulator value, a second set of multiple inputs associated with row data for a matrix multiply operation, and the common input that is shared between the first pipeline and the second pipeline. Beu however taught this limitation (e.g., see figs. 10, 11)
It would have been obvious to one of ordinary skill in the art to combine the teachings of Diard and Beu. Both references were directed to the problems of performing operations on array data in parallel in a data processor. One of ordinary skill in the art would have been motivated to incorporate the Beu teachings of multiple inputs associated with an accumulator value and multiple inputs associated with row data at least to input the data for array data processing in parallel which would speed processing and increase throughput.
As to claim 4 Diard and Beu taught The accelerator device as in claim 3, Diard taught wherein the common input is associated with column data for the graphics operation implemented with SIMD instructions (e.g., see figs 3,4 and col. 8, lines 22-31 and col. 6, lines 33-60)[note the common input to each core is input to the column(s) of processor unit(s) which comprise the cores that are configured as pipeline of functional units]. Beu taught the processing by the matrix includes matrix multiply (e.g., see figs. 10,11) implemented with SIMD instructions (e.g., see paragraph 0035).
As to claim 5 Diard and Beu taught The accelerator device as in claim 1, Beu taught wherein the general-purpose parallel processing engine is to fetch an instruction to perform operations associated with a matrix instruction and decode the instruction into multiple sub-instructions (e.g., see paragraph 0049)[note the operation of the instruction decoder of the instruction in paragraph 0050 and 0062 and the splitting of multiplication operations into a number of separate outer product operation each applied to a different combination of row/column of the first/second matrices in paragraph 0049 corresponds to this limitation][as to the fetching Beu taught the fetch stage (26) of the pipeline that fetches instruction(s) from instruction cache in fig. 1 and paragraph 0026].
As to claim 6 Diard and Beu taught The accelerator device as in claim 5, Beu taught wherein to decode the instruction into the multiple sub-instructions includes to generate a first set of sub-instructions for execution by the first pipeline and to generate a second set of sub-instructions for execution by the second pipeline (e.g., see paragraph 0049)[note the operation of the instruction decoder of the instruction in paragraph 0050 and 0062 and the splitting of multiplication operations into a number of separate outer product operation each applied to a different combination of row/column of the first/second matrices in paragraph 0049 corresponds to this limitation].
As to claim 7 Diard and Beu taught The accelerator device as in claim 6,Beu taught wherein the first set of sub-instructions and the second set of sub-instructions reference a common set of registers (register file 34) to store data associated with the common input shared between the first pipeline and the second pipeline (e.g., see paragraph 0062 and 0042 and fig. 1)[note the register file includes mapping architectural registers specified by program instructions to physical register specifiers identifying physical registers which corresponds to multiple instructions storing data storing data the data in the register file and note the common input data that is used for the operations are associated with the results that are stored in the register file].
As to claim 8 Diard and Beu taught The accelerator device as in claim 7, Beu taught wherein the matrix engine includes circuitry to: read, by the first pipeline, a first set of matrix elements specified by operands of the first set of sub-instructions and a second set of matrix elements specified by operands of the second set of sub-instructions; store, by the first pipeline, a first sub-set of matrix elements to memory within the matrix engine, the memory accessible by the second pipeline; relay, by the first pipeline, a second sub-set of matrix elements to the second pipeline; perform, by the first pipeline, processing operations specified by the first set of sub-instructions; and perform, by the second pipeline, processing operations specified by the second set of sub-instructions (e.g., see paragraphs 0058-0062)[note the mapping of the architectural register to physical registers for storage and retrieval and performing sub-operations of instruction(s) using subdivided data corresponds to this limitation].
As to claim 9 Diard and Beu taught . The accelerator device as in claim 7, Beu taught wherein to generate the first set of sub-instructions for execution by the first pipeline includes to determine a first set of registers that store operands for the first set of sub-instructions and determine a second set of registers that store operands for the second set of sub-instructions(e.g., see paragraphs 0058-0062)[note the mapping of the architectural register to physical registers for storage and retrieval and performing sub-operations of instruction(s) using subdivided data corresponds to this limitation].
.
As to claim 10 Diard and Beu taught The accelerator device as in claim 9, Beu taught wherein the common output circuitry is to write output from one of the first output memory and the second output memory to a register file associated with the matrix engine(e.g., see fig. 1)[note the register file (34) is depicted as coupled to the memory via load store unit (LDST) which is coupled to the memory. Therefore one of ordinary skill in the art would have been motivated to store/retrieve data to/from memory and register file to ensure that the data needed for processing was available with the fastest access such as in registers and ensured that when the register file was full storing data not currently being used in memory so it was not lost.
As to claim 12 Diard and Beu taught The method of claim 11, Beu taught comprising: reading operand data for an instruction to be executed by the matrix engine from a register file (34) associated with the matrix engine, the operand data including matrix elements associated with the instruction (e.g., see paragraph 0062 and 0067); Beu taught executing a first portion of the instruction via the first pipeline (e.g., see figs. 9,10 paragraph 0035) and Beu taught concurrently executing a second portion of the instruction via the second pipeline (e.g., see paragraphs 0035 and 0064); and Diard taught writing output of the first portion of the instruction and the second portion of the instruction to the register file (e.g., see col. 6, line 61-col. 7, line 6).
As to claim 13 Diard and Beu taught The method of claim 12, Beu taught wherein reading operand data for the instruction includes: reading, by the first pipeline, matrix elements associated with the first portion of the instruction and the second portion of the instruction (e.g., see paragraph 0070); Diard taught storing, by the first pipeline, a first sub-set of matrix elements to memory within the matrix engine, the memory accessible by the second pipeline; and relaying, by the first pipeline, a second sub-set of matrix elements to the second pipeline(e.g., see col. 6, line 61-col. 7, line 28)[note in the embodiment where data is needed by multiple threads one of ordinary skill would have been motivated to relay the results from one pipeline to a second pipeline at least to reduce the time for the secondary pipe to access the required data and therefore reduce processing time and increase throughput].
As to claim 14 Diard and Beu taught The method of claim 12, Diard taught wherein writing output to the register file includes: writing output from the first pipeline to a first output buffer associated with the first pipeline writing output from the second pipeline to an output buffer associated with the second pipeline (e.g., see col. 6, line 61-col. 7, line 28). Beu and Diard did not expressly detail writing output of first and second pipeline to first and second output buffers and writing output from the first output buffer and the second output buffer to the register file via a common output. However one of ordinary skill would have been motivated to store the output of the first and second pipelines in separate buffers and then storing the data to the register file at least to relax the timing necessary for storing data to the register file and retrieving data from the register file. This would have simplified the control of storing and retrieving data and a reduced system cost.
Allowable Subject Matter
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 15 requires among other things:
15. A system comprising: a memory device; and an accelerator device coupled to the memory device, the accelerator device comprising multiple pipelines of processing elements, each of the multiple pipelines including multiple pipeline stages, the multiple pipelines including a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline, the common input associated with column data for a matrix multiply operation, wherein the multiple pipeline stages each include multiple processing channels, each of the multiple processing channels includes a first set of multipliers associated with a first pipeline stage, a second set of multipliers associated with a second pipeline stage, and an adder that is common to the first pipeline stage and the second pipeline stage.
The closest prior art includes Diard and Beu. The closest prior art taught some features of claim 15 as discussed above. However the closest prior at did not disclose among other things the limitations of claim 15 as shown above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (Patent No. 2021/0182021) disclosed computational units for element approximation (e.g., see abstract).
Fleming (patent application publication No. 2019/0005161) disclosed processor for a configurable spatial accelerator with performance, correctness and power reduction features (e.g. see abstract).
Kaminitz (patent application publication No. 2022/0101042) disclosed cluster interlayer safety mechanism in an artificial neural network processor (e.g., see abstract).
Song (patent application publication No. 2021/0081175) disclosed multiply-accumulate unit (e.g., see abstract).
Kwon (patent application publication No. 2022/0036165) disclosed system with deep learning operations (e.g., see abstract).
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ERIC . COLEMAN
Primary Examiner
Art Unit 2183
EC
/ERIC COLEMAN/ Primary Examiner, Art Unit 2183