Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election with traverse of Species II, corresponding to Fig. 4, in the reply filed on February 23, 2026 is acknowledged.
Drawings
The drawings are objected to because the electrical components that are in parallel with transistor M1 and transistor M2 are unidentified.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 (line 2) recites "a fast-locking control unit". There is a lack of written description as to the circuitry used to achieve the "fast-locking control unit". Thus, the specification fails to provide a demonstration of pos.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112(pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 (line 1) recites "a phase frequency detector". The phrase is indefinite as "a phase frequency detector" was introduced in claim 1. It's unclear if this is same or different 'phase frequency detector' of claim 1. For compact prosecution purposes, the examiner interprets the 'phase frequency detector' of claim 11 is the same as the 'phase frequency detector' of claim 1. Thus, this is indefinite under 112(b).
Claim 11 (line 2) recites "a loop filter". The phrase is indefinite as "a loop filter" was introduced in claim 1. It's unclear if this is same or different 'loop filter' of claim 1. For compact prosecution purposes, the examiner interprets the 'loop filter' of claim 11 is the same as the 'loop filter' of claim 1. Thus, this is indefinite under 112(b).
Claim 11 (line 2) recites "a fast-locking control unit". The wording of "fast" is indefinite because it does not define what speed would constitute a "fast" locking control unit. For compact prosecution purposes, the examiner interprets the 'fast-locking control unit' to be a controller which speeds up the frequency locking, as shown in the section 103 rejection. Thus, this is indefinite under 112(b).
Claims 12-20 inherit the defects of the associated parent claim and/or any intervening claims.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ruegg et al. (US 20020175723 A1), in view of Ock et al. (US 20240213990 A1); hereinafter Ruegg, in view of Ock.
Regarding Claim 1, Ruegg discloses a charge pump [Fig. 4], comprising: a first current source circuit [404] comprising a first resistor open-loop gain module [412] and a first transistor [402], the first resistor open-loop gain module being connected to the first transistor in such a way that a voltage [voltage at output node 411] at an input terminal of the first transistor [pg] is consistent with a first reference voltage [414]; a second current source circuit [406] comprising a second resistor open-loop gain module [422] and a second transistor [408], the second resistor open-loop gain module being connected to the second transistor in such a way that a voltage [voltage at output node 421] at an output terminal of the second transistor [ng] is consistent with a second reference voltage [424]; and a switching circuit [214] coupled to the first current source circuit, the second current source circuit and a loop filter [202], and configured to control charging of the loop filter [paragraphs 0031-0036]. Ruegg does not explicitly disclose wherein the charge pump comprising: a first current source circuit comprising a first variable resistor open-loop gain module; a second current source circuit comprising a second variable resistor open-loop gain module; and the switching circuit configured to control charging the loop filter in response to an output signal from a phase frequency detector. It should be noted that the specification is silent concerning the need of a variable versus a single valued resistor.
Regardless, Ock discloses wherein the charge pump [Fig. 7; 730] comprising: a first current source circuit [MP1/R1] comprising a first variable resistor open-loop gain module [R1]; a second current source circuit [MN1/R2] comprising a second variable resistor open-loop gain module [R2]; and the switching circuit [SW1] configured to control charging the loop filter [Fig. 2A/3A/5A/6A/7] in response to an output signal from a phase frequency detector [paragraph 0070; 210/310/510/610/710]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ruegg, in view of Ock, by replacing the variable resistors of Ock with the constant resistors of Ruegg, for the benefit of setting a specific voltage.
Regarding Claim 2, Ruegg, in view of Ock, discloses the charge pump according to claim 1, wherein the first variable resistor open-loop gain module comprises a first resistor [Ock, R1 in place of Ruegg 412] and a first operational amplifier [Ruegg, 410], the first resistor being provided between a voltage input terminal [Ruegg, VDD/210] and the first transistor, the first transistor being provided between the first resistor and the switching circuit, and the first operational amplifier being connected to the first transistor.
Regarding Claim 5, Ruegg, in view of Ock, discloses the charge pump according to claim 2, wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor [Ruegg, paragraph 0036], and the first current source circuit is a charging current source circuit [Ruegg, paragraph 0032]comprising the first resistor, the first transistor and the first operational amplifier, wherein the PMOS transistor has a source [Ruegg, ps] connected to the voltage input terminal through the first resistor, and a drain [Ruegg, pd] connected to the switching circuit; and the first operational amplifier has a non-inverting input terminal [Ruegg, (+)/413] configured to receive the first reference voltage [Ruegg, paragraph 0037], an inverting input terminal [Ruegg, (-)/415] connected to the source of the PMOS transistor, and an output terminal [Ruegg, 411] connected to a gate of the PMOS transistor [Ruegg, pg].
Regarding Claim 3, Ruegg, in view of Ock, discloses the charge pump according to claim 1, wherein the second variable resistor open-loop gain module comprises a second resistor [Ock, R2 in place of Ruegg 422] and a second operational amplifier [Ruegg, 420], the second resistor being provided between the second transistor and a voltage output terminal [Ruegg, VSS/212], the second transistor being provided between the switching circuit and the second resistor, and the second operational amplifier being connected to the second transistor.
Regarding Claim 6, Ruegg, in view of Ock, discloses the charge pump according to claim 3, wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor [Ruegg, paragraph 0033], and the second current source circuit is a discharging current source circuit [Ruegg, paragraph 0032] comprising the second resistor, the second transistor and the second operational amplifier, wherein the second transistor has a source [Ruegg, ns] grounded through the second resistor, and a drain [Ruegg, nd] connected to the switching circuit; and the second operational amplifier has a non-inverting input terminal [Ruegg, (+)/423] configured to receive the second reference voltage, an inverting input terminal [Ruegg, (-)/425] connected to the source of the second transistor, and an output terminal [Ruegg, 421] connected to a gate [Ruegg, ng] of the second transistor.
Regarding Claim 7, Ruegg, in view of Ock, discloses the charge pump according to claim 1, wherein a magnitude of current of the first current source is regulated by adjusting the first reference voltage; and/or a magnitude of current of the second current source is regulated by adjusting the second reference voltage [Ruegg, paragraphs 0033-0038].
Claims 4 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ruegg, in view of Ock, further in view of Ang-Sheng Lin (US 7439784 B2); hereinafter Ruegg, in view of Ock, further in view of Ang-Sheng Lin.
Regarding Claim 4, Ruegg, in view of Ock, does not explicitly disclose the charge pump according to claim 1, wherein the switching circuit is configured to, in response to an UP/DOWN signal output by the phase frequency detector, enable the first current source circuit to charge the loop filter, or enable the loop filter to discharge into the second current source circuit [Ruegg, paragraphs 0026-0036].
However, Ang-Sheng Lin discloses the charge pump [Fig. 2/4, 200] wherein the switching circuit [212/214/232/234/220] is configured to, in response to an UP/DOWN signal output [output of 414] by the phase frequency detector [412], enable the first current source circuit to charge the loop filter, or enable the loop filter to discharge into the second current source circuit [column 3, line 17 - column 4, line 20]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ruegg, in view of Ock, by configuring the switching circuit with Ang-Sheng Lin's configuration, for the benefit of charging/discharging the loop filter.
Regarding Claim 8, Ruegg, in view of Ock, further in view of Ang-Sheng Lin, discloses the charge pump according to claim 4, wherein the switching circuit comprises a third operational amplifier [Ang-Sheng Lin, 220], a first switch [Ang-Sheng Lin, 232], a second switch [Ang-Sheng Lin, 212], a third switch [Ang-Sheng Lin, 234] and a fourth switch [Ang-Sheng Lin, 214], wherein the third operational amplifier has a non-inverting input terminal [Ang-Sheng Lin, top terminal of 220] connected to the second switch and the fourth switch via a first node [Ang-Sheng Lin, 216], an inverting input terminal [Ang-Sheng Lin, bottom terminal of 220], and an output terminal [Ang-Sheng Lin, output of 220 at node 224] connected to the inverting input terminal and further connected to the first switch and the third switch via a second node [Ang-Sheng Lin, 236]; the first switch and the second switch are connected to a drain of the first transistor [Ruegg, Fig. 4, pd] via a third node [Ang-Sheng Lin, node between 232-drain and 212-drain]; and the third switch and the fourth switch are connected to a drain of the second transistor [Ruegg, Fig. 4, nd] via a fourth node [Ang-Sheng Lin, node between 234-source and 214-source].
Regarding Claim 9, Ruegg, in view of Ock, further in view of Ang-Sheng Lin, discloses the charge pump according to claim 8, wherein the first node is connected to an input terminal of the loop filter [Ang-Sheng Lin, Fig. 4, 216 connected to 416].
Regarding Claim 10, Ruegg, in view of Ock, further in view of Ang-Sheng Lin, discloses the charge pump according to claim 8, wherein the second switch is configured to receive the UP signal output by the phase frequency detector [Ang-Sheng Lin, up], the first switch is configured to receive the inversed UP signal [Ang-Sheng Lin, dup], the fourth switch is configured to receive the DOWN signal output [Ang-Sheng Lin, dn] by the phase frequency detector, and the third switch is configured to receive the inversed DOWN signal [Ang-Sheng Lin, ddn].
Claims 11-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20100183109 A1), in view of Ruegg, further in view of Ock; hereinafter Lin, in view of Ruegg, further in view of Ock.
Regarding Claim 11, Lin discloses a phase-locked loop circuit [Fig. 4], comprising a phase frequency detector [1], a loop filter [3], a voltage-controlled oscillator [4], a fast-locking control unit [8; paragraphs 0046-0047], a frequency divider [5], and a charge pump [2].
As per KSR Rationale A, the usage of a charge pump in a phase-locked loop circuit is well known in the art at time of invention (Lin et al. (US 20100183109 A1)). The features of the charge pump of claim 1 are obvious in respect to the prior art, as shown in the rejection of claim 1 above. The charge pump of claim 1 provides the classic features of the charge pump of Lin, and could be substituted with predictable results. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin, in view of Ruegg, further in view of Ock, by replacing the charge pump of Lin with the charge pump of Ruegg, in view of Ock, for the benefit of setting a specific voltage and improving efficiency and stability.
Regarding Claim 12, Lin, in view of Ruegg, further in view of Ock, discloses the phase-locked loop circuit according to claim 11, wherein the first variable resistor open-loop gain module comprises a first resistor [Ock, R1 in place of Ruegg 412] and a first operational amplifier [Ruegg, 410], the first resistor being provided between a voltage input terminal [Ruegg, VDD/210] and the first transistor, the first transistor being provided between the first resistor and the switching circuit, and the first operational amplifier being connected to the first transistor.
Regarding Claim 15, Lin, in view of Ruegg, further in view of Ock, discloses the phase-locked loop circuit according to claim 12, wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor [Ruegg, paragraph 0036], and the first current source circuit is a charging current source circuit [Ruegg, paragraph 0032] comprising the first resistor, the first transistor and the first operational amplifier, wherein the PMOS transistor has a source [Ruegg, ps] connected to the voltage input terminal through the first resistor, and a drain [Ruegg, pd] connected to the switching circuit; and the first operational amplifier has a non-inverting input terminal [Ruegg, (+)/413] configured to receive the first reference voltage [Ruegg, paragraph 0037], an inverting input terminal [Ruegg, (-)/415] connected to the source of the PMOS transistor, and an output terminal [Ruegg, 411] connected to a gate of the PMOS transistor [Ruegg, pg].
Regarding Claim 13, Lin, in view of Ruegg, further in view of Ock, discloses the phase-locked loop circuit according to claim 11, wherein the second variable resistor open-loop gain module comprises a second resistor [Ock, R2 in place of Ruegg 422] and a second operational amplifier [Ruegg, 420], the second resistor being provided between the second transistor and a voltage output terminal [Ruegg, VSS/212], the second transistor being provided between the switching circuit and the second resistor, and the second operational amplifier being connected to the second transistor.
Regarding Claim 16, Lin, in view of Ruegg, further in view of Ock, discloses the phase-locked loop circuit according to claim 13, wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor [Ruegg, paragraph 0033], and the second current source circuit is a discharging current source circuit [Ruegg, paragraph 0032] comprising the second resistor, the second transistor and the second operational amplifier, wherein the second transistor has a source [Ruegg, ns] grounded through the second resistor, and a drain [Ruegg, nd] connected to the switching circuit; and the second operational amplifier has a non-inverting input terminal [Ruegg, (+)/423] configured to receive the second reference voltage, an inverting input terminal [Ruegg, (-)/425] connected to the source of the second transistor, and an output terminal [Ruegg, 421] connected to a gate of the second transistor [Ruegg, ng].
Regarding Claim 17, Lin, in view of Ruegg, further in view of Ock, discloses the phase-locked loop circuit according to claim 11, wherein a magnitude of current of the first current source is regulated by adjusting the first reference voltage; and/or a magnitude of current of the second current source is regulated by adjusting the second reference voltage [Ruegg, paragraphs 0033-0038].
Claims 14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Ruegg, further in view of Ock, further in view of Ang-Sheng Lin.
Regarding Claim 14, Lin, in view of Ruegg, further in view of Ock, does not explicitly disclose the phase-locked loop circuit according to claim 11, wherein the switching circuit is configured to, in response to an UP/DOWN signal output by the phase frequency detector, enable the first current source circuit to charge the loop filter, or enable the loop filter to discharge into the second current source circuit [Ruegg, paragraphs 0026-0036].
However, Ang-Sheng Lin discloses the charge pump [Fig. 2/4, 200] wherein the switching circuit [212/214/232/234/220] is configured to, in response to an UP/DOWN signal output [output of 414] by the phase frequency detector [412], enable the first current source circuit to charge the loop filter, or enable the loop filter to discharge into the second current source circuit [column 3, line 17 - column 4, line 20]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin, in view of Ruegg, further in view of Ock, by configuring the switching circuit with Ang-Sheng Lin's configuration, for the benefit of charging/discharging the loop filter.
Regarding Claim 18, Lin, in view of Ruegg, further in view of Ock, further in view of Ang-Sheng Lin, discloses the phase-locked loop circuit according to claim 14, wherein the switching circuit comprises a third operational amplifier [Ang-Sheng Lin, 220], a first switch [Ang-Sheng Lin, 232], a second switch [Ang-Sheng Lin, 212], a third switch [Ang-Sheng Lin, 234] and a fourth switch [Ang-Sheng Lin, 214], wherein the third operational amplifier has a non-inverting input terminal [Ang-Sheng Lin, top terminal of 220] connected to the second switch and the fourth switch via a first node [Ang-Sheng Lin, 216], an inverting input terminal [Ang-Sheng Lin, bottom terminal of 220], and an output terminal [Ang-Sheng Lin, output of 220 at node 224] connected to the inverting input terminal and further connected to the first switch and the third switch via a second node [Ang-Sheng Lin, 236]; the first switch and the second switch are connected to a drain of the first transistor [Ruegg, Fig. 4, pd] via a third node [Ang-Sheng Lin, node between 232-drain and 212-drain]; and the third switch and the fourth switch are connected to a drain of the second transistor [Ruegg, Fig. 4, nd] via a fourth node [Ang-Sheng Lin, node between 234-source and 214-source].
Regarding Claim 19, Lin, in view of Ruegg, further in view of Ock, further in view of Ang-Sheng Lin, discloses the phase-locked loop circuit according to claim 18, wherein the first node is connected to an input terminal of the loop filter [Ang-Sheng Lin, Fig. 4, 216 connected to 416].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sowlati et al. (US 7091759 B2), in view of Lin, further in view of Ruegg, further in view of Ock; hereinafter Sowlati, in view of Lin, further in view of Ruegg, further in view of Ock.
Regarding Claim 20, Sowlati discloses a transceiver [Fig. 3; 300], comprising a phase-locked loop circuit [360].
As per KSR Rationale A, the usage of a phase-locked loop circuit in a transceiver is well known in the art at the time of invention (Sowlati et al. (US 7091759 B2)). The features of the phase-locked loop circuit of claim 11 are obvious in respect to the prior art, as shown in the rejection of claim 11 above. The phase-locked loop circuit of claim 11 provides the classic features of the phase-locked loop circuit of Sowlati, and could be substituted with predictable results. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sowlati, in view of Lin, further in view of Ruegg, further in view of Ock, by replacing the phase-locked loop circuit of Sowlati with the phase-locked loop circuit of Lin, in view of Ruegg, further in view of Ock, for the benefit of setting a specific voltage and improving efficiency and stability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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/Amit R Bhatia/Examiner, Art Unit 2842
/REGIS J BETSCH/SPE, Art Unit 2843