Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Remarks
Applicant’s remarks, see A. Drawings, filed July 9, 2026, with respect to the electrical components in parallel with transistor M1 and transistor M2 were unidentified on Fig. 4 have been fully considered and are persuasive. The objection of April 9, 2026 has been withdrawn.
Applicant’s remarks, see B. Claim Rejections under 35 U.S.C. 112; 2) Rejection of Claims 11-20 under 35 U.S.C. 112(b) - Indefiniteness, filed July 9, 2026, with respect to the lack of antecedent basis for "a phase frequency detector" and "a loop filter" relative to Claim 1 have been fully considered and are persuasive. The r of April 9, 2026 has been withdrawn.
Response to Arguments
Applicant's arguments, see B. Claim Rejections under 35 U.S.C. 112; 1) Rejection of Claim 11 under 35 U.S.C. 112(a) - Written Description, filed July 9, 2026, with respect to the specification lacks sufficient structural descriptions or detailed circuitry for the recited "fast-locking control unit" has been fully considered but they are not persuasive.
Applicant argues, “It is a well-settled principle of U.S. patent law that a specification is addressed to a person having ordinary skill in the art (PHOSITA) and need not disclose what is well-known, routine, or standard in the art. The written description requirement does not demand micro-level structural schematics for components whose implementations belong to the common general knowledge of a PHOSITA. In the technical field of PLLs and integrated circuits, a "fast-locking control unit" (or fast-locking controller) is a standard, ubiquitous functional module. Its high-level implementation-such as utilizing routine logic gates or edge-triggered reset signals to temporarily adjust frequency divider states or charge pump currents to accelerate phase acquisition-is well within the routine design capabilities of a PHOSITA. To support this position, Applicants respectfully submit herewith Exhibit A (Chinese Patent Application Publication No. CN 116938234 A), which is standard prior art to the present application. For English translation, see US Publication No. 2024/0413826A1. As explicitly shown in the claims and specification of Exhibit A, the term "fast-locking control unit" is directly utilized as a standard, recognizable component within a conventional PLL architecture, along with its routine input/output interactions. Because the implementation of a fast-locking control unit was fully within the public domain and recognized as standard engineering practice prior to Applicants' priority date, the explicit textual introduction of this unit within the specification provides more than ample guidance. A PHOSITA, reading the specification in light of such established industry practices, would immediately understand how to incorporate and implement the stated fast-locking functionality without undue experimentation. Accordingly, the textual disclosure in the specification is legally sufficient to demonstrate that Applicants were in full possession of the claimed invention as of the filing date.” Examiner respectfully disagrees.
Running a search for a fast locking control unit in a phased locked loop, in PE2E Search, specifically for “pll AND (fast ADJ locking ADJ ((control ADJ unit) OR (control$1 unit)))”, provided only 15 references. Therefore, a fast locking control unit is not well-known, routine, or standard in the art. On the other hand, when running a search for a locking control unit in a phased lock loop, in PE2E Search, specifically for “pll AND (locking ADJ ((control ADJ unit) OR (control$1 unit)))”, resulted in finding over 10,000 references. Therefore, locking control units are well-known, routine, or standard in the art. Because of this discrepancy, the term “fast” is interpreted as a locking control unit that is operating faster than a standard locking control unit requiring modified circuitry.
Also, Exhibit A [Chinese Patent Application Publication No. CN 116938234 A (English translation, see US Publication No. 2024/0413826A1)] provided in the Applicant’s arguments was not incorporated by reference with the original filing of this application. This does not provide evidence that this device is well-known, routine, or standard in the art, because the reference is the Applicant’s and Inventor’s own publication.
Additionally, there are multiple ways for this controller to be used within a phase locked loop circuit, and the specification does not describe the specific use for this application.
Applicant's arguments, see B. Claim Rejections under 35 U.S.C. 112; 2) Rejection of Claims 11-20 under 35 U.S.C. 112(b) - Indefiniteness, filed July 9, 2026, with respect to the term "fast" being an indefinite term of degree has been fully considered but they are not persuasive. Explanation as to the non-persuasiveness is described below under the Claim Rejections - 35 USC § 112.
Applicant argues, “the word "fast" is not used as a subjective term of degree to measure a precise locking time. Instead, it is an integral part of an industry-recognized compound technical term ("fast-locking control unit") designating a specific class of auxiliary circuits built to accelerate PLL locking. As evidenced by Exhibit A, this unit has an objective operational meaning in the art.” Examiner respectfully disagrees.
As stated above, in the Examiner remarks to the 112(a) arguments, this terminology is not part of an industry-recognized compound technical term. Additionally, the evidence provided is the Applicant’s own publication. As there is no description in the specification, it is indefinite how fast is “fast”.
Applicant’s arguments, see C. Claim Rejections under 35 U.S.C. 103, filed July 9, 2026, with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the fast-locking control unit must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5 (lines 3-4) recites "comprising the first resistor, the first variable transistor and the first operational amplifier". Examiner understands this to be a misplacement of the word "variable", and interprets this to recite "comprising the first variable resistor, the first transistor and the first operational amplifier".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 (line 2) is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 (line 2) recites "a fast-locking control unit". There is a lack of written description as to the circuitry used to achieve the "fast-locking control unit". Although a POSITA would recognize a locking control unit, there is nothing in the specification as to how a “fast-locking control unit" would differ from the normal unit. Thus, the specification fails to provide a demonstration of possession of such a unit. Additionally, there are multiple ways for a controller to be used within a phase locked loop circuit, and the specification does not describe the specific use for this application.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 11 (line 2) recites "a fast-locking control unit". The wording of "fast" is indefinite because it does not define what speed would constitute a "fast" locking control unit. For compact prosecution purposes, the examiner interprets the 'fast-locking control unit' to be a controller which speeds up the frequency locking, as shown in the section 103 rejection. Thus, this is indefinite under 112(b).
Claims 14-20 inherit the defects of the associated parent claim and/or any intervening claims.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, and 7-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Riccardi et al. (US 20250293694 A1); hereinafter Riccardi.
Regarding Claim 1, Riccardi discloses a charge pump [Fig. 2], comprising: a first current source circuit [Fig. 2/4; 112] comprising a first variable resistor open-loop gain module [Fig. 4; 140/144] and a first transistor [Fig. 4; 142], the first variable resistor open-loop gain module being connected to the first transistor in such a way that a voltage at an input terminal of the first transistor is consistent with a first reference voltage [Fig. 4; Vref1]; a second current source circuit [Fig. 2/4; 114] comprising a second variable resistor open-loop gain module [Fig. 4; 148/152] and a second transistor [Fig. 4; 150], the second variable resistor open-loop gain module being connected to the second transistor in such a way that a voltage at an output terminal of the second transistor is consistent with a second reference voltage [Fig. 4; Vref2]; and a switching circuit [Fig. 2; 116/117/118/119/121] coupled to the first current source circuit, the second current source circuit and a loop filter [Fig. 1; 106; Fig. 2 104O is the output of 104, shown in Fig. 1 where the output of 104 is coupled 106], and configured to control charging of the loop filter in response to an output signal from a phase frequency detector [paragraphs 0022-0023], wherein the first variable resistor open-loop gain module comprises a first variable resistor [Fig. 4; 144] and a first operational amplifier [Fig. 4; 140], the first variable resistor being provided between a voltage input terminal [paragraph 0027; supply voltage terminal] and the first transistor, the first transistor being provided between the first variable resistor and the switching circuit, and the first operational amplifier being connected to the first transistor, and wherein the second variable resistor open-loop gain module comprises a second variable resistor [Fig. 4; 152] and a second operational amplifier [Fig. 4; 148], the second variable resistor being provided between the second transistor and a voltage output terminal [paragraph 0028; reference voltage terminal, such as ground], the second transistor being provided between the switching circuit and the second variable resistor, and the second operational amplifier being connected to the second transistor.
Regarding Claim 4, Riccardi discloses the charge pump according to claim 1, wherein the switching circuit is configured to, in response to an UP/DOWN signal output by the phase frequency detector [Fig. 1; paragraph 0020], enable the first current source circuit to charge the loop filter [paragraphs 0021-0023, 0027-0028], or enable the loop filter to discharge into the second current source circuit [paragraphs 0021-0023, 0027-0028].
Regarding Claim 8, Riccardi discloses the charge pump according to claim 4, wherein the switching circuit comprises a third operational amplifier [Fig. 2, 121], a first switch [Fig. 2, 117], a second switch [Fig. 2, 116; Fig. 4, 118], a third switch [Fig. 2, 119] and a fourth switch [Fig. 2, 118; Fig. 4, 120], wherein the third operational amplifier has a non-inverting input terminal connected to the second switch and the fourth switch via a first node [Fig. 2, node between 116/118 at output 104O; Fig. 4, node between 118/120 at output 104O (see Fig. 2 & 4 below)], an inverting input terminal, and an output terminal connected to the inverting input terminal and further connected to the first switch and the third switch via a second node [node between 117/119 at output of 121 (see Fig. 2 below)]; the first switch and the second switch are connected to a drain [Fig. 4, connected thru 142 to the drain] of the first transistor via a third node [Fig. 2, node between 112 and 116; Fig. 4, node between 118 and 142 (see Fig. 2 & 4 below)]; and the third switch and the fourth switch are connected to a drain [Fig. 4, drain of 150] of the second transistor via a fourth node [Fig. 2, node between 118 and 114; Fig. 4, node between 120 and 150 (see Fig. 2 & 4 below)].
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Regarding Claim 9, Riccardi discloses the charge pump according to claim 8, wherein the first node is connected to an input terminal of the loop filter [Fig. 2, node between 116/118 at output 104O; Fig. 4, node between 118/120 at output 104O; where Fig. 1 shows the charge pump output to the input of the loop filter].
Regarding Claim 10, Riccardi discloses the charge pump according to claim 8, wherein the second switch is configured to receive the UP signal output by the phase frequency detector [paragraph 0022], the first switch is configured to receive the inversed UP signal [paragraph 0023], the fourth switch is configured to receive the DOWN signal output by the phase frequency detector [paragraph 0022], and the third switch is configured to receive the inversed DOWN signal [paragraph 0023].
Regarding Claim 7, Riccardi discloses the charge pump according to claim 1, wherein a magnitude of current of the first current source is regulated by adjusting the first reference voltage [paragraph 0027]; and/or a magnitude of current of the second current source is regulated by adjusting the second reference voltage [paragraph 0028].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Riccardi, in view of Ruegg et al. (US 20020175723 A1); hereinafter Riccardi, in view of Ruegg.
Regarding Claim 5, Riccardi discloses the charge pump according to claim 1, wherein the first current source circuit is a charging current source circuit [paragraph 0022; sourcing current] comprising the first variable resistor, the first transistor and the first operational amplifier, wherein the transistor has a source [Fig. 4, 142-source] connected to the voltage input terminal through the first variable resistor, and a drain [Fig. 4, 142-drain] connected to the switching circuit [Fig. 4, indirectly connected]; and the first operational amplifier has an input terminal configured to receive the first reference voltage, an input terminal connected to the source of the transistor [Fig. 4, directly connected to 142-source], and an output terminal connected to a gate of the transistor [Fig. 4, directly connected to 142-gate]. Riccardi does not explicitly disclose wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor, and the first current source circuit is a charging current source circuit, wherein the PMOS transistor has a source connected to the voltage input terminal through the first resistor, and a drain connected to the switching circuit; and the first operational amplifier has a non-inverting input terminal configured to receive the first reference voltage, an inverting input terminal connected to the source of the PMOS transistor, and an output terminal connected to a gate of the PMOS transistor.
However, Ruegg discloses wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor [Fig. 4, 402; paragraph 0036], and the first current source circuit [404] is a charging current source circuit [paragraph 0032], wherein the PMOS transistor has a source [ps] connected to the voltage input terminal [VDD, 210] through the first resistor, and a drain [pd] connected to the switching circuit [directly connected to 214]; and the first operational amplifier [410] has a non-inverting input terminal [(+)/413] configured to receive the first reference voltage [paragraph 0037], an inverting input terminal [(-)/415] connected to the source of the PMOS transistor [directly connected to ps], and an output terminal [411] connected to a gate of the PMOS transistor [directly connected to pg]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Ruegg in the invention of Riccardi, with the expected benefit of charging the loop filter. This method of improving Riccardi using Ruegg was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Ruegg. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi and Ruegg to obtain the invention: incorporating a PMOS transistor in the charge pump's charging current source.
Regarding Claim 6, Riccardi discloses the charge pump according to claim 1, wherein the second current source circuit is a discharging current source circuit [paragraph 0022; sinking current] comprising the second variable resistor, the second transistor and the second operational amplifier, wherein the second transistor has a source [Fig. 4, 150-source] grounded through the second variable resistor, and a drain [Fig. 4, 150-drain] connected to the switching circuit [Fig. 4, directly connected to 120]; and the second operational amplifier has an input terminal configured to receive the second reference voltage, an input terminal connected to the source of the second transistor, and an output terminal connected to a gate of the second transistor. Riccardi does not explicitly disclose wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor, and the second current source circuit is a discharging current source circuit, wherein the NMOS transistor has a source grounded through the second resistor, and a drain connected to the switching circuit; and the second operational amplifier has a non-inverting input terminal configured to receive the second reference voltage, an inverting input terminal connected to the source of the NMOS transistor, and an output terminal connected to a gate of the NMOS transistor.
However, Ruegg discloses wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor [Fig. 4, 408; paragraph 0033], and the second current source circuit [406] is a discharging current source circuit [paragraph 0032], wherein the second transistor has a source [ns] grounded [VSS, 212] through the second resistor, and a drain [nd] connected to the switching circuit [directly connected to 214]; and the second operational amplifier [420] has a non-inverting input terminal [(+)/423] configured to receive the second reference voltage [paragraph 0033], an inverting input terminal [(-)/425] connected to the source of the second transistor [ns], and an output terminal [421] connected to a gate of the second transistor [ng]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Ruegg in the invention of Riccardi, with the expected benefit of discharging the loop filter. This method of improving Riccardi using Ruegg was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Ruegg. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi and Ruegg to obtain the invention: incorporating a NMOS transistor in the charge pump's discharging current source.
Claims 11, 14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Riccardi, in view of Li et al. (CN 111953339 B); hereinafter Riccardi, in view of Li .
Regarding Claim 11, as best understood, Riccardi discloses a phase-locked loop circuit [Fig. 1, 100], comprising a phase frequency detector [102], a loop filter [106], a voltage-controlled oscillator [108], a frequency divider [110], and a charge pump [104], the charge pump comprising: a first current source circuit [Fig. 2/4; 112] comprising a first variable resistor open-loop gain module [Fig. 4; 140/144] and a first transistor [Fig. 4; 142], the first variable resistor open-loop gain module being connected to the first transistor in such a way that a voltage at an input terminal of the first transistor is consistent with a first reference voltage [Fig. 4; Vref1]; a second current source circuit [Fig. 2/4; 114] comprising a second variable resistor open-loop gain module [Fig. 4; 148/152] and a second transistor [Fig. 4; 150], the second variable resistor open-loop gain module being connected to the second transistor in such a way that a voltage at an output terminal of the second transistor is consistent with a second reference voltage [Fig. 4; Vref2]; and a switching circuit [Fig. 2; 116/117/118/119/121] coupled to the first current source circuit, the second current source circuit and a loop filter [Fig. 1; 106; Fig. 2 104O is the output of 104, shown in Fig. 1 where the output of 104 is coupled 106], and configured to control charging of the loop filter in response to an output signal from a phase frequency detector [paragraphs 0022-0023], wherein the first variable resistor open-loop gain module comprises a first variable resistor [Fig. 4; 144] and a first operational amplifier [Fig. 4; 140], the first variable resistor being provided between a voltage input terminal [paragraph 0027; supply voltage terminal] and the first transistor, the first transistor being provided between the first variable resistor and the switching circuit, and the first operational amplifier being connected to the first transistor, and wherein the second variable resistor open-loop gain module comprises a second variable resistor [Fig. 4; 152] and a second operational amplifier [Fig. 4; 148], the second variable resistor being provided between the second transistor and a voltage output terminal [paragraph 0028; reference voltage terminal, such as ground], the second transistor being provided between the switching circuit and the second variable resistor, and the second operational amplifier being connected to the second transistor. Riccardi does not explicitly disclose wherein a phase-locked loop circuit [Fig. 1, 100], comprising a fast-locking control unit.
However, Li discloses a phase-locked loop circuit [Fig. 1; paragraph 0022], comprising a phase frequency detector [811], a loop filter [813], a voltage-controlled oscillator [815], a fast-locking control unit [817], a frequency divider [816], and a charge pump [812]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Ruegg in the invention of Riccardi, with the expected benefit of recovering from phase or frequency errors. This method of improving Riccardi using Ruegg was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Ruegg. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi and Ruegg to obtain the invention: incorporating a fast locking circuit within a phase-locked loop.
Regarding Claim 14, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 11, wherein the switching circuit is configured to, in response to an UP/DOWN signal output by the phase frequency detector [Riccardi; Fig. 1; paragraph 0020], enable the first current source circuit to charge the loop filter [Riccardi; paragraphs 0021-0023, 0027-0028], or enable the loop filter to discharge into the second current source circuit [Riccardi; paragraphs 0021-0023, 0027-0028].
Regarding Claim 18, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 14, wherein the switching circuit comprises a third operational amplifier [Riccardi; Fig. 2, 121], a first switch [Riccardi; Fig. 2, 117], a second switch [Riccardi; Fig. 2, 116; Fig. 4, 118], a third switch [Riccardi; Fig. 2, 119] and a fourth switch [Riccardi; Fig. 2, 118; Fig. 4, 120], wherein the third operational amplifier has a non-inverting input terminal connected to the second switch and the fourth switch via a first node [Riccardi; Fig. 2, node between 116/118 at output 104O; Fig. 4, node between 118/120 at output 104O (see Fig. 2 & 4 above between claims 8-9)], an inverting input terminal, and an output terminal connected to the inverting input terminal and further connected to the first switch and the third switch via a second node [Riccardi; node between 117/119 at output of 121 (see Fig. 2 above between claims 8-9)]; the first switch and the second switch are connected to a drain [Riccardi; Fig. 4, connected thru 142 to the drain] of the first transistor via a third node [Riccardi; Fig. 2, node between 112 and 116; Fig. 4, node between 118 and 142 (see Fig. 2 & 4 above between claims 8-9)]; and the third switch and the fourth switch are connected to a drain [Riccardi; Fig. 4, drain of 150] of the second transistor via a fourth node [Riccardi; Fig. 2, node between 118 and 114; Fig. 4, node between 120 and 150 (see Fig. 2 & 4 above between claims 8-9)].
Regarding Claim 19, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 18, wherein the first node is connected to an input terminal of the loop filter [Riccardi; Fig. 2, node between 116/118 at output 104O; Fig. 4, node between 118/120 at output 104O; where Fig. 1 shows the charge pump output to the input of the loop filter].
Regarding Claim 17, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 11, wherein a magnitude of current of the first current source is regulated by adjusting the first reference voltage [Riccardi; paragraph 0027]; and/or a magnitude of current of the second current source is regulated by adjusting the second reference voltage [Riccardi; paragraph 0028].
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Riccardi, in view of Li , and further in view of Ruegg.
Regarding Claim 15, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 11, wherein the first current source circuit is a charging current source circuit [Riccardi; paragraph 0022; sourcing current] comprising the first variable resistor, the first transistor and the first operational amplifier, wherein the transistor has a source [Riccardi; Fig. 4, 142-source] connected to the voltage input terminal through the first variable resistor, and a drain [Riccardi; Fig. 4, 142-drain] connected to the switching circuit [Riccardi; Fig. 4, indirectly connected]; and the first operational amplifier has an input terminal configured to receive the first reference voltage, an input terminal connected to the source of the transistor [Riccardi; Fig. 4, directly connected to 142-source], and an output terminal connected to a gate of the transistor [Riccardi; Fig. 4, directly connected to 142-gate]. Riccardi, in view of Li, does not explicitly disclose wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor, and the first current source circuit is a charging current source circuit, wherein the PMOS transistor has a source connected to the voltage input terminal through the first resistor, and a drain connected to the switching circuit; and the first operational amplifier has a non-inverting input terminal configured to receive the first reference voltage, an inverting input terminal connected to the source of the PMOS transistor, and an output terminal connected to a gate of the PMOS transistor.
However, Ruegg discloses wherein the first transistor is a P-type Metal-Oxide-Semiconductor (PMOS) transistor [Fig. 4, 402; paragraph 0036], and the first current source circuit [404] is a charging current source circuit [paragraph 0032], wherein the PMOS transistor has a source [ps] connected to the voltage input terminal [VDD, 210] through the first resistor, and a drain [pd] connected to the switching circuit [directly connected to 214]; and the first operational amplifier [410] has a non-inverting input terminal [(+)/413] configured to receive the first reference voltage [paragraph 0037], an inverting input terminal [(-)/415] connected to the source of the PMOS transistor [directly connected to ps], and an output terminal [411] connected to a gate of the PMOS transistor [directly connected to pg]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Ruegg in the invention of Riccardi, in view of Li, with the expected benefit of charging the loop filter. This method of improving Riccardi, in view of Li using Ruegg was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Ruegg. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi, in view of Li and Ruegg to obtain the invention: incorporating a PMOS transistor in the charge pump's charging current source.
Regarding Claim 16, as best understood, Riccardi, in view of Li, discloses the phase-locked loop circuit according to claim 11, wherein the second current source circuit is a discharging current source circuit [Riccardi; paragraph 0022; sinking current] comprising the second variable resistor, the second transistor and the second operational amplifier, wherein the second transistor has a source [Riccardi; Fig. 4, 150-source] grounded through the second variable resistor, and a drain [Riccardi; Fig. 4, 150-drain] connected to the switching circuit [Riccardi; Fig. 4, directly connected to 120]; and the second operational amplifier has an input terminal configured to receive the second reference voltage, an input terminal connected to the source of the second transistor, and an output terminal connected to a gate of the second transistor. Riccardi, in view of Li, does not explicitly disclose wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor, and the second current source circuit is a discharging current source circuit, wherein the NMOS transistor has a source grounded through the second resistor, and a drain connected to the switching circuit; and the second operational amplifier has a non-inverting input terminal configured to receive the second reference voltage, an inverting input terminal connected to the source of the NMOS transistor, and an output terminal connected to a gate of the NMOS transistor.
However, Ruegg discloses wherein the second transistor is a N-type Metal-Oxide-Semiconductor (NMOS) transistor [Fig. 4, 408; paragraph 0033], and the second current source circuit [406] is a discharging current source circuit [paragraph 0032], wherein the second transistor has a source [ns] grounded [VSS, 212] through the second resistor, and a drain [nd] connected to the switching circuit [directly connected to 214]; and the second operational amplifier [420] has a non-inverting input terminal [(+)/423] configured to receive the second reference voltage [paragraph 0033], an inverting input terminal [(-)/425] connected to the source of the second transistor [ns], and an output terminal [421] connected to a gate of the second transistor [ng]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Ruegg in the invention of Riccardi, in view of Li, with the expected benefit of discharging the loop filter. This method of improving Riccardi, in view of Li using Ruegg was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Ruegg. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi, in view of Li and Ruegg to obtain the invention: incorporating a NMOS transistor in the charge pump's discharging current source.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Riccardi, in view of Li, and further in view of Sowlati et al. (US 7091759 B2); hereinafter Riccardi, in view of Li, and further in view of Sowlati .
Regarding Claim 20, as best understood, Riccardi, in view of Li, discloses a phase-locked loop circuit according to claim 11 [see rejection of claim 11 above] . Riccardi, in view of Li, does not explicitly disclose a transceiver that comprises a phase-locked loop circuit.
However, Sowlati discloses a transceiver [Fig. 3, 200] that comprises a phase-locked loop circuit [360]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Sowlati in the invention of Riccardi, in view of Li, with the expected benefit of setting a specific voltage and improving efficiency and stability. This method of improving Riccardi, in view of Li using Sowlati was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Sowlati. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Riccardi, in view of Li and Sowlati to obtain the invention: incorporating a phase-locked loop circuit within a transceiver.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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