DETAILED ACTION
This office action is in response to the application filed on 10/14/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/23/2025 and 10/14/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 1 and 11. Therefore, the “the bypass detector configured to compare the input voltage with a predetermined threshold” and “comparing by a bypass detector, an input voltage of the buck converter to a predetermined threshold” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner’s Note: Bypass detector 160 only receives signal En_bypd.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 13 and 16 are objected to because of the following informalities: Claim 13 line 5 recites “above below” this should be “above”. Claim 16 line 3 “an input voltage” should be “the input voltage”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 7 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu US 2021/0083579.
Regarding Claim 1, Hsu teaches (Figures 1-8) A buck converter (at fig. 2) comprising: a power stage (234-236, 206 and 208) comprising: an input terminal (at Vdd) for receiving an input voltage (Vin); and an output terminal (at Vout) for outputting an output voltage (Vout); a feedback network (next to 222) coupled to the power stage, configured to generate a feedback voltage (sent to 222) according to the output voltage (Vout); a control loop (222 and 220) comprising: an error amplifier (222) configured to generate an EA voltage (from 222) by comparing a reference voltage (Vref) to the feedback voltage; and a comparator (220) coupled to the error amplifier (222), configured to generate a CMP signal (pwm) according to the EA voltage; a logic circuit (212 and 260) coupled to the control loop, configured to generate a logic control signal (Qduty) for implementing a control scheme according to a set of control signals (inputs to 212 and 260); a driver circuit (226 and 230-232) coupled between the logic circuit and the power stage (see Fig. 2), configured to drive the power stage according to the logic control signal; and a bypass detector (242) configured to compare the input voltage with a predetermined threshold related to the output voltage (Vin and Vref) and generate a bypass mode signal (with Ton, par. 36 and 41) accordingly. (For example: Par. 32-42 and 52)
Regarding Claim 4, Hsu teaches (Figures 1-8)wherein the power stage further comprises: a first switch (234) and a second switch (236) coupled in series forming a half bridge configuration between the input terminal and a ground (see fig. 2); an output inductor (206) coupled between a switching node of the first switch and the second switch and the output terminal (see fig. 2); and an output capacitor (208) coupled between the output terminal and the ground. (For example: Par. 32-42 and 52)
Regarding Claim 5, Hsu teaches (Figures 1-8)wherein: the first switch (234) comprises: a first terminal coupled to the input terminal (at Vdd); a second terminal coupled to the switching node (see fig. 2); and a control terminal coupled to the driver circuit (230); and the second switch comprises: a first terminal coupled to the switching node (see fig. 2); a second terminal coupled to the ground (gnd); and a control terminal coupled to the driver circuit (232). (For example: Par. 32-42 and 52)
Regarding Claim 7, Hsu teaches (Figures 1-8) wherein the control loop further comprises: a resistor-capacitor circuit at Vcomp coupled between the error amplifier (222) and a ground (gnd).
Regarding Claim 10, Hsu teaches (Figures 1-8) further comprising a load (connected to Vout) coupled between the output terminal and a ground (gnd).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Hsu US 2019/0081546 (Herein Hsu2).
Regarding Claim 2, Hsu teaches (Figures 1-8) the converter.
Hsu does not teach further comprising: an on-time generator coupled to the logic circuit, configured to generate a first control signal within the set of control signals; and a zero current detector coupled to the logic circuit, configured to generate a second control signal within the set of control signals and a bypass enabling signal to the bypass detector.
Hsu2 teaches (Figures 1-8) an on-time generator (146) coupled to the logic circuit (136-140), configured to generate a first control signal (_Ton) within the set of control signals; and a zero current detector (134 and 142-144) coupled to the logic circuit, configured to generate a second control signal (from Tmax) within the set of control signals and a bypass enabling signal (Ton_ req) to the bypass detector. (For example: Par. 33-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include an on-time generator coupled to the logic circuit, configured to generate a first control signal within the set of control signals; and a zero current detector coupled to the logic circuit, configured to generate a second control signal within the set of control signals and a bypass enabling signal to the bypass detector as taught by Hsu2 to provide a high efficiency, small voltage ripple buck converter having adaptive duty control.
Regarding Claim 11, Hsu teaches (Figures 1-8) A method of operating a buck converter (at fig. 2), comprising: operating the buck converter in a normal mode (normal mode of operation), wherein the normal mode comprises alternating activation of a high-side switch and a low-side switch (234-236) to regulate an output voltage (Vout); monitoring, by a zero current detector (228), a current through an output inductor of the buck converter; comparing, by a bypass detector (at 242), an input voltage (Vin) of the buck converter to a predetermined threshold (vref) related to the output voltage; generating, by the bypass detector, a bypass mode signal (Ton) when the input voltage falls below the predetermined threshold (par. 36 and 41); transitioning the buck converter from the normal mode to a bypass mode according to the bypass mode signal (par. 36-41), wherein the bypass mode comprises the high-side switch being enabled and the low-side switch being disabled (par. 36-41). (For example: Par. 32-42 and 52)
Hsu does not teach generating, by the zero current detector, a bypass enabling signal; enabling the bypass detector according to the bypass enabling signal.
Hsu2 teaches (Figures 1-8) generating, by the zero current detector (134-144), a bypass enabling signal (Ton req); enabling the bypass detector (at 146) according to the bypass enabling signal. (For example: Par. 33-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a generating, by the zero current detector, a bypass enabling signal; enabling the bypass detector according to the bypass enabling signal; as taught by Hsu2 to provide a high efficiency, small voltage ripple buck converter having adaptive duty control.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Hsu US 2019/0081546 (Herein Hsu2) and further in view of Neveu US 2024/0364210.
Regarding Claim 3, Hsu teaches (Figures 1-8) the converter.
Hsu does not teach further comprising: an over-current protection (OCP) circuit, configured to generate an over-current protection signal within the set of control signals; and a large current detection circuit, configured to detect an output current.
Neveu teaches (Figures 1-8) an over-current protection (OCP) circuit (126), configured to generate an over-current protection signal (Noi) within the set of control signals; and a large current detection circuit (125), configured to detect an output current. (For example: Par. 18-21, 29-36 and 42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include an over-current protection (OCP) circuit, configured to generate an over-current protection signal within the set of control signals; and a large current detection circuit, configured to detect an output current as taught by Neveu to provide overcurrent protection to the system.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Arno US 2019/0319540.
Regarding Claim 6, Hsu teaches (Figures 1-8) wherein the feedback network comprises: a feed forward capacitor (capacitor next to the resistor divider) coupled to the output terminal, the resistive divider and the error amplifier (see fig. 2).
Hsu does not teach a hysteresis switch coupled to the output terminal and controlled by the bypass mode signal; a bypass resistor coupled to the output terminal; a resistive divider coupled between the hysteresis switch and a ground.
Arno teaches (Figure 2) a hysteresis switch (206 ) coupled to the output terminal (at vout) and controlled by the bypass mode signal (with F_); a bypass resistor (Rh ) coupled to the output terminal; a resistive divider (R1-R2) coupled between the hysteresis switch and a ground (see fig. 2). (For example: Par. 33-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a hysteresis switch coupled to the output terminal and controlled by the bypass mode signal; a bypass resistor coupled to the output terminal; a resistive divider coupled between the hysteresis switch and a ground, as taught by Arno to reduce current peaks that may risk damaging certain elements of the power supply.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Li US 2020/0266712.
Regarding Claim 8, Hsu teaches (Figures 1-8) the error amplifier (222) comprises: a non-inverting terminal (+) for receiving the reference voltage (Vref); an inverting terminal (-) coupled to the feedback network; a first output terminal (See fig. 2).
Hsu does not teach a second output terminal coupled to the logic circuit.
Li teaches (Figure 3) a second output terminal (at 340) coupled to the logic circuit (350-352 and 350-362). (For example: Par. 33-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a second output terminal coupled to the logic circuit as taught by Li to reduce circuitry area and reduce unwanted audible noise.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Li US 2020/0266712 and further in view of Zhang US 10686381.
Regarding Claim 9, Hsu teaches (Figures 1-8) wherein the comparator (220) comprises: a non-inverting terminal (+) coupled to the first output terminal of the error amplifier; an inverting terminal; and an output terminal coupled to the logic circuit (at 260).
Hsu does not teach a signal terminal coupled to the logic circuit.
Zhang teaches (Figures 3-4) a signal terminal (at 125) coupled to the logic circuit (at sleep terminal). (For example: Col. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a signal terminal coupled to the logic circuit as taught by Zhang to reduce power consumption.
Claim(s) 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Hsu US 2019/0081546 (Herein Hsu2) further in view of Zhang US 10686381.
Regarding Claim 12, Hsu teaches (Figures 1-8) operating in a bypass mode.
Hsu does not teach disabling the bypass detector and a comparator of the buck converter; and monitoring, by an error amplifier of the buck converter, a difference between the feedback voltage and a reference voltage.
Zhang teaches (Figures 3-4) disabling (with sleep) the bypass detector (at 151) and a comparator (125) of the buck converter; and monitoring, by an error amplifier (12) of the buck converter, a difference between the feedback voltage and a reference voltage (Vfb and Vref1). (For example: Col. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a disabling the bypass detector and a comparator of the buck converter; and monitoring, by an error amplifier of the buck converter, a difference between the feedback voltage and a reference voltage as taught by Zhang to reduce power consumption.
Regarding Claim 20, Hsu teaches (Figures 1-8) the buck converter (Fig. 2).
Hsu does not teach further comprising: operating the buck converter in a sleep mode before operating the buck converter in the normal mode, wherein the sleep mode comprises: the high-side switch and the low-side switch being disabled; and the bypass detector and a comparator of the buck converter being disabled.
Zhang teaches (Figures 3-4) further comprising: operating the converter in a sleep mode (sleep mode) before operating the converter in the normal mode (normal operation), wherein the sleep mode comprises: the high-side switch and the low-side switch being disabled (one is fully on and the other is fully off); and the bypass detector (at 151) and a comparator (125) of the buck converter being disabled (sleep signal). (For example: Col. 6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include further comprising: operating the buck converter in a sleep mode before operating the buck converter in the normal mode, wherein the sleep mode comprises: the high-side switch and the low-side switch being disabled; and the bypass detector and a comparator of the buck converter being disabled, as taught by Zhang to reduce power consumption.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over HSU in view of Hsu US 2019/0081546 (Herein Hsu2) and further in view of Itou US 2021/0265914.
Regarding Claim 15, Hsu teaches (Figures 1-8) operating in the bypass mode.
Hsu does not teach disabling an over-current protection (OCP) circuit of the buck converter; and enabling a large current detection circuit of the buck converter.
Itou teaches (Figures 3 and 6) disabling an over-current protection circuit (150-2) of the buck converter (Fig. 3); and enabling a large current detection circuit (150-1) of the buck converter. (For example: Par. 97-104)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Hsu to include a disabling an over-current protection (OCP) circuit of the buck converter; and enabling a large current detection circuit of the buck converter, as taught by Itou to reduce power consumption.
Allowable Subject Matter
Claim 13-14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 13; prior art of record fails to disclose either by itself or in combination: “… further comprising: determining, by the error amplifier, whether the output voltage has risen above the reference voltage by a predetermined margin; and if the output voltage has risen above below the reference voltage by the predetermined margin: generating, by the error amplifier, a bypass out signal; and enabling the comparator of the buck converter.”
Claim 16; prior art of record fails to disclose either by itself or in combination: “…further comprising: monitoring, by the large current detection circuit, a voltage difference between an input voltage and a switching node voltage of the buck converter.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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