Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Amendment dated 7/23/2026.
2. Claims 1-8 and 20 for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-4 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson et al. (“Melanson”), U.S. Patent Publication No. 2015/0372681, Jain et al. (“Jain”), U.S. Patent Application Publication No. 2025/0278568 and Agarwal et al. (“Agarwal”), U.S. Patent Publication No. 2024/0163000.
Regarding Claims 1 and 20, Melanson teaches a device [Fig-1], comprising:
a processing unit (202 included I 118) [Para: 0025(“calibration system 118 may include a processing block 202”)] to:
find at least one value of at least one filter parameter using Bayesian Optimization [Para: 0025(“converting a measured temperature into a corresponding value for compensation signal COMP”)]; and
provide the at least one value of the at least one filter parameter (compensation signal COMP) to a filter [Para: 0025(“processing block 202 … generate compensation signal COMP to be communicated to virtual PLL 116”)] to generate an adjustment to cause clock circuitry to adjust a local clock signal or local clock (LOCAL CLOCK) based on an error signal (ERROR signal) and the at least one value of the at least one filter parameter [Para: 0021(“virtual phase-locked loop (PLL) 116 may receive error signal ERROR, local clock signal LOCAL CLK, and a compensation signal COMP … and generate, … a virtual clock VCLK corrected to compensate for timing error between local clock signal LOCAL CLK and reference clock signal REF CLK and to compensate for temperature deviation of local clock signal LOCAL CLK …”)]; and
a memory (126) to store data used by the processing unit [Para: 0029 and Fig-1].
Melanson does not disclose expressly wherein the finding the value using Bayesian Optimization;
build a model based on measurements of error between a received remote clock and the local clock and corresponding filter parameter values; and
build an acquisition function from the model to find the at least one value of the at least one filter parameter.
In the same field of endeavor (e.g., using Bayesian Optimization process is used for selecting a value), Jain teaches wherein the finding a value using Bayesian Optimization process is used for selecting a value in machine learning model [Para: 0064(“machine learning techniques such as grid search, random search, or Bayesian optimization to find the optimal set of hyperparameters that align the model”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Melanson’s teachings of find at least one value of at least one filter parameter with Jain’s teachings of finding a value using Bayesian Optimization process is used for selecting a value in machine learning model for the purpose of using relatively few model evaluations are required in order to provide an optimized parameter, and can be further parallelized for further increase in efficiency.
Also, in the same field of endeavor (e.g., clock synchronization among plurality of devices), Agarwal teaches a build model [para: 0122(machine learning model)] and wherein
build a model based on measurements of error (“clock drift” or “If a loss of time synchronization information is detected” at 834) between a received remote clock (from leader device 802 “transmit time synchronization information … a time synchronization packet” as “received packet” with clock information at follower device 806) and the local clock (such as “follower hardware clock 812” at follower device 806) and corresponding filter parameter (“clock drift” with in “permissible boundary” where the boundary is defined as “predetermined range” or “threshold” in para 0103-0104, a filter parameter) values [Para: 0171-179 and Fig-8]; and
build an acquisition function [calculating a parameter F(t)] from the model to find the at least one value of the at least one filter parameter [Para: 0135(where F(t) represent the averaged rms drift which corresponds filter parameter value as stated above)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Melanson’s teachings of find at least one value of at least one filter parameter with Agarwal’s teachings of build a model based on measurements of error between a received remote clock and the local clock and corresponding filter parameter values and build an acquisition function from the model would allow Melanson to ensuring or maintaining time-synchronization among a variety of applications and services, a fundamental importance within a network [Agarwal, Para: 0002].
Regarding Claim 2, Melanson teaches claim 1 further comprising:
the clock circuitry including:
an oscillator (oscillator 104) to generate the local clock signal having a clock frequency [Melanson, Para: 0018]; and
a hardware clock (local clock generation circuit 106) to maintain the local clock based on the local clock signal [Melanson, Para: 0018];
the filter to:
receive the error signal between the received reference signal and the local clock [Melanson, Para: 0020(“generate an error signal ERROR … of local clock signal LOCAL CLK in view of reference clock signal REF CLK”)]; and
generate the adjustment to cause the clock circuitry to adjust the local clock signal or the local clock based on the error signal and the at least one value of the at least one filter parameter [Melanson, Para: 0021(“virtual phase-locked loop (PLL) 116 may receive error signal ERROR, local clock signal LOCAL CLK, and a compensation signal COMP … and generate, … a virtual clock VCLK corrected to compensate for timing error between local clock signal LOCAL CLK and reference clock signal REF CLK and to compensate for temperature deviation of local clock signal LOCAL CLK …”)].
Agarwal teaches (1) an error signal between a remote and the local clock (“clock drift” or “If a loss of time synchronization information is detected” at 834 between leader device 802 and follower device 806);
(2) filter the error signal and generate an adjustment to cause the clock circuitry to adjust the local clock signal or the local clock based on the at least one value of the at least one filter parameter [Para: 0171-0174(“if the drift is within a permissible boundary … During the self-synchronization interval, the processor 826 may be configured, 838, to extrapolate the time synchronization … and to continue adjusting the hardware clock 812 and system clock 814”)].
Regarding Claim 3, Since it is directly related to Claim 2 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claim 2 applies equally as well to Claim 3.
Regarding Claim 4, Melanson teaches wherein the processing unit is to dynamically change the at least one value of the at least one filter parameter in order to find the at least one value of the at least one filter parameter which improves the adjustment of the local clock signal or local clock [Para: 0026(“COMP may be determined based on hysteresis of a measure temperature”)].
Allowable Subject Matter
4. Claims 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
5. Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
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